WO2008022162A3 - Systems and methods for program directed memory access patterns - Google Patents

Systems and methods for program directed memory access patterns Download PDF

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Publication number
WO2008022162A3
WO2008022162A3 PCT/US2007/075944 US2007075944W WO2008022162A3 WO 2008022162 A3 WO2008022162 A3 WO 2008022162A3 US 2007075944 W US2007075944 W US 2007075944W WO 2008022162 A3 WO2008022162 A3 WO 2008022162A3
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WO
WIPO (PCT)
Prior art keywords
memory
access
systems
methods
memory access
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Application number
PCT/US2007/075944
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French (fr)
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WO2008022162A2 (en
Inventor
Robert B Tremaine
Original Assignee
Ibm
Robert B Tremaine
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Application filed by Ibm, Robert B Tremaine filed Critical Ibm
Publication of WO2008022162A2 publication Critical patent/WO2008022162A2/en
Publication of WO2008022162A3 publication Critical patent/WO2008022162A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
PCT/US2007/075944 2006-08-15 2007-08-15 Systems and methods for program directed memory access patterns WO2008022162A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/464,503 US7539842B2 (en) 2006-08-15 2006-08-15 Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
US11/464,503 2006-08-15

Publications (2)

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WO2008022162A2 WO2008022162A2 (en) 2008-02-21
WO2008022162A3 true WO2008022162A3 (en) 2008-11-27

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PCT/US2007/075944 WO2008022162A2 (en) 2006-08-15 2007-08-15 Systems and methods for program directed memory access patterns

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US (2) US7539842B2 (en)
WO (1) WO2008022162A2 (en)

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