WO2008025238A1

WO2008025238A1 - Storage device with large capacity and method based on flash memory

Info

Publication number: WO2008025238A1
Application number: PCT/CN2007/002499
Authority: WO
Inventors: Qingyi Lin
Original assignee: Fortune Spring Technology (Shenzhen) Corporation
Priority date: 2006-08-18
Filing date: 2007-08-20
Publication date: 2008-03-06
Also published as: CN1936817A; CN100573435C

Abstract

A storage device with large capacity based on flash memory, adopting master-slave structure, performing communication management with internal communication protocol, comprising external interface, multiple controllers, and semiconductor storage media. And a storing method with large capacity based on flash memory is also provided, including steps of: distributing data to be wrote by a master controller, and transmitting the data and command to each corresponding slave controller one by one according to an internal communication protocol; detecting whether the Ready/Busy signal of each slave controller is set free; when all the Ready/Busy signals corresponding to all the slave controllers are set free, performing next cycle of transmitting of data and command.

Description

Large-capacity storage device and method based on flash memory

The invention belongs to the field of flash memory storage, and in particular relates to a large-capacity storage device and method based on flash memory. Background technique ·

Flash memory and traditional hard drives are the mainstream data storage media on the market today. Among them, the main advantages of flash memory are power saving, small volume, high shock resistance and good reliability. Most of the USB storage disks, MP3 players, PMP personal media players and memory cards on the market use flash memory as a storage medium. It is foreseeable that the application of flash memory will become more and more popular under the trend of emphasizing lightness and shortness.

At present, the flash memory specifications on the market cover many types including SLC (Single level cell), MLC (multi level cell) and AG-NAND. In addition to the differences in specifications, the flash memory has the means and efficiency of reading and writing data. There are also differences. However, the flash memory of SLC. is the highest in terms of read/write efficiency and reliability, but its unit price is high. Therefore, most of the current use of SLC flash memory as the mainstream, but with the continuous decline in product prices, product suppliers have to make some compromises in other areas, and gradually more and more manufacturers using MLC. Flash memory manufacturers have spared no effort in the development of MLC flash memory. Flash memory is increasing at twice the compound growth rate per year.

At present, a small number of manufacturers have begun to develop and replace traditional hard disks with flash memory hard disks. Mainly to focus on its power saving and shock resistance is better than the traditional hard drive. At present, the market share of traditional hard disks is still much higher than that of flash memory hard disks. The main reason is that the cost of early flash memory is too high, the supply is not stable, the transmission rate is slow, and the capacity is low. However, as manufacturers of flash memory continue to invest in development and increase production capacity, and using more advanced technologies, the capacity of flash memory continues to increase and the price is gradually rationalized. Flash memory is no longer limited to Small mobile storage device. Foreseeing that in the next few years, flash memory hard drives will most likely replace traditional hard drives as data storage.

1 Confirmation Mainstream medium.

When the technology of flash memory matures, vendors have begun to think about how to use flash memory for IA products. With the increase in production capacity of flash memory in some large manufacturers such as Samsung and Toshiba, among all mobile storage devices, storage media has the largest share of flash memory. However, the access efficiency of flash memory is generally not high, and there is a problem of capacity limitation, which cannot be used as a storage medium on a large system. The main reason is that the entire flash memory is accessed in addition to the access speed of the flash memory itself. The design of the system is a major issue.

At present, the design structure of the flash memory hard disk mostly controls the flash memory with a single flash memory controller, which can only be applied to a system with a low amount of flash memory. However, in the face of the increasing demand for high-capacity and high-volume flash memory devices in the market, a single flash memory controller system can only control a small amount of flash memory. How to control more flash memory to achieve the capacity of traditional hard disk, how to improve the load frequency when accessing multi-flash memory will reduce the operating frequency, to maintain a higher operating frequency, thus achieving the equivalent of a traditional hard disk The speed is the technology that every manufacturer wants to develop.

In addition to capacity issues, access efficiency is also a key issue. The traditional hard disk has been developed to ULTRA 133, and the data bus bandwidth can reach 133 Mbytes per second, far exceeding the access speed of flash memory. So to replace the traditional hard disk with flash memory, there are still some problems to be overcome.

Therefore, the current flash memory hard disk technology still faces some problems including capacity limitations and poor data transmission efficiency.

At present, because the demand for flash memory memory on the market is not so large, it is costly to open a special IC for this purpose, which is not cost-effective. Therefore, if you can extend the functions of the existing flash memory controller and use external logic to make it meet the needs of the flash memory hard disk, it would be a good choice. Summary of the invention An object of the present invention is to provide a large-capacity storage device based on a flash memory, which aims to solve the problems of poor access speed and capacity expansion of the prior art storage device.

The embodiment of the present invention is implemented by using a flash memory-based mass storage device, adopting a master-slave architecture, and performing communication management through an internal communication protocol to improve storage capacity and performance, including an external interface for replacing a traditional hard disk. Interface, multiple controllers, semiconductor storage media.

Another object of the embodiments of the present invention is to provide a flash memory-based mass storage method, including the following steps: The main controller allocates data to be written, and sequentially sends data and commands according to an internal communication protocol. Each corresponding slave controller; checks whether the Ready/Busy signal of each slave controller has been released; when all the corresponding slave controller's Ready/Busy signals are released, the next round of data and command transmission is performed.

The embodiments of the present invention can be applied to various large-capacity flash memory storage devices to achieve the capacity and transmission speed of the current hard disk, thereby replacing the traditional hard disk. Moreover, the present invention only needs to extend the functions of the existing flash memory controller, and it is not necessary to develop a dedicated flash hard disk controller specifically for this requirement, thereby reducing the development cost and shortening the development cycle. DRAWINGS

1 is a schematic diagram of a controller pin of an embodiment of the present invention;

2 is a basic structural diagram of a multi-flash memory system according to an embodiment of the present invention;

3 is a schematic diagram of a system frequency according to an embodiment of the present invention;

4 is a flowchart of a controller startup according to an embodiment of the present invention;

Figure 5 is a flow chart of a prior art flash memory control;

6 is a flow chart of improving flash memory control according to an embodiment of the present invention;

7 is a flow chart of writing data according to an embodiment of the present invention;

8 is a flow chart of data reading in an embodiment of the present invention;

9 is a signal diagram of a single controller after PCB layout according to an embodiment of the present invention;

FIG. 10 is a signal diagram of a plurality of flash memory multi-load circuit according to an embodiment of the present invention. [Main component symbol description]

100: Control pin of flash memory

101: Master/slave type selection pin

102: Frequency input pin

103: Frequency output pin

104: Pin of ICP signal input

105: Pin of ICP signal output

200: External IDE/CF interface

201: Bus of the internal system

202: Internal communication protocol used for internal communication

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Embodiments of the present invention utilize multiple flash controllers, employing a master-slave architecture control approach to increase capacity limitations and performance.

In these multiple controllers, the master and slave controllers have the same number and defined pins, and the internal logic is the same. The user can use an I/O pin to set whether the controller is master or slave. The master and slave internal communication protocols pass data through Data-in and Data-Out. Its pin definition is shown in Figure 1.

As shown in Figure 2, any controller can know whether it is a master controller by using an external control signal and an operating protocol between multiple chips. The main controller can choose not to connect to the flash memory, but its main purpose is to determine which slave memory to access when receiving the external access command, and then through the unique ICP (Inter- Chip Protocol), sends the accessed command to the slave controller that is responsible for accessing the flash memory, and then the slave controller accesses the data and transmits it back through the system data bus. This system data bus can be 8, 16, or 32 bits. When the system starts, the main controller needs to set the data configuration information of the system. The host controller needs to know the topology of the system, and which controller the flash memory where the external data is to be accessed is controlled by, and how the data is sent to the controller. In this way, the existing controller can be used to easily increase the capacity of the system.

In order to synchronize between the master and multiple slave controllers, the master controller is responsible for providing the frequency to the slave controller, as shown in Figure 3. The frequency of the main controller is from the oscillator outside the system and is obtained via the CLKJN signal. This frequency is divided by the PLL circuit in the controller, and the frequency after division is transmitted to all slave controllers via the CLK_OUT signal.

In addition, because the speed of the IDE and CF interfaces exceeds the storage speed of the flash memory, we need some acceleration mechanism. The speed limit of the flash memory needs to check whether the Ready/Busy of the flash memory has been released when accessing each flash memory. If the flash memory is still in a busy state and Ready/Busy is not put down, it cannot be The action required to write to this part requires a lot of waiting time. As shown in Figure 5, when writing the first controller data, it must be determined that the Ready/Busy signal of the flash memory on the first controller is released before the data can be written to the second slave controller. We use several simultaneous access methods to reduce the performance impact of Ready/Busy, as shown in Figure 6. Assuming that the host controller is to write data to the flash memory on the slave controller, the master controller transfers the commands and data to the slave controller in sequence using the ICP, and the slave controller writes data to the flash memory. After the main transfer is completed, it is checked whether the Ready/Busy signal of each slave controller's corresponding flash memory has been released. If it is released, the next data to be written and the commands are transferred to the slave controller in sequence. The advantage of this approach is that it saves the time it takes to wait for each Ready/Busy signal from the controller to flash.

The system startup process, as shown in Figure 4, each controller will check its own type I/O pin. If the level is high, it means the controller is set as the master controller, otherwise it means this control. The device is set to the slave controller. If the controller is the master controller, in order to take into account the synchronization problem of the system, the operating frequency must be determined first, and the operating frequency is the set value of the user. If the user wants better performance, the operating frequency can be set to a higher value, but when connecting multiple flash controllers to the friend controller, Faced with stability issues. In addition, the problem regarding stability is as shown in Fig. 9. When the control signal output from the basic circuit on the board is normal, a π type is present on the drawing. However, when the load on the circuit is larger, such as when the number of electronic components is too large, the high frequency is considered or attenuated due to the layout of the board. When the load is larger, the waveform is presented on the signal diagram. Taking Figure 10 as an example, when the controller on the board is connected to multiple flash memories, the load on the controller will increase, so the output signal will generate a large high-frequency attenuation and phase shift, so on the signal diagram. Present the wave pattern. Therefore, when this phenomenon occurs, the operating frequency of all controllers needs to be reduced to reduce the high frequency attenuation and phase shift. '

The host controller then needs to know the topology of the system and know which controller controls what data within the logical sector range. Because the master and the slave can have their own management methods, the master cannot know the logical sector data in the slave controller's placement position (flash memory location) and mode, and can only tell the logic fan from the ICP notification. District data. After the topological structure is established, because the host itself can choose whether or not to control the flash memory, if the flash memory is connected, the master itself has both the master and slave functions. At this point, the master needs to initialize some tables, such as the Logical To Physical Translation Table. Finally, only the IDE/CF interface settings and initialization are left, waiting for remote IDE/CF commands to perform data access operations. If the controller is set to slave mode, only some form initialization actions are required, and then the master controller waits for commands transmitted using the internal communication protocol.

The process of writing is shown in Figure 7. When the IDE/CF interface wants to perform a write operation, the host controller will receive this command on the IDE/CF interface (LBA buffer), including the written logical fan. Area and sector length, etc. The master first sets the data length and data location of the DMA buffer (if the IDE/CF interface is in Ultra mode), and then compares the topology data structure established when the system is started, and confirms that the data and logical location need to use ICP for each write. Which slave controllers are sent to. When the external data buffer is filled by the IDE/CF DMA (512 bytes in one sector), the data is transferred to the corresponding slave controller using the internal DMA, and the slave uses its internal A table that writes data to the flash memory to which it is connected.

When all slave controllers are written, all Ready/Busy letters of the slave controller are checked. Whether the number is released, if it is released, the next round of writing can be performed until all the data is written.

The process of reading is shown in Figure 8. When the IDE/CF interface wants to read, the host controller will receive this command on the IDE/CF interface (LBA buffer). This command contains the read command. Logical sector address as well as sector length and so on. The master first sets the DMA buffer (if the IDE/CF interface is in Ultra mode) data length and data location, and then compares the topology data structure established when the system is started, knowing which read operations need to use ICP in which slave control The logical location of the device reads the data. The command and logical sector locations are then sent to all relevant slave controllers, after which the master controller checks if all of the slave controller's Ready Busy have been placed. If it is, it means that all the data in the slave controller is read, and the master controller uses the internal DMA to transfer the read data from the controller to the system buffer, and the master controller then uses the system buffer. Data is transferred to the remote using external DMA.

The signal diagram of a single controller after PCB layout is shown in Figure 9. Figure 10 shows the signal diagram of multiple flash memory multiple load circuits.

In addition, when the controller of the system is connected to a certain amount of flash memory, the noise will be generated due to the accumulation of some electronic components such as the number of capacitors. At this time, the operating frequency of all controllers must be reduced. Because the operating frequency of all controllers is provided by the main controller, the main controller must have a set of circuits that can set the frequency, which can generate multiple sets of frequencies to meet the needs of different amounts of flash memory, to achieve the best performance.

In addition, the common flash controller chip on the market, after controlling a certain amount of flash memory, because of the load capacitance and PCB layout factor, the data bus can maintain the operating frequency when connecting four to eight flash memories. The high rated range can basically maintain the accuracy of the waveform. Beyond this range, it is often necessary to reduce the operating frequency to ensure the accuracy of the waveform. Therefore, multiple independent data buses are used to access a fixed number. Flash memory reduces the complexity of the PCB layout and ensures the accuracy of accessing flash memory to maintain overall high capacity, performance and stability.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalents, and improvements made within the spirit and scope of the present invention should be included in the present invention. Within the scope of protection.

Claims

Rights request

1. A large-capacity storage device based on flash memory, characterized in that:

The device uses a master-slave architecture to communicate management through internal communication protocols to enhance storage capacity and performance, including external interface interfaces to replace traditional hard drives, multiple controllers, and semiconductor storage media.

2. Apparatus according to claim 1 wherein the external interface interface is an IDE/CF interface interface.

3. The device according to claim 1, wherein the device is a SLC/MLC NAND type flash memory, an AGAND type flash memory, an NROM type flash memory or a NOR type flash memory. ·

4. Apparatus according to claim 1 wherein the controller comprises a master controller and at least one slave controller.

5. The apparatus according to claim 4, wherein the master and slave controllers have the same number and defined pins, and the internal logic is also the same; the master and slave controllers should include other pins to control A semiconductor memory component; the master and slave controllers provide at least one I/O pin, and the controller is a master or a slave; the master and slave controllers should also provide at least a Data-in and a Data-Out. Pin, internal communication protocol data transfer for master and slave; The master and slave controllers should also provide at least the CLK_IN and CLK_OUT pins for synchronizing the operating timing of multiple controllers throughout the system.

6. Apparatus according to claim 1 wherein the main controller further comprises a set of circuits for setting the operating frequency for generating sets of frequencies.

7. The device according to any one of claims 1 to 6, wherein the device is a USB flash drive (including but not limited to USB Pendriver 1.1/2.0), a PMP player, a memory card (including but not limited to SD/ MMC/CF/Memory Stick/XD) and MP3 player

8. A flash memory based mass storage method, characterized in that the method comprises the following steps:

The main controller allocates the data to be written, and sends the data and commands sequentially according to the internal communication protocol. To each corresponding slave controller; 'Check if the Ready/Busy signal of each slave controller has been released;

When all the corresponding slave controller's Ready/Busy signals are released, the next round of data and command transmission is performed.

9. The method of claim 8, wherein the method is for a USB flash drive (including but not limited to USB Pendriver 1.1/2.0), a PMP player, a memory card (including but not limited to SD/MMC/CF/ Memory Stick/XD) and MP3 player.