WO2008042109A3 - Structure cluster and method in programmable logic circuit - Google Patents
Structure cluster and method in programmable logic circuit Download PDFInfo
- Publication number
- WO2008042109A3 WO2008042109A3 PCT/US2007/020139 US2007020139W WO2008042109A3 WO 2008042109 A3 WO2008042109 A3 WO 2008042109A3 US 2007020139 W US2007020139 W US 2007020139W WO 2008042109 A3 WO2008042109 A3 WO 2008042109A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- super cluster
- configurations
- criteria
- generate
- dimension
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit, a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/537,744 | 2006-10-02 | ||
US11/537,744 US7757193B2 (en) | 2006-10-02 | 2006-10-02 | Structure cluster and method in programmable logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008042109A2 WO2008042109A2 (en) | 2008-04-10 |
WO2008042109A3 true WO2008042109A3 (en) | 2008-08-21 |
Family
ID=39262490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/020139 WO2008042109A2 (en) | 2006-10-02 | 2007-09-17 | Structure cluster and method in programmable logic circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US7757193B2 (en) |
WO (1) | WO2008042109A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9003222B2 (en) * | 2011-09-30 | 2015-04-07 | International Business Machines Corporation | Configuration fault localization in shared resource environments |
US10628625B2 (en) * | 2016-04-08 | 2020-04-21 | Synopsys, Inc. | Incrementally distributing logical wires onto physical sockets by reducing critical path delay |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6727726B1 (en) * | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
US6847993B1 (en) * | 2000-05-31 | 2005-01-25 | International Business Machines Corporation | Method, system and program products for managing cluster configurations |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3855671T2 (en) * | 1987-02-19 | 1997-05-07 | Yokogawa Medical Syst | DATA PROCESSOR FOR IMAGE RECONSTRUCTION |
US5818726A (en) * | 1994-04-18 | 1998-10-06 | Cadence Design Systems, Inc. | System and method for determining acceptable logic cell locations and generating a legal location structure |
US6609228B1 (en) * | 2000-11-15 | 2003-08-19 | International Business Machines Corporation | Latch clustering for power optimization |
US6795958B2 (en) * | 2001-08-23 | 2004-09-21 | Cadence Design Systems, Inc. | Method and apparatus for generating routes for groups of related node configurations |
US6813754B2 (en) * | 2002-11-05 | 2004-11-02 | Lattice Semiconductor Corporation | Placement processing for programmable logic devices |
US7386823B2 (en) * | 2005-07-20 | 2008-06-10 | Springsoft, Inc. | Rule-based schematic diagram generator |
US7603642B2 (en) * | 2006-09-27 | 2009-10-13 | Cadence Design Systems, Inc. | Placer with wires for RF and analog design |
-
2006
- 2006-10-02 US US11/537,744 patent/US7757193B2/en not_active Expired - Fee Related
-
2007
- 2007-09-17 WO PCT/US2007/020139 patent/WO2008042109A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6847993B1 (en) * | 2000-05-31 | 2005-01-25 | International Business Machines Corporation | Method, system and program products for managing cluster configurations |
US6727726B1 (en) * | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
Also Published As
Publication number | Publication date |
---|---|
WO2008042109A2 (en) | 2008-04-10 |
US20080082951A1 (en) | 2008-04-03 |
US7757193B2 (en) | 2010-07-13 |
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