WO2008050607A1 - Tester, driver comparator chip, response measuring device, calibration method, and calibration device - Google Patents

Tester, driver comparator chip, response measuring device, calibration method, and calibration device Download PDF

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Publication number
WO2008050607A1
WO2008050607A1 PCT/JP2007/069710 JP2007069710W WO2008050607A1 WO 2008050607 A1 WO2008050607 A1 WO 2008050607A1 JP 2007069710 W JP2007069710 W JP 2007069710W WO 2008050607 A1 WO2008050607 A1 WO 2008050607A1
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WO
WIPO (PCT)
Prior art keywords
comparator
waveform
output
driver
time
Prior art date
Application number
PCT/JP2007/069710
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuo Matsubara
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to KR1020097010698A priority Critical patent/KR101138296B1/en
Publication of WO2008050607A1 publication Critical patent/WO2008050607A1/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928Formatter
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/3193Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31932Comparators
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00Testing or calibrating of apparatus covered by the other groups of this subclass

Definitions

  • Test device driver comparator chip, response measuring device, calibration method, and calibration device
  • the present invention relates to a test apparatus, a driver comparator chip, a response measuring apparatus, a calibration method, and a calibration apparatus.
  • the present invention relates to a test apparatus for testing a device under test, a driver comparator chip and a response measuring apparatus provided in the test apparatus.
  • This application is related to the following Japanese application. For designated countries where incorporation by reference of documents is allowed, the contents described in the following application are incorporated into this application by reference and made a part of this application.
  • a test apparatus for testing a semiconductor device or the like includes a comparator that takes an output signal output from a device under test into the test apparatus (see, for example, Patent Document 1).
  • the response time when a rising edge is input may be different from the response time when a falling edge is input. If the response time of the rising edge and the falling edge is different, an error occurs in the measurement timing of the output signal from the device under test, so the test equipment cannot test the device under test with high accuracy. : JP 2000-9801 A
  • an object of the present invention is to provide a test apparatus, a driver comparator chip, a response measuring apparatus, a calibration method, and a calibration apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a test apparatus for testing a device under test the device under test being Connected to the signal generator that generates the test signal to be input to the driver, the driver that outputs the test signal to the input / output pin of the device under test, the output terminal of the driver and the input / output pin of the device under test
  • a comparator that detects the signal
  • a determination unit that determines the pass / fail of the device under test based on the output signal of the device under test detected by the comparator, and a response time for the rising edge of the signal and a response for the falling edge in the comparator
  • a response measuring device that detects a difference from time, and the response measuring device includes a driver output terminal and a comparator.
  • a driver control unit that causes the driver to output an output waveform having a rising edge and a falling edge in a state where the driver is terminated at a predetermined potential via a transmission path having a predetermined propagation delay, and a rising edge of the output waveform
  • the comparator detects the edge, the falling edge of the reflected waveform whose output waveform is reflected by the termination, the falling edge of the output waveform, and the rising edge of the reflected waveform whose output waveform is reflected by the termination
  • a difference calculating unit for calculating a difference in response time based on
  • a driver that outputs a signal, a comparator that detects a given signal, a signal in the comparator, A response measuring device that detects a difference between the response time for the rising edge and the response time for the falling edge, and the response measuring device is a transmission in which the output terminal of the driver and the input terminal of the comparator have a predetermined propagation delay.
  • a driver control unit that causes the driver to output an output waveform having a rising edge and a falling edge in a state terminated at a predetermined potential via a path; The time at which the comparator detects the rising edge of the waveform, the falling edge of the reflected waveform reflected by the end of the output waveform, the falling edge of the output waveform, and the rising edge of the reflected waveform reflected by the end of the output waveform
  • a driver comparator chip having a difference calculation unit for calculating a difference in response time based on
  • a comparator in a driver comparator having a driver that outputs a signal and a comparator that detects a given signal Is a response measuring device that detects the difference between the response time to the rising edge of the signal and the response time to the falling edge, and the output power of the driver and the input power of the comparator via a transmission path having a predetermined propagation delay
  • the driver controller outputs an output waveform having a rising edge S and a falling edge, and the rising edge of the output waveform and the output waveform are reflected by the termination.
  • Reflected waveform falling edge, output waveform falling edge, and output waveform There each rising edge of the reflection wave reflected by the end, based on the time the comparator detects, provide a response measuring device and a difference calculation unit for calculating a difference in response time.
  • an output signal from a device under test included in a test apparatus for testing the device under test is detected.
  • a method for calibrating a comparator which connects an output terminal of a driver that outputs a test signal to a device under test, an input terminal of a comparator, and a transmission path having a predetermined propagation delay, and outputs an output terminal of the driver in the transmission path.
  • the far end to which no signal is connected is connected to a voltage source that generates a signal potential output from the driver, and the driver outputs a first output waveform having a rising edge and a second output waveform having a falling edge.
  • the comparator detects the rising edge of the first output waveform, and then the first output waveform is reflected by the far end. Measure the first time until the comparator detects the falling edge of the reflected waveform of S 1 and the comparator detects the falling edge of the second output waveform. Second time until the comparator detects the rising edge of the second reflected waveform reflected by the edge And a calibration method for calculating the difference in response time based on the difference between the first time and the second time.
  • the test for the purpose of calibrating the comparator provided in the test apparatus by the method related to the fourth aspect A calibration apparatus connected to the apparatus, a voltage source that is provided in the test apparatus and generates a voltage substantially the same as the signal potential output by the driver that outputs a test signal to the device under test, In the transmission path to which the output terminal and the input terminal of the comparator that detects the output signal from the device under test are connected, the far end where the driver output terminal is not connected and the short connection jig that connects the voltage source Provide a calibration device.
  • FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention.
  • FIG. 2 shows a flow of measurement and adjustment processing of the response time of the comparator 16 by the response measuring device 20.
  • FIG. 3 shows an example of the input signal waveform and output signal waveform of comparator 16 when driver 14 outputs a rising edge, and (B) shows the edge of driver S falling edge S An example of the input signal waveform and output signal waveform of comparator 16 when output is shown.
  • FIG.5 Time interval force from driver 14 output of rising edge to output of falling edge Shows an example of input signal waveform of comparator 16 when the propagation delay time in transmission path 30 is less than twice .
  • FIG. 6 shows a configuration of a test apparatus 10 according to a first modification of the embodiment of the present invention.
  • FIG. 7 shows a configuration of a test apparatus 10 according to a second modification of the embodiment of the present invention.
  • FIG. 8 shows a configuration of a test apparatus 10 according to a third modification of the embodiment of the present invention.
  • FIG. 9 shows an example of the output waveform of the driver 14 and the reflected waveform of the transmission path 30 in the test apparatus 10 according to the fourth modification of the embodiment of the present invention.
  • FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment.
  • the test apparatus 10 is an apparatus for testing a device under test, and includes a signal generation unit 12, a driver 14, a comparator 16, a determination unit 18, and a response measurement device 20.
  • the signal generator 12 generates a test signal to be input to the device under test.
  • the signal generator 12 may include a pattern generator, a timing generator, and a waveform shaper.
  • the pattern generator generates a test pattern that is the source of the test signal, a waveform mode signal that specifies the waveform mode, an expected value pattern that is used for pass / fail judgment, and other signals.
  • the timing generator generates a timing signal that defines the timing of the leading and trailing edges of the waveform supplied to the device under test. For example, the timing generator generates a timing signal that defines the rising force or falling edge of the test signal to be generated, and also generates a strobe signal for timing determination by the comparator 16.
  • the wave shaper receives the test pattern output from the pattern generator, and generates a test signal shaped into a predetermined waveform based on the waveform mode signal from the pattern generator.
  • the driver 14 outputs a test signal to the input / output pins of the device under test. dry
  • the node 14 receives the test signal generated by the signal generation unit 12 and supplies a driver signal converted into amplitudes of predetermined VH level and VL level to the device under test via the signal terminal 22.
  • the comparator 16 is connected to the output terminal of the driver 14 and the input / output pins of the device under test, and detects a given signal.
  • the comparator 16 includes an analog comparator and a timing comparator.
  • the analog comparator receives the analog signal and converts it into two logic signals of high level and low level based on the threshold values VOH and VOL of a predetermined level.
  • the timing comparator receives two logic signals of high level and low level, individually determines the timing at the timing based on the strobe signal from the signal generator 12, and outputs the result.
  • the determination unit 18 determines pass / fail of the device under test based on the output signal of the device under test detected by the comparator 16. For example, the determination unit 18 determines pass / fail of the device under test based on the data whose timing is determined by the comparator 16 and the expected value pattern from the signal generation unit 12.
  • the response measuring device 20 detects a difference between the response time with respect to the rising edge of the signal and the response time with respect to the falling force S edge in the comparator 16. Then, the response measurement device 20 adjusts the response time of the comparator 16 based on the detected difference in response time of the comparator 16. More specifically, the response measuring device 20 has a period from the time when the falling edge is input to the input terminal of the comparator 16 to the time when the comparator 16 outputs a signal corresponding to the falling edge (falling force response). Time T) and comparator 1
  • the response measuring device 20 matches the rising response time T and the falling response time T of the comparator 16 based on the detected response time difference.
  • the comparator 16 is adjusted.
  • the response measurement device 20 includes a driver control unit 32, a first measurement unit 34, a second measurement unit 36, a difference calculation unit 38, and an adjustment unit 40.
  • the driver control unit 32 is configured such that the output terminal of the driver 14 and the input terminal of the comparator 16 are grounded via a transmission path 30 having a predetermined propagation delay.
  • the driver 14 is caused to output a first output waveform having a rising edge and a second output waveform having a falling force edge.
  • the driver control unit 32 outputs a first output waveform and a second output waveform from the driver 14 by causing the signal generation unit 12 to output a predetermined test pattern.
  • the output terminal of the driver 14 and the input terminal of the comparator 16 may be terminated (for example, short-circuited) to a predetermined potential other than the ground potential via the transmission path 30.
  • the transmission path 30 is short-circuited to the ground potential via a far-end force short connection jig in which the output terminal of the driver 14 and the input terminal of the comparator 16 are not connected.
  • the far end of the transmission path 30 is short-circuited to a voltage source that generates substantially the same voltage as the signal potential output from the driver 14 (for example, a no-level potential or a low-level potential) via a short connection jig. Good.
  • the transmission path 30 is a transmission path that connects between the device under test and the driver 14 and the comparator 16 and includes, for example, a printed circuit board having a characteristic impedance of 50 ⁇ , a coaxial cable, a coaxial connector, and the like. It's okay.
  • the transmission path 30 may be connected to the IC terminal of the device under test at the far end during a device test, and connected to a ground potential with a short connection jig at the far end instead of the device under test during measurement.
  • the short connection jig may be short-circuited between the far end of the transmission path 30 and the ground potential in the performance board! /, And grounded to the far end of the transmission path 30 in the socket board.
  • the potential may be short-circuited, or the far end of the transmission path 30 and the ground potential may be short-circuited in a dummy device that contacts the IC socket.
  • the test apparatus 10 includes a voltage source that generates substantially the same voltage as the signal potential output from the driver 14 (for example, a high level potential or a low level potential), and an output terminal of the driver 14 in the transmission path 30.
  • a calibration device such as a performance board, provided with a short connection jig for connecting the far end not connected to the voltage source may be connected.
  • the first measurement unit 34 causes the first reflected waveform to be reflected by the end of the transmission path 30. Measure the first time T until comparator 16 detects the falling edge. No. 2 After the comparator 16 detects the falling edge of the second output waveform, the measuring unit 36 detects the rising edge of the second reflected waveform that is reflected by the end of the transmission path 30 by the comparator 16. Measure the second time T until detection.
  • the difference calculation unit 38 compares the difference between the first time T and the second time T with a comparator.
  • the difference calculation unit 38 determines the rise response time T of the comparator 16 and the rise time based on the measurement time of the first time T and the second time T.
  • the adjustment unit 40 determines the response time T with respect to the rising edge in the comparator 16 or the rise time in the comparator 16 based on the difference in response time calculated by the difference calculation unit 38.
  • the adjustment unit 40 is
  • the measurement of the first time T1 or the second time T2 is controlled.
  • the adjustment unit 40 repeatedly generates a test signal for a long period that the reflected waveform disappears for the purpose of detecting a rising edge or a falling edge. Then, the adjustment unit 40 detects the edge point while sequentially changing the timing of the strobe signal generated from the signal generation unit 12 in the state where the test signal is generated in this way.
  • the adjustment unit 40 uses the rise response time T and the fall response time.
  • the timing of the strobe signal generated from the signal generator 12 is adjusted so that
  • the adjustment unit 40 can reduce the timing error between the rising edge and the falling edge of the comparator 16 during the device test.
  • FIG. 2 shows a measurement and calibration flow of the response time of the comparator 16 by the response measuring device 20.
  • Fig. 3 (A) shows an example of the input signal waveform and output signal waveform of the comparator 16 when the driver 14 outputs a rising edge
  • Fig. 3 (B) shows the output of the falling edge of the driver 14
  • An example of the input signal waveform and the output signal waveform of the comparator 16 is shown.
  • the response measuring apparatus 20 executes the calibration process from step S210 to step S214, for example, prior to the test of the device under test.
  • the response measuring device 20 terminates the output end of the driver 14 and the input end of the comparator 16 to the ground potential by connecting, for example, a short connection jig to the far end of the transmission path 30 having a predetermined propagation delay.
  • Step S210 the response measuring apparatus 20 replaces the performance board on which the device under test is placed with a performance board provided with a short connection jig that connects the far end of the transmission path 30 to the ground potential.
  • the output terminal of the driver 14 and the input terminal of the comparator 16 are terminated to the ground potential via the transmission path 30.
  • step S211 the response measuring device 20 measures a first time T as shown in FIG. 3A, for example (step S211).
  • the driver control unit 32 causes the driver 14 to output a first output waveform having a rising edge at a designated time t311. That is, the output level of the driver 14 transitions from VL to VH.
  • the first output waveform output from the driver 14 force is input to the comparator 16.
  • the time from when the output waveform is output from the driver 14 to when it is input to the comparator 16 is 0 for convenience of explanation, but there is no problem even if there is a time difference.
  • Comparator 16 receives the first output waveform at time t312 delayed by rise response time T from time t311 when the rising edge of the first output waveform output from driver 14 is input.
  • the response measuring apparatus 20 repeatedly generates the waveform of FIG. 3A from the driver 14 for a period sufficient to search for the edge point.
  • the first output waveform having the rising edge output from the driver 14 is also input to the transmission path 30.
  • the transmission path 30 transmits the input output waveform to the termination side, and reflects the reflected waveform by the termination grounded by the connection line of approximately 0 ⁇ .
  • the test apparatus 10 when the low-level potential VL is other than 0 volt (ground potential), the test apparatus 10 includes a voltage source that generates the VL voltage, and terminates the transmission path 30 by connecting it to the VL voltage.
  • the reflected waveform reflected at the end is a waveform in which the polarity of the output waveform output from the driver 14 is inverted because the end of the transmission path 30 is connected to the ground potential! /. That is, the rising edge becomes a falling edge by being reflected at the grounded terminal, and the falling edge becomes a rising edge by being reflected at the grounded terminal. Therefore, the comparator 16 inputs the first reflected waveform having the falling edge from the transmission path 30 after the time for reciprocating the transmission path 30 has elapsed.
  • the driver 14 has an internal resistance of 50 ⁇ , for example. Also, the distance of transmission path 30 The end is short-circuited to the VL voltage. As a result, the output terminal of the driver 14 is forcibly set to a DC VL level although it outputs the VH level.
  • Comparator 16 compares the time t311 when driver 14 outputs the rising edge of the first output waveform with a time T that is twice the propagation delay time T in transmission path 30.
  • the falling edge of the first reflected waveform is input. Subsequently, the comparator 16 detects the falling edge of the first reflected waveform at the time t314 delayed by the falling response time T from the time t313 when the falling edge of the first reflected waveform is input.
  • the time from when the output waveform is output from the driver 14 until the force is input to the transmission path 30 and the time from when the reflected waveform is output from the transmission path 30 to when it is input to the comparator 16 are 0. It is the same even if there is a force S and time difference indicating a certain case.
  • the first measurement unit 34 detects the falling edge of the first reflected waveform reflected by the transmission path 30 from the time t312 when the rising edge of the first output waveform output from the driver 14 is detected. Measure the first time T until the detected time t314.
  • the response measuring apparatus 20 measures a second time T as shown in FIG. 3B, for example (
  • Step S212 the far end of the transmission path 30 reflects the reflected waveform by the end grounded by the connection line of approximately 0 ⁇ .
  • the test apparatus 10 includes a voltage source that generates a VH voltage, and terminates the transmission path 30 by connecting it to the VH voltage.
  • the driver control unit 32 causes the driver 14 to output the second output waveform having the falling edge at a time t321 different from the time t311 when the rising edge of the first output waveform is output. . That is, the output level of the driver 14 transitions from VH to VL.
  • the second output waveform output from the driver 14 is input to the comparator 16.
  • Comparator 16 outputs the second output waveform at time t322, which is delayed by the falling response time T from time t321, when the falling edge of the second output waveform output from driver 14 is input.
  • the response measuring apparatus 20 repeatedly generates the waveform of FIG. 3B from the driver 14 for a period sufficient to search for the edge point.
  • the second output waveform having the falling edge output from the driver 14 is also input to the transmission path 30.
  • the comparator 16 inputs the second reflected waveform having a rising edge from the transmission path 30.
  • Comparator 16 compares the second output waveform at time t323, which is delayed by time T that is twice the propagation delay time T in transmission path 30 from time t321 when driver 14 outputs the falling edge of the second output waveform. Reflected wave
  • the driver 14 has an internal resistance of 50 ⁇ , for example.
  • the far end of the transmission path 30 is short-circuited to the VH voltage.
  • the output terminal of the driver 14 is forcibly set to the DC VH level even though the VL level is output.
  • the comparator 16 outputs the second reflected waveform.
  • the second measurement unit 36 detects the rising edge of the second reflected waveform reflected by the transmission path 30 from the time t322 when the falling edge of the second output waveform output from the driver 14 is detected. Second time T up to t324
  • step S211 and step S212 determines the response time in the comparator 16 based on the difference between the first time T and the second time T.
  • the first time T is from time t311 when the rising edge of the first output waveform is input by the comparator 16 to time t313 when the falling edge S of the first reflected waveform is input by the comparator 16
  • the rise response time T is shorter than the period (that is, the time T twice the propagation delay time in the transmission path 30).
  • the comparator 16 enters the falling edge of the second output waveform.
  • the second time T is represented by T T + T.
  • the difference calculation unit 38 calculates the difference in response time ( ⁇ - ⁇ ) as the following equation (2).
  • the adjusting unit 40 adjusts the comparator 16 based on the difference in response time calculated in step S213 so that the difference in response time becomes substantially zero (step S214). For example, the adjustment unit 40 can correct the delay by adjusting the delay amount of the strobe signal supplied from the signal generation unit 12 to the comparator 16.
  • the driver 14 already provided without using the external reference driver to supply the rising edge and falling force S to the comparator 16 for testing is used.
  • the response time of the comparator 16 can be adjusted. Therefore, according to the test apparatus 10, the characteristics of the comparator 16 can be corrected at any time, and the device under test can be tested with high accuracy.
  • FIG. 4 shows that the time interval force S from when the driver 14 outputs the rising edge to the output of the falling edge S is greater than twice the propagation delay time in the transmission path 30.
  • An example of an input signal waveform is shown.
  • Figure 5 shows an example of the input signal waveform of the comparator 16 when the time interval from when the driver 14 outputs a rising edge to when it outputs a falling edge is less than twice the propagation delay time in the transmission path 30. Show.
  • the driver control unit 32 causes the driver 14 to continuously output the first output waveform and the second output waveform at a predetermined time interval.
  • the driver control unit 32 is a time interval at which the driver 14 outputs a rising edge and a second output waveform falling edge of the first output waveform.T force propagation delay time in the transmission path 30 Twice T
  • the driver 14 is controlled so as to be larger than T.
  • the first measurement unit 34 measures the pulse width having the rising edge of the first output waveform and the falling edge of the first reflected waveform as the first time T. Determine. In other words, the first measurement unit 34 starts the measurement, and the comparator 16 The time between the first edge detected in step 2 and the second edge detected second is measured as the first time. Then, the second measuring unit 36 uses the width of the noise having the falling edge of the second output waveform and the rising edge of the second reflected waveform as the second time T.
  • the second measuring unit 36 sets the time between the third edge detected by the comparator 16 after the start of measurement and the fourth edge detected fourth as the second time T. taking measurement.
  • the driver control unit 32 outputs a time interval T power transmission that outputs a rising edge of the first output waveform and a falling edge of the second output waveform.
  • Driver 14 is adjusted so that it is smaller than time T, which is twice the propagation delay time T in transmission path 30.
  • the first measuring unit 34 measures the pulse width having the rising edge of the first output waveform and the falling edge of the first reflected waveform as the first time T. That is, the first measurement unit 34 measures the time between the first edge detected by the comparator 16 first after the start of measurement and the third edge detected third as the first time T. To do. Then, the second measurement unit 36 measures the pulse width having the falling edge of the second output waveform and the rising edge of the second reflected waveform as the second time T. That is, the second measuring unit 36 starts the measurement and then compares the comparator 16
  • the time between the second edge detected for the third time and the fourth edge detected for the fourth time is measured as the second time T.
  • FIG. 6 shows a configuration of the test apparatus 10 according to the first modification example of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
  • the test apparatus 10 is a configuration example including a driver comparator chip 50 including a driver 14, a comparator 16, and a response measuring apparatus 20.
  • the driver comparator chip 50 is obtained by integrating the driver 14, the comparator 16, and the response measuring device 20 on a semiconductor chip, a module, or a substrate.
  • the response measurement apparatus 20 can be provided for each pin resource in which the driver 14 and the comparator 16 are provided.
  • the set of the driver 14, the comparator 16, and the response measurement apparatus 20 is simplified in the test apparatus 10. Can be implemented.
  • the response measurement device 20 further includes a difference storage unit 56.
  • the difference storage unit 56 holds a value corresponding to the difference in response time calculated at the time of adjustment.
  • the adjustment unit 40 refers to the value held in the difference storage unit 56, and the rising response time T and the comparator 16
  • the latest measurement results obtained by regular adjustment can be held, so even if the response time of the comparator 16 changes with time, the response time between the rising edge and falling edge It can be adjusted so that there is no deviation.
  • FIG. 7 shows a configuration of the test apparatus 10 according to the second modification example of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
  • the response measuring device 20 further includes a switch 62 and a switch control unit 64.
  • the switch 62 switches whether the transmission path 30 connecting the driver 14 and the comparator 16 and the device under test is connected to the device under test or the ground potential! That is, the switch 62 connects the output end of the driver 14 and the input end of the comparator 16 to the device under test via the transmission path 30, and the transmission path 30 connects the output end of the driver 14 and the input end of the comparator 16. Switch between grounding through.
  • the switch 62 may be mounted on a HiFix or performance board.
  • the switch 62 may be mounted on the pin electronics board. Further, the switch 62 may be a semiconductor switch when a semiconductor switch is applicable.
  • the switch control unit 64 switches and controls the switch 62.
  • the switch control unit 64 controls the transmission path 30 to be connected to the input / output pin of the device under test during the test, and to connect the transmission path 30 to the ground potential during the adjustment.
  • the response time of the comparator 16 can be adjusted using the transmission path 30 used in the test.
  • the response measurement device 20 may further include a path length calculation unit 66.
  • Path length calculator 66 Is the propagation delay in transmission path 30 based on the first time T and the second time ⁇
  • the propagation delay time T is T / 2. From this, the propagation delay time ⁇ is
  • the path length calculation unit 66 determines the propagation delay time T as the first time T and the second time T.
  • the propagation delay time T of the transmission path 30 used in the test can be calculated.
  • test apparatus 10 includes the response measurement apparatus 20 for each pin resource, the propagation delay time T of the transmission path 30 can be calculated for each pin, for example.
  • FIG. 8 shows a configuration of a test apparatus 10 according to a third modification of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
  • the test apparatus 10 includes a plurality of sets of dryers 14 and comparators 16 extending to several thousand channels, and a plurality of response measuring apparatuses 20 corresponding one-to-one to the respective drivers 14 and comparators 16.
  • the plurality of response measuring apparatuses 20 may include a common driver control unit 32. That is, the test apparatus 10 includes a plurality of first measurement units 34, a plurality of second measurement units 36, a plurality of second measurement units 36, and an adjustment unit 40 that correspond one-to-one to a plurality of sets of drivers 14 and comparators 16. May be provided.
  • the driver control unit 32 causes the plurality of drivers 14 to output signals substantially simultaneously. Then, the plurality of response measuring devices 20 calculate the difference between the response times of the plurality of comparators 16 in parallel, and adjust the response times of the plurality of comparators 16 in parallel. Thus, according to the test apparatus 10, the force S can be adjusted to adjust the response times of the plurality of comparators 16 in a short time.
  • the test apparatus 10 further includes, as an example, an inter-pin timing control unit 70 that adjusts an inter-comparator skew between a plurality of sets of drivers 14 and comparators 16. Good.
  • the inter-pin timing control unit 70 may adjust the inter-comparator skew after each of the plurality of response measuring devices 20 individually adjusts the response time of the comparator 16. According to this, as a result of adjusting the inter-comparator skew with respect to both the rising edge and the falling edge between the plurality of comparators 16, it is possible to realize a device test with high accuracy timing.
  • FIG. 9 shows an example of the output waveform of the driver 14 and the reflected waveform of the transmission path 30 in the test apparatus 10 according to the fourth modification of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as those in FIG. 1, the description thereof will be omitted except for the following differences.
  • An output can be generated that is shorter than the propagation delay time reflected by path 30 and returning.
  • the driver control unit 32 is in a state where the output end of the driver 14 and the input end of the comparator 16 are terminated to the ground potential via the transmission path 30 having a predetermined propagation delay! /,
  • the driver 14 outputs an output waveform having a rising edge and a falling edge.
  • the transmission path 30 outputs a reflected pulse waveform that is an inverted waveform of the output pulse waveform after a predetermined time.
  • the first measurement unit 34 measures the pulse width T of the output waveform detected by the comparator 16.
  • the second measuring unit 36 reflects the output waveform at the end and is input to the comparator 16 and measures the pulse width T of the reflected waveform detected by the comparator 16.
  • the difference calculating unit 38 calculates the pulse width T of the output pulse waveform and the pulse width of the reflected pulse waveform.
  • the difference in response time is calculated.
  • the difference calculation unit 38 responds.
  • the difference in answer time may be calculated as 1/2 of the difference between the first time T and the second time T.
  • the response time of the comparator 16 can be adjusted using the driver 14 already provided, similarly to the test apparatus 10 shown in FIG.

Abstract

A response measuring device (20) in which the output end of a driver (14) and the input end of a comparator (16) are terminated at the earth potential through a transmission path (30). The device (20) comprises a driver control section (32) for outputting a first output waveform having a rising edge and a second output waveform having a falling edge and a difference calculating section (38) for calculating the difference between the response times according to the difference between a first time from when a comparator (16) detects the rising edge of the first output waveform until when the comparator (16) detects the falling edge of a first reflection wave produced when the first output waveform is reflected by the termination and a second time from when the comparator (16) detects the falling edge of the second output waveform until when the comparator (16) detects the rising edge of a second reflection waveform produced when the second output waveform is reflected by the termination.

Description

明 細 書  Specification
試験装置、ドライバコンパレータチップ、応答測定装置、校正方法および 校正装置  Test device, driver comparator chip, response measuring device, calibration method, and calibration device
技術分野  Technical field
[0001] 本発明は、試験装置、ドライバコンパレータチップ、応答測定装置、校正方法およ び校正装置に関する。特に本発明は、被試験デバイスを試験する試験装置、当該試 験装置に備えられるドライバコンパレータチップおよび応答測定装置に関する。本出 願は、下記の日本出願に関連する。文献の参照による組み込みが認められる指定国 については、下記の出願に記載された内容を参照により本出願に組み込み、本出願 の一部とする。  [0001] The present invention relates to a test apparatus, a driver comparator chip, a response measuring apparatus, a calibration method, and a calibration apparatus. In particular, the present invention relates to a test apparatus for testing a device under test, a driver comparator chip and a response measuring apparatus provided in the test apparatus. This application is related to the following Japanese application. For designated countries where incorporation by reference of documents is allowed, the contents described in the following application are incorporated into this application by reference and made a part of this application.
1. 特願 2006— 289780 出願曰 2006年 10月 25曰  1. Patent application 2006— 289780 Filing date October 25, 2006
背景技術  Background art
[0002] 半導体デバイス等を試験する試験装置は、被試験デバイスから出力された出力信 号を当該試験装置内に取り込むコンパレータを備える(例えば、特許文献 1参照。)。 コンパレータは、立ち上がりエッジを入力した時の応答時間と、立ち下がりエッジを入 力した時の応答時間とが異なる場合がある。立ち上がりエッジおよび立ち下がりエツ ジの応答時間が異なる場合、被試験デバイスからの出力信号の測定タイミングに誤 差が生じるので、試験装置は、被試験デバイスを精度良く試験をすることができない 特許文献 1 :特開 2000— 9801号公報  [0002] A test apparatus for testing a semiconductor device or the like includes a comparator that takes an output signal output from a device under test into the test apparatus (see, for example, Patent Document 1). The response time when a rising edge is input may be different from the response time when a falling edge is input. If the response time of the rising edge and the falling edge is different, an error occurs in the measurement timing of the output signal from the device under test, so the test equipment cannot test the device under test with high accuracy. : JP 2000-9801 A
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0003] ところで、試験装置は、立ち上力 Sりエッジ波形および立ち下がりエッジ波形を外部の 基準ドライバから出力させてコンパレータの応答時間を測定し、測定結果に基づき当 該コンパレータの応答時間を調整していた。しかし、このような調整をする試験装置 は、外部の基準ドライバを用いて、位相のずれが非常に小さい立ち上がりエッジ波形 および立ち下がりを発生しなければならな!/、ので、測定が容易ではなかった。 [0004] そこで本発明は、上記の課題を解決することのできる試験装置、ドライバコンパレー タチップ、応答測定装置、校正方法および校正装置を提供することを目的とする。こ の目的は請求の範囲における独立項に記載の特徴の組み合わせにより達成される。 また従属項は本発明の更なる有利な具体例を規定する。 [0003] By the way, the test device outputs the rising force S edge waveform and the falling edge waveform from the external reference driver, measures the response time of the comparator, and adjusts the response time of the comparator based on the measurement result. Was. However, a test device that makes such adjustments must use an external reference driver to generate rising edge waveforms and falling edges with very little phase shift! /, So measurement is not easy. It was. Accordingly, an object of the present invention is to provide a test apparatus, a driver comparator chip, a response measuring apparatus, a calibration method, and a calibration apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.
課題を解決するための手段  Means for solving the problem
[0005] 上記課題を解決するために、本明細書に含まれるイノベーションに関連する第 1の 側面による試験装置の一つの例によると、被試験デバイスを試験する試験装置であ つて、被試験デバイスに入力すべき試験信号を生成する信号生成部と、試験信号を 被試験デバイスの入出力ピンに対して出力するドライバと、ドライバの出力端及び被 試験デバイスの入出力ピンに接続され、与えられる信号を検出するコンパレータと、 コンパレータが検出した被試験デバイスの出力信号に基づいて、被試験デバイスの 良否を判定する判定部と、コンパレータにおける、信号の立ち上がりエッジに対する 応答時間と、立ち下がりエッジに対する応答時間との差を検出する応答測定装置と を備え、応答測定装置は、ドライバの出力端及びコンパレータの入力端力 所定の 伝播遅延を有する伝送経路を介して所定電位に終端された状態において、ドライバ に、立ち上がりエッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ 制御部と、出力波形の立ち上がりエッジ、出力波形が終端により反射された反射波 形の立ち下がりエッジ、出力波形の立ち下がりエッジ、および出力波形が終端により 反射された反射波形の立ち上がりエッジのそれぞれを、コンパレータが検出する時 刻に基づいて、応答時間の差を算出する差分算出部とを有する試験装置を提供す In order to solve the above problem, according to one example of the test apparatus according to the first aspect related to the innovation included in the present specification, a test apparatus for testing a device under test, the device under test being Connected to the signal generator that generates the test signal to be input to the driver, the driver that outputs the test signal to the input / output pin of the device under test, the output terminal of the driver and the input / output pin of the device under test A comparator that detects the signal, a determination unit that determines the pass / fail of the device under test based on the output signal of the device under test detected by the comparator, and a response time for the rising edge of the signal and a response for the falling edge in the comparator A response measuring device that detects a difference from time, and the response measuring device includes a driver output terminal and a comparator. Force end force A driver control unit that causes the driver to output an output waveform having a rising edge and a falling edge in a state where the driver is terminated at a predetermined potential via a transmission path having a predetermined propagation delay, and a rising edge of the output waveform When the comparator detects the edge, the falling edge of the reflected waveform whose output waveform is reflected by the termination, the falling edge of the output waveform, and the rising edge of the reflected waveform whose output waveform is reflected by the termination And a difference calculating unit for calculating a difference in response time based on
[0006] 本明細書に含まれるイノベーションに関連する第 2の側面によるドライバコンパレー タチップの一つの例によると、信号を出力するドライバと、与えられる信号を検出する コンパレータと、コンパレータにおける、信号の立ち上がりエッジに対する応答時間と 、立ち下がりエッジに対する応答時間との差を検出する応答測定装置とを備え、応答 測定装置は、ドライバの出力端及びコンパレータの入力端が、所定の伝播遅延を有 する伝送経路を介して所定電位に終端された状態において、ドライバに、立ち上がり エッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ制御部と、出力 波形の立ち上がりエッジ、出力波形が終端により反射された反射波形の立ち下がり エッジ、出力波形の立ち下がりエッジ、および出力波形が終端により反射された反射 波形の立ち上がりエッジのそれぞれを、コンパレータが検出する時刻に基づいて、応 答時間の差を算出する差分算出部とを有するドライバコンパレータチップを提供する [0006] According to one example of a driver comparator chip according to the second aspect related to the innovation included in the present specification, a driver that outputs a signal, a comparator that detects a given signal, a signal in the comparator, A response measuring device that detects a difference between the response time for the rising edge and the response time for the falling edge, and the response measuring device is a transmission in which the output terminal of the driver and the input terminal of the comparator have a predetermined propagation delay. A driver control unit that causes the driver to output an output waveform having a rising edge and a falling edge in a state terminated at a predetermined potential via a path; The time at which the comparator detects the rising edge of the waveform, the falling edge of the reflected waveform reflected by the end of the output waveform, the falling edge of the output waveform, and the rising edge of the reflected waveform reflected by the end of the output waveform A driver comparator chip having a difference calculation unit for calculating a difference in response time based on
[0007] 本明細書に含まれるイノベーションに関連する第 3の側面による応答測定装置の一 つの例によると、信号を出力するドライバと、与えられる信号を検出するコンパレータ とを有するドライバコンパレータにおける、コンパレータの信号の立ち上がりエッジに 対する応答時間と、立ち下がりエッジに対する応答時間との差を検出する応答測定 装置であって、ドライバの出力端及びコンパレータの入力端力 所定の伝播遅延を 有する伝送経路を介して所定電位に終端された状態において、ドライバに、立ち上 力 Sりエッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ制御部と、出 力波形の立ち上がりエッジ、出力波形が終端により反射された反射波形の立ち下が りエッジ、出力波形の立ち下がりエッジ、および出力波形が終端により反射された反 射波形の立ち上がりエッジのそれぞれを、コンパレータが検出する時刻に基づいて、 応答時間の差を算出する差分算出部とを備える応答測定装置を提供する。 [0007] According to one example of a response measurement apparatus according to the third aspect related to the innovation included in the present specification, a comparator in a driver comparator having a driver that outputs a signal and a comparator that detects a given signal Is a response measuring device that detects the difference between the response time to the rising edge of the signal and the response time to the falling edge, and the output power of the driver and the input power of the comparator via a transmission path having a predetermined propagation delay In this state, the driver controller outputs an output waveform having a rising edge S and a falling edge, and the rising edge of the output waveform and the output waveform are reflected by the termination. Reflected waveform falling edge, output waveform falling edge, and output waveform There each rising edge of the reflection wave reflected by the end, based on the time the comparator detects, provide a response measuring device and a difference calculation unit for calculating a difference in response time.
[0008] 本明細書に含まれるイノベーションに関連する第 4の側面による校正方法の一つの 例によると、被試験デバイスを試験する試験装置に備えられた、被試験デバイスから の出力信号を検出するコンパレータの校正方法であって、被試験デバイスに対して 試験信号を出力するドライバの出力端、コンパレータの入力端および所定の伝播遅 延を有する伝送経路を接続するとともに、伝送経路におけるドライバの出力端が接続 されていない遠端をドライバから出力される信号電位を発生する電圧源に接続し、ド ライバから、立ち上がりエッジを有する第 1の出力波形と立ち下がりエッジを有する第 2の出力波形とを、繰り返し出力し、第 1の出力波形の立ち上がりエッジをコンパレー タが検出してから、第 1の出力波形が遠端により反射された第 1の反射波形の立ち下 力 Sりエッジをコンパレータが検出するまでの第 1の時間を測定し、第 2の出力波形の 立ち下がりエッジをコンパレータが検出してから、第 2の出力波形が遠端により反射さ れた第 2の反射波形の立ち上がりエッジをコンパレータが検出するまでの第 2の時間 を測定し、第 1の時間と第 2の時間との差分に基づいて、応答時間の差を算出する校 正方法を提供する。 [0008] According to one example of a calibration method according to the fourth aspect related to innovation included in the present specification, an output signal from a device under test included in a test apparatus for testing the device under test is detected. A method for calibrating a comparator, which connects an output terminal of a driver that outputs a test signal to a device under test, an input terminal of a comparator, and a transmission path having a predetermined propagation delay, and outputs an output terminal of the driver in the transmission path. The far end to which no signal is connected is connected to a voltage source that generates a signal potential output from the driver, and the driver outputs a first output waveform having a rising edge and a second output waveform having a falling edge. Output repeatedly, the comparator detects the rising edge of the first output waveform, and then the first output waveform is reflected by the far end. Measure the first time until the comparator detects the falling edge of the reflected waveform of S 1 and the comparator detects the falling edge of the second output waveform. Second time until the comparator detects the rising edge of the second reflected waveform reflected by the edge And a calibration method for calculating the difference in response time based on the difference between the first time and the second time.
[0009] 本明細書に含まれるイノベーションに関連する第 5の側面による校正装置の一つの 例によると、第 4の側面に関する方法により試験装置に備えられたコンパレータを校 正することを目的として試験装置に接続される校正装置であって、試験装置に備えら れた、被試験デバイスに対して試験信号を出力するドライバが出力する信号電位と 略同一の電圧を発生する電圧源と、ドライバの出力端および被試験デバイスからの 出力信号を検出するコンパレータの入力端が接続された伝送経路における、ドライ バの出力端がされていない遠端と、電圧源とを接続するショート接続治具とを備える 校正装置を提供する。  [0009] According to one example of a calibration apparatus according to the fifth aspect related to innovation included in the present specification, the test for the purpose of calibrating the comparator provided in the test apparatus by the method related to the fourth aspect A calibration apparatus connected to the apparatus, a voltage source that is provided in the test apparatus and generates a voltage substantially the same as the signal potential output by the driver that outputs a test signal to the device under test, In the transmission path to which the output terminal and the input terminal of the comparator that detects the output signal from the device under test are connected, the far end where the driver output terminal is not connected and the short connection jig that connects the voltage source Provide a calibration device.
[0010] なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではなぐ これらの特徴群のサブコンビネーションもまた、発明となりうる。  [0010] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. A sub-combination of these feature groups can also be an invention.
図面の簡単な説明  Brief Description of Drawings
[0011] [図 1]本発明の実施形態に係る試験装置 10の構成を示す。  FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention.
[図 2]応答測定装置 20によるコンパレータ 16の応答時間の測定および調整処理フロ 一を示す。  FIG. 2 shows a flow of measurement and adjustment processing of the response time of the comparator 16 by the response measuring device 20.
[図 3] (A)は、ドライバ 14が立ち上がりエッジを出力した場合における、コンパレータ 1 6の入力信号波形および出力信号波形の一例を示し、(B)は、ドライバ 14が立ち下 力 Sりエッジ出力した場合における、コンパレータ 16の入力信号波形および出力信号 波形の一例を示す。  [Figure 3] (A) shows an example of the input signal waveform and output signal waveform of comparator 16 when driver 14 outputs a rising edge, and (B) shows the edge of driver S falling edge S An example of the input signal waveform and output signal waveform of comparator 16 when output is shown.
[図 4]ドライバ 14が立ち上がりエッジを出力してから立ち下がりエッジを出力するまで の時間間隔が、伝送経路 30における伝搬遅延時間の 2倍より大き!/、場合における、 コンパレータ 16の入力信号波形の一例を示す。  [Figure 4] Comparator 16 input signal waveform when driver 14 outputs a rising edge and a falling edge is greater than twice the propagation delay time in transmission path 30! / An example is shown.
[図 5]ドライバ 14が立ち上がりエッジを出力してから立ち下がりエッジを出力するまで の時間間隔力 伝送経路 30における伝搬遅延時間の 2倍より小さい場合における、 コンパレータ 16の入力信号波形の一例を示す。  [Fig.5] Time interval force from driver 14 output of rising edge to output of falling edge Shows an example of input signal waveform of comparator 16 when the propagation delay time in transmission path 30 is less than twice .
[図 6]本発明の実施形態の第 1変形例に係る試験装置 10の構成を示す。  FIG. 6 shows a configuration of a test apparatus 10 according to a first modification of the embodiment of the present invention.
[図 7]本発明の実施形態の第 2変形例に係る試験装置 10の構成を示す。 [図 8]本発明の実施形態の第 3変形例に係る試験装置 10の構成を示す。 FIG. 7 shows a configuration of a test apparatus 10 according to a second modification of the embodiment of the present invention. FIG. 8 shows a configuration of a test apparatus 10 according to a third modification of the embodiment of the present invention.
[図 9]本発明の実施形態の第 4変形例に係る試験装置 10における、ドライバ 14の出 力波形および伝送経路 30による反射波形の一例を示す。  FIG. 9 shows an example of the output waveform of the driver 14 and the reflected waveform of the transmission path 30 in the test apparatus 10 according to the fourth modification of the embodiment of the present invention.
符号の説明  Explanation of symbols
[0012] 10···試験装置、 12···信号生成部、 14· "ドライバ、 16· "コンパレータ、 18· "判 定部、 20·· ·応答測定装置、 22·· ·信号端子、 30·· ·伝送経路、 32· ··ドライバ制御 部、 34','第1測定部、 36···第 2測定部、 38···差分算出部、 40···調整部、 50·· 'ドライバコンパレータチップ、 56· ··差分記憶部、 62·· 'スィッチ、 64· · 'スィッチ制 御部、 66·· '経路長算出部、 70· ··ピン間タイミング制御部  [0012] 10 ··· Test equipment, 12 ··· Signal generator, 14 · "Driver, 16 · Comparator, 18 · Judger, 20 · · Response measuring device, 22 · · · Signal terminal, 30 ... Transmission path, 32 ... Driver control part, 34 ',' First measurement part, 36 ... Second measurement part, 38 ... Difference calculation part, 40 ... Adjustment part, 50 ... · 'Driver comparator chip, 56 · · · Difference memory, 62 · ·' Switch, 64 · 'Switch control, 66 · · Path length calculation, 70 · · Inter-pin timing control
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0013] 以下、発明の実施の形態を通じて本発明の(一)側面を説明するが、以下の実施形 態は請求の範囲に係る発明を限定するものではなぐまた実施形態に示された特徴 の組み合わせ全てが発明の解決手段に必須であるとは限らない。  [0013] Hereinafter, (1) aspects of the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the scope of the claims, and the features shown in the embodiments. Not all combinations are essential for the solution of the invention.
[0014] 図 1は、本実施形態に係る試験装置 10の構成を示す。試験装置 10は、被試験デ バイスを試験する装置であって、信号生成部 12と、ドライバ 14と、コンパレータ 16と、 判定部 18と、応答測定装置 20とを備える。  FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. The test apparatus 10 is an apparatus for testing a device under test, and includes a signal generation unit 12, a driver 14, a comparator 16, a determination unit 18, and a response measurement device 20.
[0015] 信号生成部 12は、被試験デバイスに入力すべき試験信号を生成する。信号生成 部 12は、一例として、パターン発生器と、タイミング発生器と、波形成形器とを有して よい。パターン発生器は、一例として、試験信号の元となる試験パターンと、波形モ ードを指定する波形モード信号と、良否判定に使用される期待値パターン、その他の 信号を発生する。  The signal generator 12 generates a test signal to be input to the device under test. For example, the signal generator 12 may include a pattern generator, a timing generator, and a waveform shaper. For example, the pattern generator generates a test pattern that is the source of the test signal, a waveform mode signal that specifies the waveform mode, an expected value pattern that is used for pass / fail judgment, and other signals.
[0016] タイミング発生器は、被試験デバイスに供給する波形の前縁及び後縁のタイミング を規定するタイミング信号を発生する。タイミング発生器は、一例として、発生する試 験信号の立ち上力 ^エッジまたは立ち下がりエッジを規定するタイミング信号を発生 し、また、コンパレータ 16でタイミング判定をするストローブ信号を発生する。波形成 形器は、パターン発生器から出力された試験パターンを受け、パターン発生器からの 波形モード信号に基づいて、所定の波形に整形した試験信号を生成する。  [0016] The timing generator generates a timing signal that defines the timing of the leading and trailing edges of the waveform supplied to the device under test. For example, the timing generator generates a timing signal that defines the rising force or falling edge of the test signal to be generated, and also generates a strobe signal for timing determination by the comparator 16. The wave shaper receives the test pattern output from the pattern generator, and generates a test signal shaped into a predetermined waveform based on the waveform mode signal from the pattern generator.
[0017] ドライバ 14は、試験信号を被試験デバイスの入出力ピンに対して出力する。ドライ ノ 14は、一例として、信号生成部 12により生成された試験信号を受けて、所定の V Hレベル、 VLレベルの振幅に変換したドライバ信号を信号端子 22を介して被試験 デバイスに供給する。 The driver 14 outputs a test signal to the input / output pins of the device under test. dry For example, the node 14 receives the test signal generated by the signal generation unit 12 and supplies a driver signal converted into amplitudes of predetermined VH level and VL level to the device under test via the signal terminal 22.
[0018] コンパレータ 16は、ドライバ 14の出力端及び被試験デバイスの入出力ピンに接続 され、与えられる信号を検出する。コンパレータ 16は、一例として、アナログコンパレ ータとタイミングコンパレータとを有する。アナログコンパレータは、アナログ信号を受 けて所定レベルのしきい値 VOH、 VOLに基づいて、ハイレベルおよびローレベルの 2つの論理信号に変換する。タイミングコンパレータは、ハイレベルおよびローレベル の 2つの論理信号を受け、信号生成部 12からのストローブ信号に基づくタイミングで 個々にタイミング判定をして出力する。  The comparator 16 is connected to the output terminal of the driver 14 and the input / output pins of the device under test, and detects a given signal. As an example, the comparator 16 includes an analog comparator and a timing comparator. The analog comparator receives the analog signal and converts it into two logic signals of high level and low level based on the threshold values VOH and VOL of a predetermined level. The timing comparator receives two logic signals of high level and low level, individually determines the timing at the timing based on the strobe signal from the signal generator 12, and outputs the result.
[0019] 判定部 18は、コンパレータ 16が検出した被試験デバイスの出力信号に基づいて、 被試験デバイスの良否を判定する。判定部 18は、一例として、コンパレータ 16により タイミング判定したデータと信号生成部 12からの期待値パターンとに基づいて、被試 験デバイスの良否を判定する。  The determination unit 18 determines pass / fail of the device under test based on the output signal of the device under test detected by the comparator 16. For example, the determination unit 18 determines pass / fail of the device under test based on the data whose timing is determined by the comparator 16 and the expected value pattern from the signal generation unit 12.
[0020] 応答測定装置 20は、コンパレータ 16における、信号の立ち上がりエッジに対する 応答時間と、立ち下力 Sりエッジに対する応答時間との差を検出する。そして、応答測 定装置 20は、検出したコンパレータ 16の応答時間の差に基づき、コンパレータ 16の 応答時間を調整する。より詳しくは、応答測定装置 20は、コンパレータ 16の入力端 に立ち下がりエッジが入力された時刻から、コンパレータ 16が当該立ち下がりエッジ に応じた信号を出力する時刻までの期間(立ち下力り応答時間 T )と、コンパレータ 1  The response measuring device 20 detects a difference between the response time with respect to the rising edge of the signal and the response time with respect to the falling force S edge in the comparator 16. Then, the response measurement device 20 adjusts the response time of the comparator 16 based on the detected difference in response time of the comparator 16. More specifically, the response measuring device 20 has a period from the time when the falling edge is input to the input terminal of the comparator 16 to the time when the comparator 16 outputs a signal corresponding to the falling edge (falling force response). Time T) and comparator 1
F  F
6の入力端に立ち上がりエッジが入力された時刻から、コンパレータ 16が当該立ち上 力 Sりエッジに応じた信号を出力する時刻までの期間(立ち上力 Sり応答時間丁)との差 (  The difference between the time when the rising edge is input to the input terminal of 6 and the time when the comparator 16 outputs a signal corresponding to the rising force S edge (rising force S response time)
R  R
応答時間差)を検出する。そして、応答測定装置 20は、検出した応答時間差に基づ き、コンパレータ 16の立ち上がり応答時間 Tと立ち下がり応答時間 Tとが一致する  Response time difference) is detected. Then, the response measuring device 20 matches the rising response time T and the falling response time T of the comparator 16 based on the detected response time difference.
R F  R F
ように、例えばコンパレータ 16を調整する。  For example, the comparator 16 is adjusted.
[0021] 応答測定装置 20は、ドライバ制御部 32と、第 1測定部 34と、第 2測定部 36と、差分 算出部 38と、調整部 40とを有する。ドライバ制御部 32は、ドライバ 14の出力端及び コンパレータ 16の入力端が、所定の伝播遅延を有する伝送経路 30を介して接地電 位に終端 (ショート接続)された状態において、ドライバ 14に、立ち上がりエッジを有 する第 1の出力波形と、立ち下力^エッジを有する第 2の出力波形とを出力させる。ド ライバ制御部 32は、一例として、信号生成部 12に対して所定の試験パターンを出力 させることにより、ドライバ 14から第 1の出力波形および第 2の出力波形を出力させる The response measurement device 20 includes a driver control unit 32, a first measurement unit 34, a second measurement unit 36, a difference calculation unit 38, and an adjustment unit 40. The driver control unit 32 is configured such that the output terminal of the driver 14 and the input terminal of the comparator 16 are grounded via a transmission path 30 having a predetermined propagation delay. When the terminal is terminated (short-connected), the driver 14 is caused to output a first output waveform having a rising edge and a second output waveform having a falling force edge. For example, the driver control unit 32 outputs a first output waveform and a second output waveform from the driver 14 by causing the signal generation unit 12 to output a predetermined test pattern.
[0022] ドライバ 14の出力端及びコンパレータ 16の入力端は、伝送経路 30を介して接地電 位以外の所定電位に終端 (例えばショート接続)されてもよい。また、伝送経路 30は、 当該ドライバ 14の出力端及びコンパレータ 16の入力端が接続されていない遠端力 ショート接続治具を介して接地電位にショート接続する。また、伝送経路 30の遠端は 、ドライバ 14が出力する信号電位(例えばノ、ィレベル電位またはローレベル電位)と 略同一の電圧を発生する電圧源に、ショート接続治具を介してショート接続されてよ い。 [0022] The output terminal of the driver 14 and the input terminal of the comparator 16 may be terminated (for example, short-circuited) to a predetermined potential other than the ground potential via the transmission path 30. In addition, the transmission path 30 is short-circuited to the ground potential via a far-end force short connection jig in which the output terminal of the driver 14 and the input terminal of the comparator 16 are not connected. In addition, the far end of the transmission path 30 is short-circuited to a voltage source that generates substantially the same voltage as the signal potential output from the driver 14 (for example, a no-level potential or a low-level potential) via a short connection jig. Good.
[0023] ここで、伝送経路 30は、被試験デバイスとドライバ 14及びコンパレータ 16との間を 接続する、例えば 50 Ωの特性インピーダンスのプリント基板、同軸ケーブル、同軸コ ネクタ等を含む伝送経路であってよい。また、伝送経路 30は、デバイス試験時には、 遠端に被試験デバイスの IC端子が接続され、測定時には、被試験デバイスに代えて 遠端にショート接続治具を接地電位に接続されてよい。また、ショート接続治具は、 一例として、パフォーマンスボード内で伝送経路 30の遠端と接地電位とをショート接 続してもよ!/、し、ソケットボード内で伝送経路 30の遠端と接地電位とをショート接続し てもよいし、 ICソケットに接触するダミーデバイス内で伝送経路 30の遠端と接地電位 とをショート接続してもよい。また、試験装置 10は、一例として、ドライバ 14が出力す る信号電位(例えばハイレベル電位またはローレベル電位)と略同一の電圧を発生 する電圧源と、伝送経路 30におけるドライバ 14の出力端がされていない遠端と電圧 源とを接続するショート接続治具とを備えるパフォーマンスボード等の校正装置が、 接続されてよい。  [0023] Here, the transmission path 30 is a transmission path that connects between the device under test and the driver 14 and the comparator 16 and includes, for example, a printed circuit board having a characteristic impedance of 50 Ω, a coaxial cable, a coaxial connector, and the like. It's okay. The transmission path 30 may be connected to the IC terminal of the device under test at the far end during a device test, and connected to a ground potential with a short connection jig at the far end instead of the device under test during measurement. In addition, for example, the short connection jig may be short-circuited between the far end of the transmission path 30 and the ground potential in the performance board! /, And grounded to the far end of the transmission path 30 in the socket board. The potential may be short-circuited, or the far end of the transmission path 30 and the ground potential may be short-circuited in a dummy device that contacts the IC socket. In addition, as an example, the test apparatus 10 includes a voltage source that generates substantially the same voltage as the signal potential output from the driver 14 (for example, a high level potential or a low level potential), and an output terminal of the driver 14 in the transmission path 30. A calibration device, such as a performance board, provided with a short connection jig for connecting the far end not connected to the voltage source may be connected.
[0024] 第 1測定部 34は、第 1の出力波形の立ち上がりエッジをコンパレータ 16が検出して から、当該第 1の出力波形が伝送経路 30の終端により反射された第 1の反射波形の 立ち下がりエッジをコンパレータ 16が検出するまでの第 1の時間 Tを測定する。第 2 測定部 36は、第 2の出力波形の立ち下がりエッジをコンパレータ 16が検出してから、 第 2の出力波形が伝送経路 30の終端により反射された第 2の反射波形の立ち上がり エッジをコンパレータ 16が検出するまでの第 2の時間 Tを測定する。 [0024] After the comparator 16 detects the rising edge of the first output waveform, the first measurement unit 34 causes the first reflected waveform to be reflected by the end of the transmission path 30. Measure the first time T until comparator 16 detects the falling edge. No. 2 After the comparator 16 detects the falling edge of the second output waveform, the measuring unit 36 detects the rising edge of the second reflected waveform that is reflected by the end of the transmission path 30 by the comparator 16. Measure the second time T until detection.
2  2
[0025] 差分算出部 38は、第 1の時間 Tと第 2の時間 Tとの差分に基づいて、コンパレータ  [0025] The difference calculation unit 38 compares the difference between the first time T and the second time T with a comparator.
1 2  1 2
16の応答時間の差を算出する。差分算出部 38は、一例として、第 1の時間 Tと第 2 の時間 Tとの測定時間に基づいて、コンパレータ 16の立ち上がり応答時間 Tと、立  Calculate the difference in 16 response times. As an example, the difference calculation unit 38 determines the rise response time T of the comparator 16 and the rise time based on the measurement time of the first time T and the second time T.
2 R ち下がり応答時間 Tの差を算出する。  2 R Calculates the difference in the falling response time T.
F  F
[0026] 調整部 40は、差分算出部 38が算出した応答時間の差に基づいて、コンパレータ 1 6における立ち上がりエッジに対する応答時間 T、またはコンパレータ 16における立  [0026] The adjustment unit 40 determines the response time T with respect to the rising edge in the comparator 16 or the rise time in the comparator 16 based on the difference in response time calculated by the difference calculation unit 38.
R  R
ち下がりエッジに対する応答時間 Tの少なくとも一方を調整する。調整部 40は、一  Adjust at least one of the response times T to the falling edge. The adjustment unit 40 is
F  F
例として、第 1の時間 T1又は第 2の時間 T2の測定を制御する。すなわち、調整部 40 は、立ち上がりエッジ又は立ち下がりエッジを検出することを目的として、反射波形が 消滅する程度の長周期の間、試験信号を繰り返し発生させる。そして、調整部 40は 、このように試験信号を発生した状態において、信号生成部 12から発生するストロー ブ信号のタイミングを順次変更しながら、エッジ点を検出する。  As an example, the measurement of the first time T1 or the second time T2 is controlled. In other words, the adjustment unit 40 repeatedly generates a test signal for a long period that the reflected waveform disappears for the purpose of detecting a rising edge or a falling edge. Then, the adjustment unit 40 detects the edge point while sequentially changing the timing of the strobe signal generated from the signal generation unit 12 in the state where the test signal is generated in this way.
[0027] これにより、調整部 40は、一例として、立ち上がり応答時間 Tと立ち下がり応答時 [0027] As a result, the adjustment unit 40, for example, uses the rise response time T and the fall response time.
R  R
間 Tとが一致するように、信号生成部 12から発生するストローブ信号のタイミングを The timing of the strobe signal generated from the signal generator 12 is adjusted so that
F F
補正すること力 Sできる。従って、調整部 40は、デバイス試験時におけるコンパレータ 1 6の立ち上がりエッジと立ち下がりエッジとのタイミング誤差を小さくすることができる。  Correcting power S Therefore, the adjustment unit 40 can reduce the timing error between the rising edge and the falling edge of the comparator 16 during the device test.
[0028] 図 2は、応答測定装置 20によるコンパレータ 16の応答時間の測定および校正フロ 一を示す。図 3 (A)は、ドライバ 14が立ち上がりエッジを出力した場合における、コン パレータ 16の入力信号波形および出力信号波形の一例を示し、図 3 (B)は、ドライ ノ 14が立ち下がりエッジ出力した場合における、コンパレータ 16の入力信号波形お よび出力信号波形の一例を示す。  FIG. 2 shows a measurement and calibration flow of the response time of the comparator 16 by the response measuring device 20. Fig. 3 (A) shows an example of the input signal waveform and output signal waveform of the comparator 16 when the driver 14 outputs a rising edge, and Fig. 3 (B) shows the output of the falling edge of the driver 14 An example of the input signal waveform and the output signal waveform of the comparator 16 is shown.
[0029] 応答測定装置 20は、例えば被試験デバイスの試験に先立って、ステップ S210か らステップ S214までの校正処理を実行する。まず、応答測定装置 20は、ドライバ 14 の出力端及びコンパレータ 16の入力端を、所定の伝播遅延を有する伝送経路 30の 遠端に例えばショート接続治具を接続することにより、接地電位に終端する (ステップ S210)。応答測定装置 20は、一例として、被試験デバイスが載置されるパフォーマ ンスボードを、伝送経路 30の遠端と接地電位とを接続するショート接続治具が設けら れたパフォーマンスボードに交換することにより、ドライバ 14の出力端及びコンパレー タ 16の入力端を伝送経路 30を介して接地電位に終端する。 [0029] The response measuring apparatus 20 executes the calibration process from step S210 to step S214, for example, prior to the test of the device under test. First, the response measuring device 20 terminates the output end of the driver 14 and the input end of the comparator 16 to the ground potential by connecting, for example, a short connection jig to the far end of the transmission path 30 having a predetermined propagation delay. (Step S210). As an example, the response measuring apparatus 20 replaces the performance board on which the device under test is placed with a performance board provided with a short connection jig that connects the far end of the transmission path 30 to the ground potential. The output terminal of the driver 14 and the input terminal of the comparator 16 are terminated to the ground potential via the transmission path 30.
[0030] 次に、応答測定装置 20は、例えば図 3 (A)に示すような第 1の時間 Tを測定する( ステップ S211)。ステップ S211において、まず、ドライバ制御部 32は、指定された時 刻 t311において、立ち上がりエッジを有する第 1の出力波形をドライバ 14から出力さ せる。すなわち、ドライバ 14の出力レベルは、 VLから VHに遷移する。ドライバ 14力、 ら出力された第 1の出力波形は、コンパレータ 16に入力される。なお、ここでは、ドラ ィバ 14から出力波形が出力されてからコンパレータ 16に入力するまでの時間は、説 明の便宜上 0である場合を示すが時間差があっても支障とはならない。コンパレータ 16は、ドライバ 14から出力された第 1の出力波形の立ち上がりエッジを入力した時刻 t311から、立ち上がり応答時間 T分遅れた時刻 t312において、当該第 1の出力波 Next, the response measuring device 20 measures a first time T as shown in FIG. 3A, for example (step S211). In step S211, first, the driver control unit 32 causes the driver 14 to output a first output waveform having a rising edge at a designated time t311. That is, the output level of the driver 14 transitions from VL to VH. The first output waveform output from the driver 14 force is input to the comparator 16. Here, the time from when the output waveform is output from the driver 14 to when it is input to the comparator 16 is 0 for convenience of explanation, but there is no problem even if there is a time difference. Comparator 16 receives the first output waveform at time t312 delayed by rise response time T from time t311 when the rising edge of the first output waveform output from driver 14 is input.
R  R
形の立ち上がりエッジ点をサーチして検出する。ここで、応答測定装置 20は、エッジ 点をサーチするために十分な期間、図 3 (A)の波形をドライバ 14から繰り返して発生 させる。  Search for and detect rising edge points of shapes. Here, the response measuring apparatus 20 repeatedly generates the waveform of FIG. 3A from the driver 14 for a period sufficient to search for the edge point.
[0031] さらに、ドライバ 14から出力された立ち上がりエッジを有する第 1の出力波形は、伝 送経路 30にも入力される。ここで、伝送経路 30は、入力した出力波形を終端側に伝 搬させ、略 0 Ωの接続線により接地された終端により反射波形を反射する。  Further, the first output waveform having the rising edge output from the driver 14 is also input to the transmission path 30. Here, the transmission path 30 transmits the input output waveform to the termination side, and reflects the reflected waveform by the termination grounded by the connection line of approximately 0Ω.
[0032] ここで、ローレベル電位 VLが 0ボルト (接地電位)以外の場合、試験装置 10は、 VL 電圧を発生する電圧源を備え、伝送経路 30を VL電圧に接続して終端する。終端に ぉレ、て反射された反射波形は、伝送経路 30の終端が接地電位に接続されて!/、るこ とから、ドライバ 14から出力された出力波形と正負が反転した波形となる。すなわち、 立ち上がりエッジは、接地された終端で反射されることにより立ち下りエッジとなり、立 ち下りエッジは、接地された終端で反射されることにより立ち上がりエッジとなる。従つ て、コンパレータ 16では、伝送経路 30を往復する時間経過後において、立ち下りェ ッジを有する第 1の反射波形を伝送経路 30から入力する。なお、反射波形が消滅し た後には、ドライバ 14は、例えば 50 Ωの内部抵抗を有する。また、伝送経路 30の遠 端は、 VL電圧にショート接続されている。この結果、ドライバ 14の出力端は、 VHレ ベルを出力しているにも関わらず、強制的に直流的な VLレベルになる。 Here, when the low-level potential VL is other than 0 volt (ground potential), the test apparatus 10 includes a voltage source that generates the VL voltage, and terminates the transmission path 30 by connecting it to the VL voltage. The reflected waveform reflected at the end is a waveform in which the polarity of the output waveform output from the driver 14 is inverted because the end of the transmission path 30 is connected to the ground potential! /. That is, the rising edge becomes a falling edge by being reflected at the grounded terminal, and the falling edge becomes a rising edge by being reflected at the grounded terminal. Therefore, the comparator 16 inputs the first reflected waveform having the falling edge from the transmission path 30 after the time for reciprocating the transmission path 30 has elapsed. Note that after the reflected waveform disappears, the driver 14 has an internal resistance of 50 Ω, for example. Also, the distance of transmission path 30 The end is short-circuited to the VL voltage. As a result, the output terminal of the driver 14 is forcibly set to a DC VL level although it outputs the VH level.
[0033] コンパレータ 16は、ドライバ 14が第 1の出力波形の立ち上がりエッジを出力した時 刻 t311から、伝送経路 30における伝搬遅延時間 T の 2倍の時間 T分遅延した時 [0033] Comparator 16 compares the time t311 when driver 14 outputs the rising edge of the first output waveform with a time T that is twice the propagation delay time T in transmission path 30.
A B  A B
刻 t313において、第 1の反射波形の立ち下がりエッジを入力する。続いて、コンパレ ータ 16は、第 1の反射波形の立ち下がりを入力した時刻 t313から立ち下がり応答時 間 T分遅れた時刻 t314において、当該第 1の反射波形の立ち下がりエッジを検出 At t313, the falling edge of the first reflected waveform is input. Subsequently, the comparator 16 detects the falling edge of the first reflected waveform at the time t314 delayed by the falling response time T from the time t313 when the falling edge of the first reflected waveform is input.
F F
する。なお、ここでは、ドライバ 14から出力波形が出力されて力も伝送経路 30に入力 するまでの時間、および、反射波形が伝送経路 30から出力されてからコンパレータ 1 6に入力するまでの時間は 0である場合を示す力 S、時間差があっても同様となる。そし て、第 1測定部 34は、ドライバ 14から出力された第 1の出力波形の立ち上がりエッジ を検出した時刻 t312から、伝送経路 30により反射された第 1の反射波形の立ち下が りエッジを検出した時刻 t314までの第 1の時間 Tを測定する。  To do. Here, the time from when the output waveform is output from the driver 14 until the force is input to the transmission path 30 and the time from when the reflected waveform is output from the transmission path 30 to when it is input to the comparator 16 are 0. It is the same even if there is a force S and time difference indicating a certain case. The first measurement unit 34 detects the falling edge of the first reflected waveform reflected by the transmission path 30 from the time t312 when the rising edge of the first output waveform output from the driver 14 is detected. Measure the first time T until the detected time t314.
[0034] 次に、応答測定装置 20は、例えば図 3 (B)に示すような第 2の時間 Tを測定する( Next, the response measuring apparatus 20 measures a second time T as shown in FIG. 3B, for example (
2  2
ステップ S212)。ここで、伝送経路 30の遠端は、略 0 Ωの接続線により接地された終 端により反射波形を反射する。試験装置 10は、 VH電圧を発生する電圧源を備え、 伝送経路 30を VH電圧に接続して終端する。ステップ S212において、まず、ドライバ 制御部 32は、第 1の出力波形の立ち上がりエッジを出力させた時刻 t311とは異なる 時刻 t321において、立ち下がりエッジを有する第 2の出力波形をドライバ 14から出 力させる。すなわち、ドライバ 14の出力レベルは、 VHから VLに遷移する。ドライバ 1 4から出力された第 2の出力波形は、コンパレータ 16に入力される。コンパレータ 16 は、ドライバ 14から出力された第 2の出力波形の立ち下がりエッジを入力した時刻 t3 21から、立ち下がり応答時間 T分遅れた時刻 t322において、当該第 2の出力波形  Step S212). Here, the far end of the transmission path 30 reflects the reflected waveform by the end grounded by the connection line of approximately 0Ω. The test apparatus 10 includes a voltage source that generates a VH voltage, and terminates the transmission path 30 by connecting it to the VH voltage. In step S212, first, the driver control unit 32 causes the driver 14 to output the second output waveform having the falling edge at a time t321 different from the time t311 when the rising edge of the first output waveform is output. . That is, the output level of the driver 14 transitions from VH to VL. The second output waveform output from the driver 14 is input to the comparator 16. Comparator 16 outputs the second output waveform at time t322, which is delayed by the falling response time T from time t321, when the falling edge of the second output waveform output from driver 14 is input.
F  F
の立ち下がりエッジ点をサーチして検出する。ここで、応答測定装置 20は、エッジ点 をサーチするために十分な期間、図 3 (B)の波形をドライバ 14から繰り返して発生さ せる。  Search for and detect the falling edge point. Here, the response measuring apparatus 20 repeatedly generates the waveform of FIG. 3B from the driver 14 for a period sufficient to search for the edge point.
[0035] さらに、ドライバ 14から出力された立ち下がりエッジを有する第 2の出力波形は、伝 送経路 30にも入力される。ドライバ 14から出力された立ち下がりエッジを有する第 2 の出力波形が伝送経路 30に入力された場合、コンパレータ 16は、立ち上がりエッジ を有する第 2の反射波形を伝送経路 30から入力する。コンパレータ 16は、ドライバ 1 4が第 2の出力波形の立ち下がりエッジを出力した時刻 t321から、伝送経路 30にお ける伝搬遅延時間 Tの 2倍の時間 T分遅延した時刻 t323において、第 2の反射波 Further, the second output waveform having the falling edge output from the driver 14 is also input to the transmission path 30. Second with falling edge output from driver 14 When the output waveform is input to the transmission path 30, the comparator 16 inputs the second reflected waveform having a rising edge from the transmission path 30. Comparator 16 compares the second output waveform at time t323, which is delayed by time T that is twice the propagation delay time T in transmission path 30 from time t321 when driver 14 outputs the falling edge of the second output waveform. Reflected wave
A B  A B
形の立ち上がりエッジを入力する。なお、反射波形が消滅した後には、ドライバ 14は 、例えば 50 Ωの内部抵抗を有する。また、伝送経路 30の遠端は、 VH電圧にショート 接続されている。この結果、ドライバ 14の出力端は、 VLレベルを出力しているにも関 わらず、強制的に直流的な VHレベルになる。  Enter the rising edge of the shape. Note that after the reflected waveform disappears, the driver 14 has an internal resistance of 50 Ω, for example. The far end of the transmission path 30 is short-circuited to the VH voltage. As a result, the output terminal of the driver 14 is forcibly set to the DC VH level even though the VL level is output.
[0036] 続いて、コンパレータ 16は、第 2の反射波形の立ち上がりエッジを入力した時刻 t3 23から立ち上がり応答時間 T分遅れた時刻 t324において、当該第 2の反射波形の [0036] Subsequently, at time t324, which is delayed by the rising response time T from time t3 23 when the rising edge of the second reflected waveform is input, the comparator 16 outputs the second reflected waveform.
R  R
立ち上がりエッジを検出する。そして、第 2測定部 36は、ドライバ 14から出力された第 2の出力波形の立ち下がりエッジを検出した時刻 t322から、伝送経路 30により反射 された第 2の反射波形の立ち上がりエッジを検出した時刻 t324までの第 2の時間 T  Detect rising edge. Then, the second measurement unit 36 detects the rising edge of the second reflected waveform reflected by the transmission path 30 from the time t322 when the falling edge of the second output waveform output from the driver 14 is detected. Second time T up to t324
2 を測定する。  Measure 2.
[0037] ステップ S211およびステップ S212の処理が終わると、次に、差分算出部 38は、第 1の時間 Tと第 2の時間 Tとの差分に基づいて、コンパレータ 16における応答時間  [0037] After the processing of step S211 and step S212 is completed, the difference calculating unit 38 then determines the response time in the comparator 16 based on the difference between the first time T and the second time T.
1 2  1 2
の差を算出する(ステップ S213)。ここで、第 1の時間 Tは、第 1の出力波形の立ち 上がりエッジをコンパレータ 16が入力した時刻 t311から、第 1の反射波形の立ち下 力 Sりエッジをコンパレータ 16が入力した時刻 t313までの期間(すなわち、伝送経路 3 0における伝搬遅延時間の 2倍の時間 T )に対して、立ち上がり応答時間 T分短ぐ  Is calculated (step S213). Here, the first time T is from time t311 when the rising edge of the first output waveform is input by the comparator 16 to time t313 when the falling edge S of the first reflected waveform is input by the comparator 16 The rise response time T is shorter than the period (that is, the time T twice the propagation delay time in the transmission path 30).
B R  B R
立ち下がり応答時間 T分長い時間となる。すなわち、第 1の時間 Tは、 T T +T  Fall response time T minutes longer. That is, the first time T is T T + T
F 1 B R F で表される。  F 1 B R F
[0038] 一方、第 2の時間 Tは、第 2の出力波形の立ち下がりエッジをコンパレータ 16が入  [0038] On the other hand, during the second time T, the comparator 16 enters the falling edge of the second output waveform.
2  2
力した時亥 Ijt321力、ら、第 2の反射波形の立ち上がりエッジをコンパレータ 16が入力 した時刻 t323までの期間(すなわち、伝送経路 30における伝搬遅延時間の 2倍の 時間 T )に対して、立ち下がり応答時間 T分短ぐ立ち上がり応答時間 T分長い時 Ijt321 force, and the rising edge of the second reflected waveform rises for the period up to time t323 when the comparator 16 inputs (that is, the time T that is twice the propagation delay time in the transmission path 30). Fall response time T minutes shorter Rise response time T minutes longer
B F R B F R
間となる。すなわち、第 2の時間 Tは、 T T +Tで表される。  Between. That is, the second time T is represented by T T + T.
2 B F R  2 B F R
[0039] このような第 1の時間 Tおよび第 2の時間 Tの差を算出すると下記式(1)のように 表される。 [0039] When the difference between the first time T and the second time T is calculated, the following equation (1) is obtained. expressed.
(T T ) = { (T T +T )—(T T +T ) } = 2 X (T — T )  (T T) = {(T T + T) — (T T + T)} = 2 X (T — T)
1 2 Β R F Β F R F R  1 2 Β R F Β F R F R
[0040] 従って、差分算出部 38は、応答時間の差 (Τ — Τ )を、下記式(2)のように、第 1の  [0040] Therefore, the difference calculation unit 38 calculates the difference in response time (Τ-Τ) as the following equation (2).
F R  F R
時間 Τと第 2の時間 Τとの差の 1/2により算出することができる。  It can be calculated by 1/2 of the difference between the time Τ and the second time Τ.
1 2  1 2
(Τ -Τ ) = (Τ Τ ) /2 - - - (2)  (Τ -Τ) = (Τ Τ) / 2---(2)
F R 1 2  F R 1 2
[0041] 次に、調整部 40は、ステップ S213により算出された応答時間の差に基づき、応答 時間の差が略 0となるようにコンパレータ 16を調整する(ステップ S214)。調整部 40 は、一例として、信号生成部 12からコンパレータ 16へ供給するストローブ信号の遅 延量を調整付与することで補正できる。  Next, the adjusting unit 40 adjusts the comparator 16 based on the difference in response time calculated in step S213 so that the difference in response time becomes substantially zero (step S214). For example, the adjustment unit 40 can correct the delay by adjusting the delay amount of the strobe signal supplied from the signal generation unit 12 to the comparator 16.
[0042] 以上のような試験装置 10によれば、外部の基準ドライバから立ち上がりエッジおよ び立ち下力 Sりエッジをコンパレータ 16に供給させて試験することなぐ既に備えられ ているドライバ 14を用いてコンパレータ 16の応答時間を調整することができる。従つ て、試験装置 10によれば、随時コンパレータ 16の特性を補正することができ、精度 良く被試験デバイスを試験することができる。  [0042] According to the test apparatus 10 as described above, the driver 14 already provided without using the external reference driver to supply the rising edge and falling force S to the comparator 16 for testing is used. The response time of the comparator 16 can be adjusted. Therefore, according to the test apparatus 10, the characteristics of the comparator 16 can be corrected at any time, and the device under test can be tested with high accuracy.
[0043] 図 4は、ドライバ 14が立ち上がりエッジを出力してから立ち下がりエッジを出力する までの時間間隔力 S、伝送経路 30における伝搬遅延時間の 2倍より大きい場合におけ る、コンパレータ 16の入力信号波形の一例を示す。図 5は、ドライバ 14が立ち上がり エッジを出力してから立ち下がりエッジを出力するまでの時間間隔が、伝送経路 30 における伝搬遅延時間の 2倍より小さい場合における、コンパレータ 16の入力信号 波形の一例を示す。  [0043] FIG. 4 shows that the time interval force S from when the driver 14 outputs the rising edge to the output of the falling edge S is greater than twice the propagation delay time in the transmission path 30. An example of an input signal waveform is shown. Figure 5 shows an example of the input signal waveform of the comparator 16 when the time interval from when the driver 14 outputs a rising edge to when it outputs a falling edge is less than twice the propagation delay time in the transmission path 30. Show.
[0044] ドライバ制御部 32は、第 1の出力波形と第 2の出力波形とを所定の時間間隔で連 続してドライバ 14から出力させる。一例として、ドライバ制御部 32は、図 4に示すよう に、ドライバ 14が第 1の出力波形の立ち上がりエッジ及び第 2の出力波形立ち下がり エッジを出力する時間間隔 T力 伝送経路 30における伝播遅延時間 T の 2倍の時  The driver control unit 32 causes the driver 14 to continuously output the first output waveform and the second output waveform at a predetermined time interval. As an example, as shown in FIG. 4, the driver control unit 32 is a time interval at which the driver 14 outputs a rising edge and a second output waveform falling edge of the first output waveform.T force propagation delay time in the transmission path 30 Twice T
X A  X A
間 Tより大きくなるようにドライバ 14を制御する。  The driver 14 is controlled so as to be larger than T.
B  B
[0045] この場合において、第 1測定部 34は、第 1の出力波形の立ち上がりエッジと、第 1の 反射波形の立ち下がりエッジとを有するパルスのノ レス幅を、第 1の時間 Tとして測 定する。すなわち、第 1測定部 34は、測定を開始してからコンパレータ 16がー番目 に検出した第 1エッジと、 2番目に検出した第 2エッジとの間の時間を、第 1の時間 として測定する。そして、第 2測定部 36は、第 2の出力波形の立ち下がりエッジと、第 2の反射波形の立ち上がりエッジとを有するノ ルスのノ ルス幅を、第 2の時間 Tとし [0045] In this case, the first measurement unit 34 measures the pulse width having the rising edge of the first output waveform and the falling edge of the first reflected waveform as the first time T. Determine. In other words, the first measurement unit 34 starts the measurement, and the comparator 16 The time between the first edge detected in step 2 and the second edge detected second is measured as the first time. Then, the second measuring unit 36 uses the width of the noise having the falling edge of the second output waveform and the rising edge of the second reflected waveform as the second time T.
2 て測定する。すなわち、第 2測定部 36は、測定を開始してからコンパレータ 16が 3番 目に検出した第 3エッジと、 4番目に検出した第 4エッジとの間の時間を、第 2の時間 Tとして測定する。  2 Measure. That is, the second measuring unit 36 sets the time between the third edge detected by the comparator 16 after the start of measurement and the fourth edge detected fourth as the second time T. taking measurement.
2  2
[0046] また、一例として、ドライバ制御部 32は、図 5に示すように、第 1の出力波形の立ち 上がりエッジ及び第 2の出力波形の立ち下がりエッジを出力する時間間隔 T力 伝  Further, as an example, as shown in FIG. 5, the driver control unit 32 outputs a time interval T power transmission that outputs a rising edge of the first output waveform and a falling edge of the second output waveform.
X  X
送経路 30における伝播遅延時間 T の 2倍の時間 Tより小さくなるようにドライバ 14を  Driver 14 is adjusted so that it is smaller than time T, which is twice the propagation delay time T in transmission path 30.
A B  A B
制御する。この場合において、第 1測定部 34は、第 1の出力波形の立ち上がりエッジ と、第 1の反射波形の立ち下がりエッジとを有するパルスのノ レス幅を、第 1の時間 T として測定する。すなわち、第 1測定部 34は、測定を開始してからコンパレータ 16が 一番目に検出した第 1エッジと、 3番目に検出した第 3エッジとの間の時間を、第 1の 時間 Tとして測定する。そして、第 2測定部 36は、第 2の出力波形の立ち下がりエツ ジと、第 2の反射波形の立ち上がりエッジとを有するパルスのノ レス幅を、第 2の時間 Tとして測定する。すなわち、第 2測定部 36は、測定を開始してからコンパレータ 16 Control. In this case, the first measuring unit 34 measures the pulse width having the rising edge of the first output waveform and the falling edge of the first reflected waveform as the first time T. That is, the first measurement unit 34 measures the time between the first edge detected by the comparator 16 first after the start of measurement and the third edge detected third as the first time T. To do. Then, the second measurement unit 36 measures the pulse width having the falling edge of the second output waveform and the rising edge of the second reflected waveform as the second time T. That is, the second measuring unit 36 starts the measurement and then compares the comparator 16
2 2
力 ¾番目に検出した第 2エッジと、 4番目に検出した第 4エッジとの間の時間を、第 2の 時間 Tとして測定する。  The time between the second edge detected for the third time and the fourth edge detected for the fourth time is measured as the second time T.
2  2
[0047] 図 6は、本実施形態の第 1変形例に係る試験装置 10の構成を示す。本変形例に係 る試験装置 10は、図 1に示した同一符号の部材と略同一の構成および機能を採るの で、以下相違点を除き説明を省略する。  FIG. 6 shows a configuration of the test apparatus 10 according to the first modification example of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
[0048] 試験装置 10は、ドライバ 14と、コンパレータ 16と、応答測定装置 20とを有するドラ ィバコンパレータチップ 50を備える構成例である。ドライバコンパレータチップ 50は、 一例として、半導体チップ、モジュールまたは基板上に、ドライバ 14、コンパレータ 16 および応答測定装置 20を集積したものである。このような本変形例に係る試験装置 1 0によれば、ドライバ 14およびコンパレータ 16が設けられるピンリソース毎に応答測 定装置 20を備えることができる。さらに、本変形例に係る試験装置 10によれば、ドラ ィバ 14、コンパレータ 16および応答測定装置 20の組を当該試験装置 10内に簡易 に実装することができる。 [0048] The test apparatus 10 is a configuration example including a driver comparator chip 50 including a driver 14, a comparator 16, and a response measuring apparatus 20. As an example, the driver comparator chip 50 is obtained by integrating the driver 14, the comparator 16, and the response measuring device 20 on a semiconductor chip, a module, or a substrate. According to such a test apparatus 10 according to this modification, the response measurement apparatus 20 can be provided for each pin resource in which the driver 14 and the comparator 16 are provided. Furthermore, according to the test apparatus 10 according to the present modification, the set of the driver 14, the comparator 16, and the response measurement apparatus 20 is simplified in the test apparatus 10. Can be implemented.
[0049] また、応答測定装置 20は、差分記憶部 56を更に有する。差分記憶部 56は、調整 時において算出された応答時間の差に応じた値を保持する。調整部 40は、差分記 憶部 56に保持された値を参照して、コンパレータ 16の立ち上がり応答時間 Tおよび In addition, the response measurement device 20 further includes a difference storage unit 56. The difference storage unit 56 holds a value corresponding to the difference in response time calculated at the time of adjustment. The adjustment unit 40 refers to the value held in the difference storage unit 56, and the rising response time T and the comparator 16
R  R
立ち下がり応答時間 Tを調整する。これにより、本変形例に係る試験装置 10によれ  Adjust fall response time T. As a result, the test apparatus 10 according to this variation
F  F
ば、例えば定期的に調整して得られた最新の測定結果を保持することができるので、 コンパレータ 16の応答時間が経時変化する場合であっても、立ち上がりエッジと立ち 下がりエッジとの応答時間にずれがないように調整することができる。  For example, the latest measurement results obtained by regular adjustment can be held, so even if the response time of the comparator 16 changes with time, the response time between the rising edge and falling edge It can be adjusted so that there is no deviation.
[0050] 図 7は、本実施形態の第 2変形例に係る試験装置 10の構成を示す。本変形例に係 る試験装置 10は、図 1に示した同一符号の部材と略同一の構成および機能を採るの で、以下相違点を除き説明を省略する。  FIG. 7 shows a configuration of the test apparatus 10 according to the second modification example of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
[0051] 本変形例において、応答測定装置 20は、スィッチ 62と、スィッチ制御部 64とを更に 有する。スィッチ 62は、ドライバ 14及びコンパレータ 16と、被試験デバイスとを接続 する伝送経路 30を、被試験デバイス又は接地電位の!/、ずれに接続するかを切り替 える。すなわち、スィッチ 62は、ドライバ 14の出力端及びコンパレータ 16の入力端を 伝送経路 30を介して被試験デバイスに接続する力、、ドライバ 14の出力端及びコンパ レータ 16の入力端を伝送経路 30を介して接地するかを切り替える。なお、スィッチ 6 2は、ハイフィックス、パフォーマンスボードに実装されてよい。また、ドライバ 14を実 装する基板(ピンエレクトロニクス基板) 、反射波形のエッジを測定可能な程度の伝 送線路長を含む場合には、スィッチ 62は、当該ピンエレクトロニクス基板に実装され てよい。また、スィッチ 62は、半導体スィッチが適用可能な場合には、半導体スィッチ であってもよい。  [0051] In this modification, the response measuring device 20 further includes a switch 62 and a switch control unit 64. The switch 62 switches whether the transmission path 30 connecting the driver 14 and the comparator 16 and the device under test is connected to the device under test or the ground potential! That is, the switch 62 connects the output end of the driver 14 and the input end of the comparator 16 to the device under test via the transmission path 30, and the transmission path 30 connects the output end of the driver 14 and the input end of the comparator 16. Switch between grounding through. The switch 62 may be mounted on a HiFix or performance board. Further, when the board (pin electronics board) on which the driver 14 is mounted and the transmission line length that can measure the edge of the reflected waveform are included, the switch 62 may be mounted on the pin electronics board. Further, the switch 62 may be a semiconductor switch when a semiconductor switch is applicable.
[0052] スィッチ制御部 64は、スィッチ 62を切り替え制御する。スィッチ制御部 64は、試験 時において、伝送経路 30を被試験デバイスの入出力ピンに接続し、調整時におい て、伝送経路 30を接地電位に接続するべく制御する。このような変形例に係る試験 装置 10によれば、試験において使用される伝送経路 30を利用して、コンパレータ 16 の応答時間を調整することができる。  The switch control unit 64 switches and controls the switch 62. The switch control unit 64 controls the transmission path 30 to be connected to the input / output pin of the device under test during the test, and to connect the transmission path 30 to the ground potential during the adjustment. According to the test apparatus 10 according to such a modification, the response time of the comparator 16 can be adjusted using the transmission path 30 used in the test.
[0053] また、応答測定装置 20は、経路長算出部 66を更に有してよい。経路長算出部 66 は、第 1の時間 Tおよび第 2の時間 Τに基づいて、伝送経路 30における伝播遅延 In addition, the response measurement device 20 may further include a path length calculation unit 66. Path length calculator 66 Is the propagation delay in transmission path 30 based on the first time T and the second time Τ
1 2  1 2
時間 Τを算出する。ここで、第 1の時間 Τおよび第 2の時間 Τの和は、下記式(3)の Calculate time Τ. Here, the sum of the first time Τ and the second time Τ is given by the following equation (3).
A 1 2 A 1 2
ように表される。  It is expressed as follows.
(T +T ) = { (Τ -Τ +Τ ) + (Τ -Τ +Τ ) } = 2 ΧΤ · ' · (3)  (T + T) = {(Τ -Τ + Τ) + (Τ -Τ + Τ)} = 2 ΧΤ '' (3)
1 2 B R F B F R B  1 2 B R F B F R B
[0054] また、伝搬遅延時間 T は、 T /2となる。このことから、伝搬遅延時間 Τ は、下記  Further, the propagation delay time T is T / 2. From this, the propagation delay time Τ is
A B A  A B A
式(4)のように表される。  It is expressed as equation (4).
T = (T +Τ ) /4 · ' · (4)  T = (T + Τ) / 4/4 '' (4)
A 1 2  A 1 2
[0055] 従って、経路長算出部 66は、伝搬遅延時間 Tを、第 1の時間 Tと第 2の時間 Tと  Accordingly, the path length calculation unit 66 determines the propagation delay time T as the first time T and the second time T.
A 1 2 の和の 4分の 1により算出することができる。このように本変形例に係る試験装置 10に よれば、試験において用いられる伝送経路 30の伝搬遅延時間 Tを算出することが  It can be calculated by a quarter of the sum of A 1 2. As described above, according to the test apparatus 10 according to this modification, the propagation delay time T of the transmission path 30 used in the test can be calculated.
A  A
できる。さらに、試験装置 10は、ピンリソース毎に応答測定装置 20を備えていれば、 伝送経路 30の伝播遅延時間 Tを例えばピン毎に算出することができる。  it can. Furthermore, if the test apparatus 10 includes the response measurement apparatus 20 for each pin resource, the propagation delay time T of the transmission path 30 can be calculated for each pin, for example.
A  A
[0056] 図 8は、本実施形態の第 3変形例に係る試験装置 10の構成を示す。本変形例に係 る試験装置 10は、図 1に示した同一符号の部材と略同一の構成および機能を採るの で、以下相違点を除き説明を省略する。  FIG. 8 shows a configuration of a test apparatus 10 according to a third modification of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the members having the same reference numerals shown in FIG. 1, the description thereof will be omitted except for the following differences.
[0057] 本変形例において、当該試験装置 10は、数千チャンネルにも及ぶ複数組のドライ ノ 14及びコンパレータ 16と、それぞれのドライバ 14及びコンパレータ 16に一対一で 対応する複数の応答測定装置 20とを備える。なお、この場合において、複数の応答 測定装置 20は、共通のドライバ制御部 32を備えてよい。すなわち、試験装置 10は、 複数組のドライバ 14及びコンパレータ 16に一対一に対応する、複数の第 1測定部 3 4、複数の第 2測定部 36、複数の第 2測定部 36及び調整部 40を備えてよい。  [0057] In this modification, the test apparatus 10 includes a plurality of sets of dryers 14 and comparators 16 extending to several thousand channels, and a plurality of response measuring apparatuses 20 corresponding one-to-one to the respective drivers 14 and comparators 16. With. In this case, the plurality of response measuring apparatuses 20 may include a common driver control unit 32. That is, the test apparatus 10 includes a plurality of first measurement units 34, a plurality of second measurement units 36, a plurality of second measurement units 36, and an adjustment unit 40 that correspond one-to-one to a plurality of sets of drivers 14 and comparators 16. May be provided.
[0058] ドライバ制御部 32は、複数のドライバ 14に対して略同時に信号を出力させる。そし て、複数の応答測定装置 20は、複数のコンパレータ 16のそれぞれの応答時間の差 を並行して算出して、複数のコンパレータ 16の応答時間を並行して調整する。これに より、試験装置 10によれば、短時間で複数のコンパレータ 16の応答時間を調整する こと力 Sでさる。  The driver control unit 32 causes the plurality of drivers 14 to output signals substantially simultaneously. Then, the plurality of response measuring devices 20 calculate the difference between the response times of the plurality of comparators 16 in parallel, and adjust the response times of the plurality of comparators 16 in parallel. Thus, according to the test apparatus 10, the force S can be adjusted to adjust the response times of the plurality of comparators 16 in a short time.
[0059] また、試験装置 10は、一例として、複数組のドライバ 14およびコンパレータ 16の間 におけるコンパレータ間スキューを調整するピン間タイミング制御部 70を更に備えて よい。ピン間タイミング制御部 70は、複数の応答測定装置 20のそれぞれが個別にコ ンパレータ 16の応答時間を調整した後に、コンパレータ間スキューを調整してよい。 これによれば、複数のコンパレータ 16間において、立ち上がりエッジ及び立ち下がり エッジの両エッジに対するコンパレータ間スキューが調整される結果、高精度なタイミ ングでのデバイス試験が実現できる。 [0059] In addition, the test apparatus 10 further includes, as an example, an inter-pin timing control unit 70 that adjusts an inter-comparator skew between a plurality of sets of drivers 14 and comparators 16. Good. The inter-pin timing control unit 70 may adjust the inter-comparator skew after each of the plurality of response measuring devices 20 individually adjusts the response time of the comparator 16. According to this, as a result of adjusting the inter-comparator skew with respect to both the rising edge and the falling edge between the plurality of comparators 16, it is possible to realize a device test with high accuracy timing.
[0060] 図 9は、本実施形態の第 4変形例に係る試験装置 10における、ドライバ 14の出力 波形および伝送経路 30による反射波形の一例を示す。本変形例に係る試験装置 1 0は、図 1と略同一の構成および機能を採るので、以下相違点を除き説明を省略する FIG. 9 shows an example of the output waveform of the driver 14 and the reflected waveform of the transmission path 30 in the test apparatus 10 according to the fourth modification of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as those in FIG. 1, the description thereof will be omitted except for the following differences.
[0061] 本変形例は、ドライバ 14が出力する出カノ ルス波形のノ ルス幅 Tの時間が、伝送 [0061] In this modification, the time of the pulse width T of the output waveform output from the driver 14 is transmitted.
3  Three
経路 30で反射して戻る伝搬遅延時間よりも短い出カノ ルスを発生する。本変形例に おいて、ドライバ制御部 32は、ドライバ 14の出力端及びコンパレータ 16の入力端が 、所定の伝播遅延を有する伝送経路 30を介して接地電位に終端された状態にお!/、 て、ドライバ 14に、立ち上がりエッジ及び立ち下がりエッジを有する出カノ ルス波形 を出力させる。ドライバ 14から出力された出カノ ルス波形を入力した場合、伝送経路 30は、所定時間後に、出力パルス波形に対して反転した波形の反射パルス波形を 出力する。  An output can be generated that is shorter than the propagation delay time reflected by path 30 and returning. In this modification, the driver control unit 32 is in a state where the output end of the driver 14 and the input end of the comparator 16 are terminated to the ground potential via the transmission path 30 having a predetermined propagation delay! /, Thus, the driver 14 outputs an output waveform having a rising edge and a falling edge. When an output waveform output from the driver 14 is input, the transmission path 30 outputs a reflected pulse waveform that is an inverted waveform of the output pulse waveform after a predetermined time.
[0062] 第 1測定部 34は、コンパレータ 16が検出した出カノ ルス波形のノ ルス幅 Tを測定  [0062] The first measurement unit 34 measures the pulse width T of the output waveform detected by the comparator 16.
3 する。第 2測定部 36は、出カノ ルス波形が終端により反射されてコンパレータ 16に 入力され、当該コンパレータ 16が検出した反射ノ^レス波形のノ ルス幅 Tを測定する  3 to do. The second measuring unit 36 reflects the output waveform at the end and is input to the comparator 16 and measures the pulse width T of the reflected waveform detected by the comparator 16.
4  Four
[0063] 差分算出部 38は、出力パルス波形のパルス幅 T及び反射パルス波形のパルス幅 [0063] The difference calculating unit 38 calculates the pulse width T of the output pulse waveform and the pulse width of the reflected pulse waveform.
3  Three
Tの差分に基づいて、応答時間の差を算出する。差分算出部 38は、一例として、応 Based on the difference in T, the difference in response time is calculated. As an example, the difference calculation unit 38 responds.
4 Four
答時間の差を、第 1の時間 Tと第 2の時間 Tとの差の 1/2により算出してよい。この  The difference in answer time may be calculated as 1/2 of the difference between the first time T and the second time T. this
1 2  1 2
ような本変形例に係る試験装置 10によれば、図 1に示した試験装置 10と同様に、既 に備えられているドライバ 14を用いてコンパレータ 16の応答時間を調整することがで きる。  According to the test apparatus 10 according to this modified example, the response time of the comparator 16 can be adjusted using the driver 14 already provided, similarly to the test apparatus 10 shown in FIG.
[0064] 以上、本発明(一)側面を実施の形態を用いて説明したが、本発明の技術的範囲 は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変 更または改良を加えることが可能であることが当業者に明らかである。その様な変更 または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、請求の範囲の 記載から明らかである。 [0064] As described above, the aspect (1) of the present invention has been described using the embodiment, but the technical scope of the present invention. Is not limited to the range described in the above embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

Claims

請求の範囲 The scope of the claims
[1] 被試験デバイスを試験する試験装置であって、  [1] A test apparatus for testing a device under test,
前記被試験デバイスに入力すべき試験信号を生成する信号生成部と、 前記試験信号を前記被試験デバイスの入出力ピンに対して出力するドライバと、 前記ドライバの出力端及び前記被試験デバイスの前記入出力ピンに接続され、与 えられる信号を検出するコンパレータと、  A signal generator for generating a test signal to be input to the device under test, a driver for outputting the test signal to an input / output pin of the device under test, an output terminal of the driver and a front of the device under test A comparator connected to the write output pin and detecting a given signal;
前記コンパレータが検出した前記被試験デバイスの出力信号に基づいて、前記被 試験デバイスの良否を判定する判定部と、  A determination unit for determining pass / fail of the device under test based on an output signal of the device under test detected by the comparator;
前記コンパレータにおける、信号の立ち上力 Sりエッジに対する応答時間と、立ち下 力 Sりエッジに対する応答時間との差を検出する応答測定装置と  A response measuring device for detecting a difference between a response time to the rising edge of the signal and a response time to the falling edge of the signal in the comparator;
を備え、  With
前記応答測定装置は、  The response measuring device includes:
前記ドライバの出力端及び前記コンパレータの入力端が、所定の伝播遅延を有す る伝送経路を介して所定電位に終端された状態において、前記ドライバに、立ち上 力 Sりエッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ制御部と、 前記出力波形の立ち上がりエッジ、前記出力波形が終端により反射された反射波 形の立ち下がりエッジ、前記出力波形の立ち下がりエッジ、および前記出力波形が 終端により反射された反射波形の立ち上がりエッジのそれぞれを、前記コンパレータ が検出する時刻に基づいて、前記応答時間の差を算出する差分算出部と を有する試験装置。  In a state where the output terminal of the driver and the input terminal of the comparator are terminated to a predetermined potential via a transmission path having a predetermined propagation delay, the rising edge S and the falling edge are supplied to the driver. A driver control unit that outputs an output waveform including: a rising edge of the output waveform; a falling edge of a reflected waveform reflected by a termination of the output waveform; a falling edge of the output waveform; and the output waveform A test apparatus comprising: a difference calculating unit that calculates a difference in response time based on a time at which the comparator detects each rising edge of the reflected waveform reflected by the terminal end.
[2] 前記所定電位は、接地電位である請求項 1の記載の試験装置。  2. The test apparatus according to claim 1, wherein the predetermined potential is a ground potential.
[3] 前記ドライバ制御部は、前記ドライバに、立ち上がりエッジを有する第 1の出力波形 と、立ち下がりエッジを有する第 2の出力波形とを出力させ、 [3] The driver control unit causes the driver to output a first output waveform having a rising edge and a second output waveform having a falling edge,
前記第 1の出力波形の立ち上力 Sりエッジを前記コンパレータが検出してから、前記 第 1の出力波形が終端により反射された第 1の反射波形の立ち下がりエッジを前記コ ンパレータが検出するまでの第 1の時間を測定する第 1測定部と、  The comparator detects the rising edge of the first output waveform after the comparator detects the falling edge of the first output waveform, and then the falling edge of the first reflected waveform reflected by the termination of the first output waveform. A first measuring unit for measuring a first time until,
前記第 2の出力波形の立ち下力 Sりエッジを前記コンパレータが検出してから、前記 第 2の出力波形が終端により反射された第 2の反射波形の立ち上がりエッジを前記コ ンパレータが検出するまでの第 2の時間を測定する第 2測定部とを更に有し、 前記差分算出部は、前記第 1の時間と前記第 2の時間との差分に基づいて、前記 応答時間の差を算出する After the comparator detects the falling force S edge of the second output waveform, the rising edge of the second reflected waveform reflected by the end of the second output waveform is And a second measuring unit that measures a second time until the comparator detects it, and the difference calculating unit is configured to determine the response time based on a difference between the first time and the second time. Calculate the difference between
請求項 1に記載の試験装置。  The test apparatus according to claim 1.
[4] 前記応答測定装置は、前記差分算出部が算出した前記応答時間の差に基づいて[4] The response measuring device may be configured based on the response time difference calculated by the difference calculation unit.
、前記コンパレータにおける前記立ち上がりエッジに対する応答時間、または前記コ ンパレータにおける前記立ち下がりエッジに対する応答時間の少なくとも一方を調整 する調整部を更に有する請求項 3に記載の試験装置。 4. The test apparatus according to claim 3, further comprising an adjustment unit that adjusts at least one of a response time to the rising edge in the comparator or a response time to the falling edge in the comparator.
[5] 前記ドライバ制御部は、前記ドライバが第 1の出力波形及び前記第 2の出力波形を 出力する時間間隔が、前記伝送経路の伝播遅延時間の 2倍より大きくなるように前記 ドライバを制御し、 [5] The driver control unit controls the driver so that a time interval at which the driver outputs the first output waveform and the second output waveform is greater than twice the propagation delay time of the transmission path. And
前記第 1測定部は、前記第 1の出力波形の立ち上がりエッジと、前記第 1の反射波 形の立ち下がりエッジとを有するパルスのノ ルス幅を、前記第 1の時間として測定し、 前記第 2測定部は、前記第 2の出力波形の立ち下がりエッジと、前記第 2の反射波 形の立ち上がりエッジとを有するパルスのノ ルス幅を、前記第 2の時間として測定す る  The first measurement unit measures a pulse width of a pulse having a rising edge of the first output waveform and a falling edge of the first reflected waveform as the first time, and (2) The measurement unit measures the pulse width of the pulse having the falling edge of the second output waveform and the rising edge of the second reflected waveform as the second time.
請求項 3に記載の試験装置。  The test apparatus according to claim 3.
[6] 当該試験装置は、複数組の前記ドライバ及び前記コンパレータを有し、 [6] The test apparatus includes a plurality of sets of the driver and the comparator,
前記応答測定装置は、  The response measuring device includes:
複数組の前記ドライバ及び前記コンパレータに一対一に対応する、複数の前記第 1測定部、複数の前記第 2測定部、及び複数の前記差分算出部を有し、  A plurality of the first measurement units, a plurality of the second measurement units, and a plurality of the difference calculation units, which correspond one-to-one to the plurality of sets of the drivers and the comparators,
前記ドライバ制御部は、複数の前記ドライバに対して略同時に信号を出力させる 請求項 3に記載の試験装置。  The test apparatus according to claim 3, wherein the driver control unit causes the plurality of drivers to output signals substantially simultaneously.
[7] 前記応答測定装置は、前記ドライバ及び前記コンパレータと、前記被試験デバイス とを接続する伝送経路を、前記被試験デバイス又は前記接地電位のレ、ずれに接続 するかを切り替えるスィッチをさらに有する請求項 3に記載の試験装置。 [7] The response measuring apparatus further includes a switch that switches whether a transmission path connecting the driver and the comparator and the device under test is connected to the device under test or the ground potential. The test apparatus according to claim 3.
[8] 前記応答測定装置は、前記第 1の時間及び前記第 2の時間に基づいて、前記伝送 経路における伝播遅延時間を算出する経路長算出部を更に有する請求項 7に記載 の試験装置。 [8] The response measurement apparatus may further include a path length calculation unit that calculates a propagation delay time in the transmission path based on the first time and the second time. Testing equipment.
[9] 信号を出力するドライバと、 [9] A driver that outputs a signal;
与えられる信号を検出するコンパレータと、  A comparator for detecting a given signal;
前記コンパレータにおける、信号の立ち上力 Sりエッジに対する応答時間と、立ち下 力 Sりエッジに対する応答時間との差を検出する応答測定装置と  A response measuring device for detecting a difference between a response time to the rising edge of the signal and a response time to the falling edge of the signal in the comparator;
を備え、  With
前記応答測定装置は、  The response measuring device includes:
前記ドライバの出力端及び前記コンパレータの入力端が、所定の伝播遅延を有す る伝送経路を介して所定電位に終端された状態において、前記ドライバに、立ち上 力 Sりエッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ制御部と、 前記出力波形の立ち上がりエッジ、前記出力波形が終端により反射された反射波 形の立ち下がりエッジ、前記出力波形の立ち下がりエッジ、および前記出力波形が 終端により反射された反射波形の立ち上がりエッジのそれぞれを、前記コンパレータ が検出する時刻に基づいて、前記応答時間の差を算出する差分算出部と を有するドライバコンパレータチップ。  In a state where the output terminal of the driver and the input terminal of the comparator are terminated to a predetermined potential via a transmission path having a predetermined propagation delay, the rising edge S and the falling edge are supplied to the driver. A driver control unit that outputs an output waveform including: a rising edge of the output waveform; a falling edge of a reflected waveform reflected by a termination of the output waveform; a falling edge of the output waveform; and the output waveform A driver comparator chip comprising: a difference calculation unit that calculates a difference in the response time based on a time at which the comparator detects each rising edge of the reflected waveform reflected by the terminal end.
[10] 前記所定電位は、接地電位である請求項 9の記載のドライバコンパレータチップ。 10. The driver comparator chip according to claim 9, wherein the predetermined potential is a ground potential.
[11] 前記ドライバ制御部は、前記ドライバに、立ち上がりエッジを有する第 1の出力波形 と、立ち下がりエッジを有する第 2の出力波形とを出力させ、 [11] The driver control unit causes the driver to output a first output waveform having a rising edge and a second output waveform having a falling edge,
前記第 1の出力波形の立ち上力 Sりエッジを前記コンパレータが検出してから、前記 第 1の出力波形が終端により反射された第 1の反射波形の立ち下がりエッジを前記コ ンパレータが検出するまでの第 1の時間を測定する第 1測定部と、  The comparator detects the rising edge of the first output waveform after the comparator detects the falling edge of the first output waveform, and then the falling edge of the first reflected waveform reflected by the termination of the first output waveform. A first measuring unit for measuring a first time until,
前記第 2の出力波形の立ち下力 Sりエッジを前記コンパレータが検出してから、前記 第 2の出力波形が終端により反射された第 2の反射波形の立ち上がりエッジを前記コ ンパレータが検出するまでの第 2の時間を測定する第 2測定部と、を更に備え、 前記差分算出部は、前記第 1の時間と前記第 2の時間との差分に基づいて、前記 応答時間の差を算出する  From the time when the comparator detects the falling edge S of the second output waveform until the time when the comparator detects the rising edge of the second reflected waveform reflected by the end of the second output waveform A second measuring unit that measures the second time of the second time, and the difference calculating unit calculates the difference in the response time based on a difference between the first time and the second time
請求項 9に記載のドライバコンパレータチップ。  The driver comparator chip according to claim 9.
[12] 信号を出力するドライバと、与えられる信号を検出するコンパレータとを有するドライ バコンパレータにおける、前記コンパレータの信号の立ち上がりエッジに対する応答 時間と、立ち下力^エッジに対する応答時間との差を検出する応答測定装置であつ て、 [12] A driver having a driver for outputting a signal and a comparator for detecting a given signal. A response measuring device for detecting the difference between the response time of the comparator signal to the rising edge and the response time to the falling force edge of the comparator,
前記ドライバの出力端及び前記コンパレータの入力端が、所定の伝播遅延を有す る伝送経路を介して所定電位に終端された状態において、前記ドライバに、立ち上 力 Sりエッジと、立ち下がりエッジとを有する出力波形を出力させるドライバ制御部と、 前記出力波形の立ち上がりエッジ、前記出力波形が終端により反射された反射波 形の立ち下がりエッジ、前記出力波形の立ち下がりエッジ、および前記出力波形が 終端により反射された反射波形の立ち上がりエッジのそれぞれを、前記コンパレータ が検出する時刻に基づいて、前記応答時間の差を算出する差分算出部と を備える応答測定装置。  In a state where the output terminal of the driver and the input terminal of the comparator are terminated to a predetermined potential via a transmission path having a predetermined propagation delay, the rising edge S and the falling edge are supplied to the driver. A driver control unit that outputs an output waveform including: a rising edge of the output waveform; a falling edge of a reflected waveform reflected by a termination of the output waveform; a falling edge of the output waveform; and the output waveform A response measuring device comprising: a difference calculating unit that calculates a difference in the response time based on a time at which the comparator detects each rising edge of the reflected waveform reflected by the terminal end.
[13] 前記所定電位は、接地電位である請求項 12の記載の応答測定装置。 13. The response measuring apparatus according to claim 12, wherein the predetermined potential is a ground potential.
[14] 前記ドライバ制御部は、前記ドライバに、立ち上がりエッジを有する第 1の出力波形 と、立ち下がりエッジを有する第 2の出力波形とを出力させ、 [14] The driver control unit causes the driver to output a first output waveform having a rising edge and a second output waveform having a falling edge,
前記第 1の出力波形の立ち上力 Sりエッジを前記コンパレータが検出してから、前記 第 1の出力波形が終端により反射された第 1の反射波形の立ち下がりエッジを前記コ ンパレータが検出するまでの第 1の時間を測定する第 1測定部と、  The comparator detects the rising edge of the first output waveform after the comparator detects the falling edge of the first output waveform, and then the falling edge of the first reflected waveform reflected by the termination of the first output waveform. A first measuring unit for measuring a first time until,
前記第 2の出力波形の立ち下力 Sりエッジを前記コンパレータが検出してから、前記 第 2の出力波形が終端により反射された第 2の反射波形の立ち上がりエッジを前記コ ンパレータが検出するまでの第 2の時間を測定する第 2測定部と、を更に備え、 前記差分算出部は、前記第 1の時間と前記第 2の時間との差分に基づいて、前記 応答時間の差を算出する  From the time when the comparator detects the falling edge S of the second output waveform until the time when the comparator detects the rising edge of the second reflected waveform reflected by the end of the second output waveform A second measuring unit that measures the second time of the second time, and the difference calculating unit calculates the difference in the response time based on a difference between the first time and the second time
請求項 12に記載の応答測定装置。  The response measurement device according to claim 12.
[15] 前記ドライバ制御部は、前記ドライバに、立ち上がりエッジ及び立ち下がりエッジを 有する出力パルス波形を出力させ、 [15] The driver control unit causes the driver to output an output pulse waveform having a rising edge and a falling edge,
前記コンパレータが検出した前記出カノ ルス波形のノ ルス幅を測定する第 1測定 部と、  A first measurement unit for measuring a pulse width of the output waveform detected by the comparator;
前記出力ノ^レス波形が終端により反射されて前記コンパレータに入力され、前記コ ンパレータが検出した反射ノ ルス波形のノ ルス幅を測定する第 2測定部と、を更に 備え The output waveform is reflected by the terminal and input to the comparator, and the waveform is reflected. And a second measuring unit for measuring the width of the reflected noise waveform detected by the comparator.
前記差分算出部は、前記出力パルス波形及び前記反射パルス波形のパルス幅の 差分に基づいて、前記応答時間の差を算出する  The difference calculating unit calculates the difference in response time based on a difference in pulse width between the output pulse waveform and the reflected pulse waveform.
請求項 1に記載の試験装置。  The test apparatus according to claim 1.
[16] 前記ドライバ制御部は、前記ドライバに、立ち上がりエッジ及び立ち下がりエッジを 有する出力パルス波形を出力させ、 [16] The driver control unit causes the driver to output an output pulse waveform having a rising edge and a falling edge,
前記コンパレータが検出した前記出カノ ルス波形のノ ルス幅を測定する第 1測定 部と、  A first measurement unit for measuring a pulse width of the output waveform detected by the comparator;
前記出力ノ^レス波形が終端により反射されて前記コンパレータに入力され、前記コ ンパレータが検出した反射ノ ルス波形のノ ルス幅を測定する第 2測定部と、を更に 備え、  A second measuring section that reflects the output waveform at the end and is input to the comparator, and measures the width of the reflected noise waveform detected by the comparator;
前記差分算出部は、前記出力パルス波形及び前記反射パルス波形のパルス幅の 差分に基づいて、前記応答時間の差を算出する  The difference calculating unit calculates the difference in response time based on a difference in pulse width between the output pulse waveform and the reflected pulse waveform.
請求項 9に記載のドライバコンパレータチップ。  The driver comparator chip according to claim 9.
[17] 前記ドライバの出力端及び前記コンパレータの入力端力 S、前記ドライバに、立ち上 力 Sりエッジ及び立ち下がりエッジを有する出カノ ルス波形を出力させるドライバ制御 部と、 [17] a driver control unit that outputs an output waveform having a rising edge and a falling edge to the driver, and an output terminal force S of the driver and an input terminal force S of the comparator;
前記コンパレータが検出した前記出カノ ルス波形のノ ルス幅を測定する第 1測定 部と、  A first measurement unit for measuring a pulse width of the output waveform detected by the comparator;
前記出力ノ^レス波形が終端により反射されて前記コンパレータに入力され、前記コ ンパレータが検出した反射ノ ルス波形のノ ルス幅を測定する第 2測定部と、を更に 備え、  A second measuring section that reflects the output waveform at the end and is input to the comparator, and measures the width of the reflected noise waveform detected by the comparator;
前記差分算出部は、前記出力パルス波形及び前記反射パルス波形のパルス幅の 差分に基づいて、前記応答時間の差を算出する  The difference calculating unit calculates the difference in response time based on a difference in pulse width between the output pulse waveform and the reflected pulse waveform.
請求項 12に記載の応答測定装置。  The response measuring device according to claim 12.
[18] 被試験デバイスを試験する試験装置に備えられた、前記被試験デバイスからの出 力信号を検出するコンパレータの校正方法であって、 前記被試験デバイスに対して試験信号を出力するドライバの出力端、前記コンパレ ータの入力端および所定の伝播遅延を有する伝送経路を接続するとともに、前記伝 送経路における前記ドライバの出力端が接続されていない遠端を前記ドライバから 出力される信号電位を発生する電圧源に接続し、 [18] A comparator calibration method for detecting an output signal from the device under test, provided in a test apparatus for testing the device under test, A driver output terminal for outputting a test signal to the device under test, an input terminal of the comparator, and a transmission path having a predetermined propagation delay are connected, and an output terminal of the driver in the transmission path is connected. The far end not connected to a voltage source that generates a signal potential output from the driver,
前記ドライバから、立ち上がりエッジを有する第 1の出力波形と立ち下がりエッジを 有する第 2の出力波形とを、繰り返し出力し、  The driver repeatedly outputs a first output waveform having a rising edge and a second output waveform having a falling edge,
前記第 1の出力波形の立ち上力 Sりエッジを前記コンパレータが検出してから、前記 第 1の出力波形が前記遠端により反射された第 1の反射波形の立ち下がりエッジを 前記コンパレータが検出するまでの第 1の時間を測定し、  The comparator detects the falling edge of the first reflected waveform in which the first output waveform is reflected by the far end after the comparator detects the rising edge S of the first output waveform. Measure the first time until
前記第 2の出力波形の立ち下力 Sりエッジを前記コンパレータが検出してから、前記 第 2の出力波形が前記遠端により反射された第 2の反射波形の立ち上がりエッジを 前記コンパレータが検出するまでの第 2の時間を測定し、  The comparator detects the rising edge of the second reflected waveform in which the second output waveform is reflected by the far end after the comparator detects the falling edge S edge of the second output waveform. Measure the second time until
前記第 1の時間と前記第 2の時間との差分に基づいて、応答時間の差を算出する 校正方法。  A calibration method for calculating a difference in response time based on a difference between the first time and the second time.
請求項 18の方法により試験装置に備えられたコンパレータを校正することを目的と して前記試験装置に接続される校正装置であって、  A calibration device connected to the test device for the purpose of calibrating a comparator provided in the test device by the method of claim 18, comprising:
前記試験装置に備えられた、被試験デバイスに対して試験信号を出力するドライバ が出力する信号電位と略同一の電圧を発生する電圧源と、  A voltage source that is provided in the test apparatus and generates a voltage substantially the same as a signal potential output by a driver that outputs a test signal to a device under test;
前記ドライバの出力端および前記被試験デバイスからの出力信号を検出する前記 コンパレータの入力端が接続された伝送経路における、前記ドライバの出力端がさ れて!/、な!/、遠端と、前記電圧源とを接続するショート接続治具と  In the transmission path to which the output end of the driver and the input end of the comparator for detecting the output signal from the device under test are connected, the output end of the driver is touched! /, NA! /, The far end, A short connection jig for connecting the voltage source;
を備える校正装置。  A calibration device comprising:
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