WO2008063477A2 - Shifter register for low power consumption application - Google Patents
Shifter register for low power consumption application Download PDFInfo
- Publication number
- WO2008063477A2 WO2008063477A2 PCT/US2007/023782 US2007023782W WO2008063477A2 WO 2008063477 A2 WO2008063477 A2 WO 2008063477A2 US 2007023782 W US2007023782 W US 2007023782W WO 2008063477 A2 WO2008063477 A2 WO 2008063477A2
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- WO
- WIPO (PCT)
- Prior art keywords
- stage
- signal
- input
- voltage
- shift register
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Definitions
- the present invention relates to shift register circuits, and more particularly it) to shift register designs adapted for providing the lowest possible power consumption.
- Fig. 1 illustrates one conventional design for a single stage static shift register.
- this circuit 10 has a signal input in, a clock input is ck and in this configuration complimentary outputs out and out * .
- the circuit is powered by a supply voltage provided by two rail voltages VDD and VSS.
- This specific circuit uses an input signal buffer transistor MPl that feeds a pair of cross-coupled transistors MP2 and MP3 to store the input signal state.
- 20 Inverters INVl and INV2 connected to the output of MPl serve to buffer output voltage and current levels.
- Clock switch transistors MNl, MN2, MN3 and MN4 turn on the shift register to accept a digital input signal, such as from a previous stage.
- Fig. 2 illustrates another known shift register stage circuit 20 that improves to some extent on the design of Fig. 1.
- This shift register stage circuit is adapted to operate with a low voltage swing clock signal, but high voltage swing logic circuits.
- the voltage range between VDD and VSS might be 10 volts to provide high speed.
- the voltage swing from the clock input ck might be much less that — on the order of three volts or so - to reduce power consumption.
- the input and output signals for the circuit 20 of Fig. 2 are as follows:
- the circuit 20 is configured such that an internal node a serves as both a collection point for input signal state and for driving output buffer INVl.
- the number of state transistors has been reduced to only two, MP2 and MPl , arranged in cascode series.
- the ck signal input is fed to the source of MP2.
- the VDD supply voltage is fed to bias the body of transistor MP2.
- the gate of MP2 is fed by complimentary output from the previous shift register stage.
- the gate of MPl is controlled by vgp which is an analog bias voltage.
- MPl is biased such that it conducts when its source voltage is greater than vgp by an amount, Wtp, where Ntp is the threshold voltage of MPl .
- the voltage vgp is thus set so that VEE- vgp ⁇ Wtp where Wtp is the threshold voltage of transistor MPl .
- the circuit 20 of Fig. 2 thus offers reduced power consumption as compared to the circuit 10 of Fig. 1. In designs such as this, however, with a high voltage swing shift register driven by a low voltage swing input clock, internal or external level shifters and clock buffers are thus often necessary.
- the present invention is an improved design for a high voltage shift register which directly accepts low voltage clock signal inputs without using clock buffers.
- a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a , driven directly by a single input transistor. This arrangement allows for reduced power consumption.
- the invention also provides improved speed.
- the speed of the shift register stage is mainly determined by parasitic capacitance connected to the single node a, and a small signal resistance from a clock signal input ck to node a.
- the parasitic capacitance includes wiring capacitance and capacitance of the transistors connected to node a.
- a number of applications can take advantage of the resulting low power consumption and high speed. These include displays designed to use a shift register according to the new invention; portable devices that run on batteries such as video eyewear; electronic viewfinders for camcorder and digital cameras; military systems such as thermal weapon sights and night vision goggles; and other end uses.
- Fig. 1 illustrates a prior art shift register stage that accommodates low voltage swing clock signal inputs.
- Fig. -2 illustrates another prior art shift register stage.
- Fig. 3 illustrates one embodiment of the invention.
- Figs. 4A and 4B illustrate clock signals in more detail.
- Figs. 5A and 5B show how multiple stages of Fig. 3 are combined and a timing diagram.
- Fig. 6 is a high level diagram illustrating a bidirectional shift register.
- Fig. 3 illustrates a circuit 30 that improves over the arrangements of Figs. 1 and 2.
- the clock signal input Ck also drives a stage transistor MPl .
- the gate of MPl is fed from a pair of cascode transistors MP2 and MP3 that set the state at node a as determined by inputs e * and vgp.
- the inverted input from the previous stage e * is fed to the input terminal of inverter INV3 to control the gate of transistor MP3.
- the MP3 drain terminal controls the gate of transistor MPl .
- the source terminal of transistor MP2 is fed from voltage VDD.
- An intended pre-charge input pc * is fed through the single NAND gate together with a reset signal r * .
- the output of the single NAND gate drives the gate terminal of signal buffer transistor MNl .
- the first inverter INVl and second inverter INV2 provide, respectively, the inverted outputs out * and non-inverted output out.
- circuit 20 Operation of circuit 20 is similar to that of circuit 20 of Fig. 2. However, the number of transistors connected to node a is reduced. In addition, through inverters
- node a is shielded from external wiring and devices driven by shift register stage 30.
- the resistance from ck to node a is also reduced from that of a pair of cascode transistors to that of a single transistor.
- vgp is set as VEE-vgp ⁇ Ytp, where Vtp is the threshold voltage of transistor MPl.
- Vtp is the threshold voltage of transistor MPl.
- the diagram of Fig. 4 A can help visualize this situation, where Vsw is the switching threshold of transistor MPl and Vtp is the p- channel threshold voltage of MPl .
- Fig. 4B illustrates, more particularly, the situation of low voltage clock signal ck where the signal value varies from a high rail voltage VDD only down to a voltage VEE that is much greater than the low rail voltage VSS.
- the swing between VEE and VDD may, for example, be only 3.3 volts with the threshold voltage Vu, set to slightly above VEE.
- the speed of the shift register stage 30 of Fig. 3 is thus mainly determined by the parasitic capacitance connected to node a and the small signal resistance from the clock input ck to node a.
- This parasitic capacitance includes wiring capacitance and the capacitance of those transistors that are connected to node a.
- Transistor MPl is in turn biased such that it barely turns on when charging node a. Since this switching operation will already be relatively slow (i.e., it is controlled by a clock signal having a low voltage swing), one wants to avoid introducing extra resistance there.
- INVl no external outputs directly.
- the inverters INVl and INV2 thus also provide isolation from both outputs out and out*, providing circuit 30 with further isolation from the impedances that would be presented by external circuitry.
- the inverters INVl and INV2 may comprise fast 10 volt swing gates that are of less concern in terms of power consumption than the rest of internal shift register 20 circuitry driven by the low voltage swing clock signals. This arrangement also reduces the capacitive load on node a by having only the single connection.
- the circuit 30 of Fig. 3 thus allows node a to swing from VDD to VSS being driven only by a low voltage swing clock signal ck (swinging from a much lower voltage range from 0-3 volts), while minimizing both resistance load and capacitance load.
- the circuit 30 of Fig. 3 thus provides advantages over the circuits 10 or 20 of Fig. 1 and/or Fig. 2 for the following reasons:
- Fig. 5A and 5B illustrate how multiple individual stages 30 of Fig. 3 may be combined to provide a pipelined shift register 50.
- at least three individual stages 30 are required to feed a logic bit 1 from input to output.
- the series connected (pipelined) stages 30-1, 30-2, and 30-3 each have inverted output signals o * feeding the next successive inverted input signal e * .
- a pair of offset clock signals, ckO and ck1 feed respective stages.
- the output of a given stage 30-3 feeds the reset input of the initial stage.
- This circuit thus provides a type of circulating shift register in which a bit value may be shifted from input to output.
- the timing diagram of Fig. 5B illustrates that, for example, on the rising edge of the pre-charge pc signal all stages (o0, o1 , o2, o3, etc.), are reset to a zero logic state.
- the output o0 (from the first stage 30-1) will switch to a high logic value state.
- a similar change occurs in the state of o1 (the output of second stage 30-2).
- output o2 On the next rising edge of clock signal ckO, output o2 will also then reach a high voltage state.
- the feedback connection from the output 02 of the third stage (30-3) back to the first stage 30-1 will then cause the output state ⁇ 0 of the first stage 30-1 to return to a low logic value.
- Fig. 6 is a high level diagram illustrating how a pipelined shift register 50 such as shown in Fig. 5A may be arranged to provide a bidirectional shift register 60.
- One such pipeline 50-1 is arranged to shift from left to right, and a second pipeline 50-2 to shift to right to left.
- Multiplexers 51 - 1 , ...51 -n- 1 , 51 -n connected to each output bit permit selection of the direction to be used.
- Shift registers may be used in many different applications.
- displays of the type described in co- pending U.S. Application No. 11/784,215 filed April 5, 2007, hereby incorporated by reference include an array of pixel elements.
- those pixel elements are controlled by row select lines and column select lines. These select lines may be fed from respective shift registers 50 that are implemented as described herein.
- Displays of that type may in turn be used in digital cameras, digital Single Lens Reflex (SLR) cameras, night vision displays, handheld video games, mobile telephones, video eyewear devices, and other similar products.
- SLR single Lens Reflex
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009537179A JP5358449B2 (en) | 2006-11-20 | 2007-11-14 | Shift register for low power consumption applications |
CN200780042807.XA CN101563722B (en) | 2006-11-20 | 2007-11-14 | Shifter register for low power consumption application |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86005906P | 2006-11-20 | 2006-11-20 | |
US60/860,059 | 2006-11-20 |
Publications (2)
Publication Number | Publication Date |
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WO2008063477A2 true WO2008063477A2 (en) | 2008-05-29 |
WO2008063477A3 WO2008063477A3 (en) | 2008-07-10 |
Family
ID=39430300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/023782 WO2008063477A2 (en) | 2006-11-20 | 2007-11-14 | Shifter register for low power consumption application |
Country Status (4)
Country | Link |
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JP (1) | JP5358449B2 (en) |
CN (1) | CN101563722B (en) |
TW (1) | TWI467586B (en) |
WO (1) | WO2008063477A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102656620B (en) * | 2009-11-13 | 2017-06-09 | 寇平公司 | Method for driving 3D binocular ophthalmoscopes from standard video stream |
US20120297256A1 (en) * | 2011-05-20 | 2012-11-22 | Qualcomm Incorporated | Large Ram Cache |
CN103208251B (en) * | 2013-04-15 | 2015-07-29 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display device |
CN106033683A (en) * | 2015-03-20 | 2016-10-19 | 南京瀚宇彩欣科技有限责任公司 | Shift register apparatus and display apparatus |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5479370A (en) * | 1992-02-20 | 1995-12-26 | Kabushiki Kaisha Toshiba | Semiconductor memory with bypass circuit |
US5869857A (en) * | 1997-04-07 | 1999-02-09 | Chen; Pao-Jung | CMOS photodetectors with wide range operating region |
US6232939B1 (en) * | 1997-11-10 | 2001-05-15 | Hitachi, Ltd. | Liquid crystal display apparatus including scanning circuit having bidirectional shift register stages |
US6934210B2 (en) * | 2001-08-30 | 2005-08-23 | Renesas Technology Corporation | Semiconductor memory circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0192998A (en) * | 1987-10-02 | 1989-04-12 | Seiko Epson Corp | Shift register |
US5949398A (en) * | 1996-04-12 | 1999-09-07 | Thomson Multimedia S.A. | Select line driver for a display matrix with toggling backplane |
US5859630A (en) * | 1996-12-09 | 1999-01-12 | Thomson Multimedia S.A. | Bi-directional shift register |
JP2002368604A (en) * | 2001-06-04 | 2002-12-20 | Nippon Hoso Kyokai <Nhk> | Shift register circuit, and imaging device employing the same, and display device |
TWI220051B (en) * | 2003-05-22 | 2004-08-01 | Au Optronics Corp | Shift register circuit |
-
2007
- 2007-11-14 CN CN200780042807.XA patent/CN101563722B/en active Active
- 2007-11-14 WO PCT/US2007/023782 patent/WO2008063477A2/en active Application Filing
- 2007-11-14 JP JP2009537179A patent/JP5358449B2/en active Active
- 2007-11-20 TW TW96143838A patent/TWI467586B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5479370A (en) * | 1992-02-20 | 1995-12-26 | Kabushiki Kaisha Toshiba | Semiconductor memory with bypass circuit |
US5869857A (en) * | 1997-04-07 | 1999-02-09 | Chen; Pao-Jung | CMOS photodetectors with wide range operating region |
US6232939B1 (en) * | 1997-11-10 | 2001-05-15 | Hitachi, Ltd. | Liquid crystal display apparatus including scanning circuit having bidirectional shift register stages |
US6934210B2 (en) * | 2001-08-30 | 2005-08-23 | Renesas Technology Corporation | Semiconductor memory circuit |
Also Published As
Publication number | Publication date |
---|---|
TW200841347A (en) | 2008-10-16 |
CN101563722A (en) | 2009-10-21 |
CN101563722B (en) | 2013-01-16 |
TWI467586B (en) | 2015-01-01 |
JP5358449B2 (en) | 2013-12-04 |
JP2010510612A (en) | 2010-04-02 |
WO2008063477A3 (en) | 2008-07-10 |
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