WO2008081968A1 - Manufacturing method of semiconductor chip - Google Patents
Manufacturing method of semiconductor chip Download PDFInfo
- Publication number
- WO2008081968A1 WO2008081968A1 PCT/JP2007/075368 JP2007075368W WO2008081968A1 WO 2008081968 A1 WO2008081968 A1 WO 2008081968A1 JP 2007075368 W JP2007075368 W JP 2007075368W WO 2008081968 A1 WO2008081968 A1 WO 2008081968A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor wafer
- semiconductor
- resist film
- plasma
- dicing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
An object is to provide a manufacturing method of a semiconductor chip, by which while a semiconductor wafer is not broken when the semiconductor wafer is transported before plasma dicing is carried out, a time required for the plasma dicing can be shortened, so that a manufacturing efficiency of the semiconductor chips can be improved. After a resist film 6 has been formed on a ground rear plane 1q of a semiconductor wafer 1, partial portions (6a and 1b) of cutting margin areas (6a, 1b, 1c, 3c) along dicing lines 2 are removed by a blade 13 corresponding to a mechanical cutting means, and thickness 't' of remaining cutting margin areas 1c of the semiconductor wafer 1 along a thickness direction thereof are made thinner, which never causes any problem when the semiconductor wafer 1 is transported. Thereafter, all of the remaining cutting margin areas (1c, 3a) are removed by performing a plasma etching process.
Description
DESCRIPTION
MANUFACTURINGMETHOD OF SEMICONDUCTOR CHEP
Technical Field
The present invention is related to a semiconductor chip manufacturing method for obtaining a plurality of semiconductor chips by dividing a semiconductor wafer where a plurality of semiconductor elements have been formed on a circuit forming plane of the semiconductor wafer.
Background Art
Very recently, as new technical ideas for dividing semiconductor wafers into individual semiconductor chips, a specific attention has been paid to plasma dicing having small damage while the semiconductor wafers are cut. The above-described plasma dicing implies the following dicing technique. That is, while a resist film is formed on a plane (namely, rear plane) of a semiconductor wafer, which is located opposite to a circuit forming plane thereof, grooves (namely, boundary grooves) are formed in this resist film along dicing lines used to segment semiconductor elements from each other; and thereafter, while the resist film where these grooves have been formed is employed as a mask, the semiconductor wafer is plasma-etched so as to cut and segment the semiconductor wafer into individual semiconductor chips in a separation manner. Generally speaking, in this plasma dicing, a mask is fabricated by employing a photolithographic technique. However, when the mask is fabricated by utilizing the photolithographic technique, higher cost is required. As a result, maskless type plasma dicing has been proposed (refer to patent publication 1). That is, grooves are formed in a surface of a semiconductor wafer by operating mechanical cutting means without employing a mask, and then, plasma dicing is carried out from the grooves.
[Patent Publication 1] JP-A-2003-197569
Disclosure of the Invention
However, the method described in the above-mentioned patent publication 1 has the below-mentioned problem. That is, normally, since an etching rate by the plasma
dicing requires approximately 2 μm/minute, if a thickness of a cutting margin area after a groove machining has been performed is excessively thick, then a lengthy time is unnecessarily required in a dicing step, so that a manufacturing efficiency is deteriorated. On the other hand, the above-described method has another problem. That is, if a thickness of a cutting margin area after a groove machinig has been performed is excessively thin, then a semiconductor wafer may be easily broken, so that it is practically difficult to subsequently transport the semiconductor wafer (namely, semiconductor wafer is transported into vacuum chamber for plasma etching treatment etc.).
As a consequence, the present invention has an object to provide a semiconductor chip manufacturing method capable of improving a manufacturing efficiency of semiconductor chips by shortening a time required for performing plasma dicing, while a semiconductor wafer is not broken, and the like when the semiconductor wafer is transported before the plasma dicing is carried out.
According to the invention, a semiconductor chip manufacturing method to obtain a plurality of semiconductor chips, in that a semiconductor wafer where a plurality of semiconductor elements have been formed on a circuit forming plane of the semiconductor wafer is divided along dicing lines for segmenting the semiconductor elements from each other, the method comprising: a rear plane grinding step for grinding a rear plane of the semiconductor wafer, which is located opposite to the circuit forming plane; a resist film forming step for forming a resist film on the ground rear plane of the semiconductor wafer; a groove machining step for removing by mechanical cutting means, both all of cutting margin areas of the resist film in a thickness direction of the resist film along the dicing lines, and also, a portion of a cutting margin area of the semiconductor wafer on the side of the resist film in a thickness direction of the semiconductor wafer; a plasma dicing step for performing a plasma etching process with respect to the semiconductor wafer while the resist mask is employed as a mask in order that all of remaining cutting margin areas of the semiconductor wafer in the thickness direction thereof along the dicing lines are removed; and a resist film removing step for removing the resist film from the semiconductor wafer after the plasma dicing step is performed.
A semiconductor chip manufacturing method recited in Claim 2 is featured by that in the semiconductor chip manufacturing method recited in Claim 1, a thickness of the remaining cutting area of the semiconductor wafer in the thickness direction thereof along the dicing lines after the groove machining step is performed is 50 to 200 μm.
In the present invention, after the resist film has been formed on the ground rear plane of the semiconductor wafer, the partial portions of the cutting margin areas along the dicing lines are removed by mechanical cutting means, and the thicknesses of the remaining cutting margin areas of the semiconductor wafer along the thickness direction thereof are made thinner, which never causes any problem when the semiconductor wafer is transported. Thereafter, all of the remaining cutting margin areas are removed by performing the plasma etching process. As a consequence, the time required in the plasma dicing can be largely shortened, as compared with the required time when all of the cutting margin areas are removed by performing the plasma etching process so as to cut and segment the semiconductor wafer. As a consequence, in accordance with the present invention, while the semiconductor wafer is not broken when the semiconductor wafer is transported before the plasma dicing is carried out, the time required for the plasma dicing can be shortened, so that the manufacturing efficiency of the semiconductor chips can be largely improved.
Also, since the plasma etching process is carried out after the resist film has been formed on the semiconductor wafer, radicals decomposed within the plasma atmosphere are concentrated in the vicinity of the mechanical cut/removed portions of the semiconductor wafer, so that the etching rate can be improved, and thus, the highspeed plasma etching process can be realized. Moreover, the resist pattern of the resist film is formed at the same time when the cutting margin areas are cut and removed by the mechanical cutting means, so that the high cost photolithography is no longer required.
Also, in the case that the semiconductor wafer is cut and segmented into the semiconductor chips in the final cutting stage, this cutting operation is carried out by the plasma etching treatment whose cutting damage is small. As a result, when the semiconductor wafer is cut and segmented and this semiconductor wafer has a fragile low
dielectric substance layer on the plane thereof (namely, circuit forming plane) which is located opposite to the plane thereof where the resist film is formed, the above-described semiconductor chip manufacturing method of the present invention becomes especially advantage.
Brief Description of the Drawings
Fig. 1 is a perspective view of a blade cutting apparatus used in one embodiment mode of the present invention.
Fig. 2 is a sectional view of a plasma processing apparatus used in the embodiment mode of the present invention.
Fig. 3 is a flow chart for describing step sequences as to a method for manufacturing a semiconductor chip according to the embodiment mode of the present invention.
Figs. 4(a) to 4(d) are explanatory diagrams for explaining the semiconductor chip manufacturing method according to the embodiment mode of the present invention.
Figs. 5(a) to 5(c) are explanatory diagrams for explaining the semiconductor chip manufacturing method according to the embodiment mode of the present invention.
Fig. 6(a) to 6(d) are explanatory diagrams for explaining the semiconductor chip manufacturing method according to the embodiment mode of the present invention.
Best Mode for Carrying Out the Invention
Firstly, a description is made of structures of the blade cutting apparatus 10 and the plasma processing apparatus 30, which are utilized in the embodiment mode of the present invention, with reference to Fig. 1 and Fig. 2.
Referring now to drawings, a description is made of embodiment modes of the present invention. In Fig. 1, the blade cutting apparatus 10 is arranged by containing a wafer holding unit 11, a transport plate 12, a blade 13, a blade holding unit 14, a blade transporting mechanism 16, a blade driving mechanism 17, a wafer transporting mechanism 18, a control unit 19, a recognizing unit 20, an operating/inputting unit 21, a work data storage unit 22, and the like. The wafer holding unit 11 holds a semiconductor wafer 1 in a horizontal attitude, which should be processed. The transport plate 12 has
been provided above the wafer holding unit 11 in a freely transportable manner. The blade holding unit 14 has been fixed on the transport plate 12 and holds the blade 13 in a freely rotatable manner around a horizontal rotation axis (it is so assumed that direction along which rotation axis is extended is defined as X axis). The blade transporting mechanism 16 transports the transport plate 12 in addition to a camera 15 fixed on the transport plate 12. The blade driving mechanism 17 rotatably drives the blade 13. The wafer transporting mechanism 18 transports (including rotation) the wafer holding unit 11. The control unit 19 controls operations of these mechanisms 16, 17, 18. The recognizing unit 20 performs a positional recognition of the semiconductor wafer 1 from an image photographed by the camera 15. The operating/inputting unit 21 supplies an operation signal and an input signal to the control unit 19. The work data storage unit 22 is connected to the control unit 19.
While the wafer holding unit 11 has contained a fixing/holding member such as a vacuum chuck which fixes/holds the semiconductor wafer 1 on an upper plane thereof, the semiconductor wafer 1 is fixed/held by this fixing/holding member in such a manner that a plane of this semiconductor wafer 1 is directed to an upper direction where a groove machining is carried out by employing the blade 13. The blade transporting mechanism 16 transports the transport plate 12 along both an X-axis direction and a Z-axis direction (upper/lower directions) so as to transport both the blade holding unit 14 and the camera 15 fixed on the transport plate 12 in an upper space of the semiconductor wafer 1 under control of the control unit 19. The blade driving mechanism 17 rotatably drives the blade 13 around the rotation axis under control of the control unit 19. The wafer transporting mechanism 18 transports the wafer holding unit 11 along a Y-axis direction (namely, direction intersected with X axis within horizontal plane), and also, rotates the wafer holding unit 11 around an upper/lower rotation axis which is located parallel to the Z axis under control of the control unit 19. The camera 15 photographs the semiconductor wafer 1 positioned just under the camera 15 by utilizing infrared light. The recognizing unit 20 performs a positional recognition of the semiconductor wafer 1 based upon the photographed image of the camera 15, and then, transmits positional information about the semiconductor wafer 1 obtained from the positional recognition to the control unit 19.
The control unit 19 grasps a positional relationship between the semiconductor wafer 1 and the blade 13 based upon the positional information of the semiconductor wafer 1 transmitted from the recognizing unit 20. The operating/inputting unit 21 supplies various sorts of input signals to the control unit 19 in response to operations made by an operator. While data about grid-shaped dicing lines 2 has been stored in the work data storage unit 22 and the grid- shaped dicing lines 2 constitute segment lines utilized when the semiconductor wafer 1 is cut and segmented into individual semiconductor chips, the control unit 19 controls operations as to both the blade transporting mechanism 16 and the wafer transporting mechanism 18 in such a manner that the blade 13 may be relatively moved with respect to the semiconductor wafer 1 along the dicing lines 2 whose data has been stored in the work data storage unit 22.
In Fig. 2, the plasma processing apparatus 30 has been constituted by a vacuum chamber 31, a lower electrode 32, an upper electrode 33, a high frequency power supply unit 34, a cooling unit 35, a gas supplying path 36, an oxygen gas supplying unit 37, a fluorine-series gas supplying unit 38, a first opening/closing valve 39, a first flow rate control valve 40, a second opening/closing valve 41, and a second flow rate control valve 42. Both the lower electrode 32 and the upper electrode 33 have been provided within the vacuum chamber 31. The high frequency power supply unit 34 applies a high frequency voltage to the lower electrode 32. The cooling unit 35 circulates a coolant within the lower electrode 32. The gas supplying path 36 has been extended from the internal portion of the upper electrode 33 outside the vacuum chamber 31, and has been forked outside the vacuum chamber 31. The oxygen gas supplying unit 37 has been connected to one-sided branch path (will be referred to as "first branch path 36a" hereinafter) of the forked gas supply path 36. The fluorine-series gas supplying unit 38 has been connected to the other-sided branch path (will be referred to as "second branch path 36b" hereinafter) of the forked gas supply path 36. Both the first opening/closing valve 39 and the first flow rate control valve 40 have been interposed in the first branch path 36a. Both the second opening/closing valve 41 and the second flow rate control valve 42 have been interposed in the first branch path 36b.
An internal space of the vacuum chamber 31 has been provided as a tightly closed
space employed in order to perform a plasma process operation with respect to the semiconductor wafer 1. The lower electrode 32 has been provided within the vacuum chamber 31 in such a manner that a holding plane of the semiconductor wafer 1 is set upwardly, whereas the upper electrode 33 has been provided within the vacuum chamber 31 in such a manner that a lower plane of this upper electrode 33 is located opposite to an upper plane of the lower electrode 32.
While both a wafer holding mechanism (not shown) constructed of a vacuum chuck and an electrostatic absorbing mechanism, and a ring-shaped frame 32a made of an electrically insulating material have been provided on the upper plane of the lower electrode 32, the semiconductor wafer 1 is supported in such a manner that the plane thereof to which the plasma processing operation is performed is directed upwardly and a peripheral portion thereof is surrounded by the frame 32a, and is fixed on the upper plane of the lower electrode 32 by the wafer holding mechanism.
While oxygen gas (alternatively, mixture gas whose major gas component is oxygen may be employed) has been filled into the oxygen gas supplying unit 37, the oxygen gas is supplied via the first branch path 36a and the gas supply path 36 to the upper electrode 33 when the first opening/closing valve 39 has been opened (second opening/closing valve 41 has been closed). A flow rate of the oxygen gas from the oxygen gas supplying unit 37 to the upper electrode 33 is adjusted by controlling an open degree of the first flow rate control valve 40. Also, while fluorine-series gas, for example, surfer hexafluoride has been filled into the fluorine-series gas supplying unit 38, the fluorine-series gas is supplied via the second branch path 36b and the gas supply path 36 to the upper electrode 33 when the second opening/closing valve 41 has been opened (first opening/closing valve 39 has been closed). A flow rate of the fluorine-series gas from the fluorine-series gas supplying unit 38 to the upper electrode 33 is adjusted by controlling an open degree of the second flow rate control valve 42.
While a porous plate 33a having a flat plate shape has been provided on the lower plane of the upper electrode 33, the oxygen gas and the fluorine-series gas supplied via the gas supply path 36 are uniformly sprayed onto the upper plane of the lower electrode 32
via this porous plate 33 a.
Next, a description is made of a method for manufacturing a semiconductor chip with reference to a flow chart of Fig. 3, and step explanatory diagrams shown in Fig. 4, Fig. 5, and Fig. 6. While a low dielectric substance layer 3 has been provided on a circuit forming plane Ip of the semiconductor wafer 1, a plurality of semiconductor elements 4 have been formed on the circuit forming plane Ip under such a condition that the low dielectric substance layer 3 is employed as an insulating layer (Fig. 4(a)).
As previously explained, in order to obtain a plurality of semiconductor chips 1'
(Fig. 6(d)) by dividing the semiconductor wafer 1 where the plurality of semiconductor elements 4 have been formed on the circuit forming plane Ip along the dicing lines 2 for segmenting the semiconductor elements 4 from each other, firstly, as indicated in Fig. 4(b), a sheet-shaped protection tape (for example, UV tape) 5 having an adhesive characteristic is adhered on the circuit forming plane Ip of the semiconductor wafer 1 (protection tape adhering step Sl shown in Fig. 3).
After, the protection tape adhering step Sl has been accomplished, as shown in Fig. 4(c), a rear plane Iq of the semiconductor wafer 1 is ground by employing a rear plane grinding apparatus 50 (rear plane grinding step S2 shown in Fig. 3). The rear plane Iq is located opposite to the circuit forming plane Ip.
The rear plane grinding apparatus 50 is made of a rotary table 51 and a rotary grinder 52 provided above the rotary table 51. The semiconductor wafer 1 is mounted on an upper plane of the rotary table 51 in such a manner that the rear plane Iq of the semiconductor wafer 1 is directed to the upper direction. When the semiconductor wafer 1 is mounted on the rotary table 51, the rotary grinder 52 is depressed from the upper direction against the rear plane Iq of the semiconductor wafer 1 (arrow "A" shown in Fig. 4(c)). Also, while the rotary table 51 and the rotary grinder 52 are being rotated around an upper axis and a lower axis respectively (arrows B and C indicated in Fig. 4(c)), the rotary grinder 52 is swung within the horizontal plane (arrow D shown in Fig. 4(c)). As a result, the rear plane Iq of the semiconductor wafer 1 is ground, so that the thickness of the
semiconductor wafer 1 is made thinner than approximately 600 to 150 μm. It should be understood that since such a damaged layer (namely, layer which has not already been made from single crystal) having a depth of approximately 1 μm is formed in the rear plane Iq of the semiconductor wafer 1 after this rear plane Iq has been ground, either a polishing treatment or a plasma etching treatment is carried out with respect to the rear plane Iq of the semiconductor wafer 1 dismounted from the rear plane grinding apparatus 50 so as to remove the damaged layer.
After the rear plane grinding step S2 has been accomplished, as shown in Fig. 5 (a), a photosensitive resist film 6 is formed on the rear plane Iq of the semiconductor wafer 1 (resist film forming step S3 indicated in Fig. 3). This resist film 6 functions as a mask in a plasma dicing step S6 which will be performed later.
After the resist film forming step S3 has been accomplished, the semiconductor wafer 1 is mounted on the wafer holding unit 11 of the blade cutting apparatus 10. At this time, the semiconductor wafer 1 is set in such a manner that the rear plane Iq where the resist film 6 has been formed is directed to the upper direction. Then, as shown in Fig. 5(b) and Fig. 5(c), all of cutting margin areas 6a of the resist film 6 along the thickness direction of this resist film 6, which is located along the dicing lines 2, and also, portions Ib of a cutting margin areas Ia of the semiconductor wafer 1 along the thickness direction of the semiconductor wafer 1, which are located along the dicing lines 2, are ground by the rotated blade 3 so as to be removed (groove machining step S4 shown in Fig. 3). The above-described portions Ib of the cutting margin area Ia are located on the side of the resist film 6. As a result, the semiconductor wafer 1 is brought into such a condition that the semiconductor wafer 1 has been connected along the in-plane direction of the semiconductor wafer 1 by remaining cutting margin area Ic within the cutting margin areas Ia along the dicing lines 2, while the cutting margin areas Ic are left on the side of the low dielectric substance layer 3.
In this case, as previously described, while the data of the dicing lines 2 has been stored in the work data storage unit 22, the control unit 19 transports both the transport plate 12 and the wafer holding unit 11 (namely, both blade 13 and semiconductor wafer 1
are transported) based upon the data of the dicing lines 2 stored in this work data storage unit 22 and the position of the semiconductor wafer 1 acquired by being photographed by the camera 15. Since the wafer holding unit 11 is transported along the Y-axis direction under such a condition that the rotated blade 13 is contacted to the semiconductor wafer 1, a groove machining can be carried out along one dicing line 2 located parallel to the Y axis. As a result, this groove machining is performed by combining two transporting modes with each other, so that the groove machining along all of the dicing lines 2 arrayed in the grid shape can be carried out. Namely, in one transporting mode, the transport plate 12 is transported in a step form along the X-axis direction, whereas in the other transporting mode, the wafer holding unit 11 is rotated by an angle of 90 degrees around the Z axis.
In the above-described groove machining step S4, a thickness "t" (refer to Fig. 5(c)) of the remaining cutting margin areas Ic of the semiconductor wafer 1, which are directed to the thickness direction of the semiconductor wafer 1 along the dicing lines 2, become approximately 50 to 200 μm. It should be understood that the thickness values of 50 μm to 200 μm are equal to such values capable of securing sufficiently high strengths by which there is no problem in a wafer carrying-in step S5 performed after the above-described groove machining step S4 has been accomplished, namely, in such a step S 5 that the semiconductor wafer 1 is carried in the vacuum chamber 31. If a thickness become smaller than the above-described thickness range (50 to 200 μm), then there is a risk that the semiconductor wafer 1 under transportation is broken. If a thickness becomes larger than the above-described thickness range, then there is such an inconvenient possibility that a time required for executing a plasma etching process (plasma dicing step S6) subsequent to the groove machining step S4 is prolonged. It should also be noted that in this groove machining step S4, the resist film 6 along the dicing lines 2 is removed. As a consequence, a resist pattern which is required in a plasma etching process (will be performed later) has been just formed on the remaining resist film 6.
After the groove machining step S4 is accomplished, the semiconductor wafer 1 is dismounted from the wafer holding unit 11 of the blade cutting apparatus 10, and the dismounted semiconductor wafer 1 is carried into the vacuum chamber 31 of the plasma
processing apparatus 30, and then, the semiconductor wafer 1 is fixed on the upper plane of the lower electrode 32 (wafer carrying-in step S 5 shown in Fig. 3). At this time, the semiconductor wafer 1 is set in such a manner that the rear plane Iq where the resist film 6 has been formed is directed upwardly.
After the wafer carrying-in step S5 is accomplished, while the resist film 6 is employed as a mask, a plasma etching process operation is performed by conducting the fluorine-series gas with respect to the semiconductor wafer 1 (plasma dicing step S6 shown in Fig. 3).
In the above-described plasma dicing step S6, first of all, the second opening/closing valve 41 is opened under such a condition that the first opening/closing valve 39 is closed so as to supply the fluorine-series gas from the fluorine-series gas supplying unit 38 to the upper electrode 33. As a result, the fluorine-series gas is sprayed from the upper electrode 33 via the porous plate 33a onto the upper plane of the semiconductor wafer 1. When the high frequency power supply unit 34 is driven under this condition in order to apply a high frequency voltage to the lower electrode 32, plasma Pf of the fluorine-series gas is generated between the lower electrode 32 and the upper electrode 33 (Fig. 6(a)).
The generated plasma Pf of the fluorine-series gas etches the semiconductor wafer 1 from the portions from which the resist film 6 has been removed in the groove machining step S4. As a result, all of the remaining cutting margin areas of the thickness direction as to the semiconductor wafer 1 along the dicing lines 2 are removed, while these remaining cutting margin areas correspond to both the cutting margin areas Ic of the thickness direction of the semiconductor wafer 1 and the cutting margin areas 3 a of the low dielectric substance layer 3 along the thickness direction thereof. Then, the semiconductor wafer 1 is cut in a batch manner along the dicing lines 2 into individual semiconductor chips 1 ' equipped with the resist films 6 (see Fig. 6(b)). It should also be understood that while the etching process of the semiconductor wafer 1 is carried out by conducting the plasma Pf of the fluorine-series gas, the cooling unit 35 is driven so as to circulate the coolant within the lower electrode 32 in order to avoid that the temperature of
this semiconductor wafer 1 is increased by heat of the plasma Pt.
After the plasma dicing step S6 is accomplished, subsequently, plasma Po of the oxygen gas is generated within the vacuum chamber 31 so as to remove ashing of the resist film 6 left on the upper plane (rear plane Iq) of the semiconductor wafer 1 (namely, such a wafer condition that respective cut and segmented semiconductor chips 1 ' have been connected to each other by protection tape 5) in a resist film removing step S7 shown in Fig. 3.
In order to perform this ashing removing operation, first of all, the first opening/closing valve 39 is opened under such a condition that the second opening/closing valve 41 is closed so as to supply the oxygen gas from the oxygen gas supplying unit 37 to the upper electrode 33. As a result, the oxygen gas is sprayed from the upper electrode 33 via the porous plate 33 a onto the upper plane of the semiconductor wafer 1. When the high frequency power supply unit 34 is driven under this condition in order to apply a high frequency voltage to the lower electrode 32, plasma Po of the oxygen gas is generated between the lower electrode 32 and the upper electrode 33 (Fig. 6(c)). This plasma Po of the oxygen gas ashes the resist film 6 corresponding to an organic article, so that the resist film 6 is removed from the rear plane Iq of the semiconductor wafer 1 (of each of semiconductor chips 1 ') (refer to Fig. 6(d)). It should also be noted that in the above-described resist film removing step S7, while the ashing removing operation of the resist film 6 is carried out by conducting the plasma Po of the oxygen gas, the cooling unit 35 is driven so as to circulate the coolant within the lower electrode 32 in order to avoid that the temperature of this semiconductor wafer 1 is increased by heat of the plasma Po.
After ashing of the resist film 6 has been completely removed, the semiconductor wafer 1 (namely, such a semiconductor wafer condition that cut and segmented semiconductor chips 1 ' have been connected to each other by UV tape 5) is transported out from the vacuum chamber 31 (wafer carrying-out step S8 indicated in Fig. 3).
As a consequence, the manufacturing operation of the semiconductor chips 1' is accomplished, and after the semiconductor wafer 1 is transported out from the vacuum
chamber 31, if the protection tape 5 adhered onto the circuit forming plane Ip of the semiconductor wafer 1 is stretched, then the cut and segmented semiconductor chips 1 ' can be brought into such a condition that these semiconductor chips 1' are separated from each other. Then, if the protection tape 5 is a UV tape, then adhesive force of this UV tape may disappear when ultraviolet rays are irradiated onto this protection tape 5. As a result, the semiconductor chips 1' may be easily exfoliated from the protection tape 5.
As previously described, in the manufacturing method for the semiconductor chip according to the present embodiment mode, after the resist film 6 has been formed on the ground rear plane Iq of the semiconductor wafer 1, the partial portions (6a and Ib) of the cutting margin areas (6a, Ib, Ic, 3a) along the dicing lines 2 are removed by the blade 13 corresponding to the mechanical cutting means, and the thickness "t" of the remaining cutting margin areas Ic of the semiconductor wafer 1 along the thickness direction thereof are made thinner, which never causes any problem when the semiconductor wafer 1 is transported. Thereafter, all of the remaining cutting margin areas (Ic, 3 a) are removed by performing the plasma etching process. As a consequence, the time required in the plasma dicing can be largely shortened, as compared with the required time when all of the cutting margin areas (6a, Ib, Ic, 3a) are removed by performing the plasma etching process so as to cut and segment the semiconductor wafer 1. As a consequence, in accordance with the semiconductor chip manufacturing method of the present embodiment mode, while the semiconductor wafer 1 is not broken when the semiconductor wafer 1 is transported before the plasma dicing is carried out, the time required for the plasma dicing can be shortened, so that the manufacturing efficiency of the semiconductor chips 1' can be largely improved.
Also, since the plasma etching process is carried out after the resist film 6 has been formed on the semiconductor wafer 1, radicals decomposed within the plasma atmosphere are concentrated in the vicinity of the mechanical cut/removed portions of the semiconductor wafer 1, so that the etching rate (for example, 20 to 25 μm/minute) can be improved, and thus, the high speed plasma etching process can be realized. Moreover, the resist pattern of the resist film 6 is formed at the same time when the cutting margin areas are cut and removed by the blade 13, so that the high cost photolithography is no
longer required. In this case, while the resist film 6 is not formed on the semiconductor wafer 1, even when a portion of the surface (rear plane Iq) of the semiconductor wafer 1 is cut and removed by the blade 13 along the dicing lines 2 and thereafter the plasma etching process is carried out, the semiconductor wafer 1 may be diced along the dicing lines (above-explained patent publication 1). However, in this case, the radicals decomposed within the plasma atmosphere are dispersed not only near the cut and removed portions of the semiconductor wafer 1 by the blade 13, but also the entire surface (entire rear plane Iq) of the semiconductor wafer 1. As a result, an etching rate of the semiconductor wafer 1 becomes 2 μm/minute, namely becomes very small.
Also, in the case that the semiconductor wafer 1 is cut and segmented into the semiconductor chips 1 ' in the final cutting stage, this cutting operation is carried out by the plasma etching treatment whose cutting damage is small. As a result, as represented in the present embodiment mode, when the semiconductor wafer 1 is cut and segmented and this semiconductor wafer 1 has the fragile low dielectric substance layer 3 on the plane thereof (namely, circuit forming plane 1) which is located opposite to the plane thereof where the resist film 6 is formed, the above-described semiconductor chip manufacturing method of the present embodiment mode becomes especially advantage.
Industrial Applicability
In the semiconductor chip manufacturing method, while the semiconductor wafer is not broken when the semiconductor wafer is transported before the plasma dicing is carried out, the time required for the plasma dicing can be shortened, so that the manufacturing efficiency of the semiconductor chips can be largely improved. This application is based upon and claims the benefit of priority of Japanese
Patent Application No. 2006-349189 filed on December 26, 2005, the contents of which are incorporated herein by reference in its entirety.
Claims
1. A semiconductor chip manufacturing method to obtain a plurality of semiconductor chips, in that a semiconductor wafer where a plurality of semiconductor elements have been formed on a circuit forming plane of the semiconductor wafer is divided along dicing lines for segmenting the semiconductor elements from each other, the method comprising: a rear plane grinding step for grinding a rear plane of the semiconductor wafer, which is located opposite to the circuit forming plane; a resist film forming step for forming a resist film on the ground rear plane of the semiconductor wafer; a groove machining step for removing by mechanical cutting means, both all of cutting margin areas of the resist film in a thickness direction of the resist film along the dicing lines, and also, a portion of a cutting margin area of the semiconductor wafer on the side of the resist film in a thickness direction of the semiconductor wafer; a plasma dicing step for performing a plasma etching process with respect to the semiconductor wafer while the resist mask is employed as a mask in order that all of remaining cutting margin areas of the semiconductor wafer in the thickness direction thereof along the dicing lines are removed; and a resist film removing step for removing the resist film from the semiconductor wafer after said plasma dicing step is performed.
2. A semiconductor chip manufacturing method as claimed in claim 1 wherein: a thickness of the remaining cutting area of said semiconductor wafer in the thickness direction thereof along the dicing lines after said groove machining step is performed is 50 to 200 μm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006-349189 | 2006-12-26 | ||
| JP2006349189A JP2008159985A (en) | 2006-12-26 | 2006-12-26 | Method for manufacturing semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008081968A1 true WO2008081968A1 (en) | 2008-07-10 |
Family
ID=39232802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2007/075368 WO2008081968A1 (en) | 2006-12-26 | 2007-12-26 | Manufacturing method of semiconductor chip |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2008159985A (en) |
| TW (1) | TW200830392A (en) |
| WO (1) | WO2008081968A1 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100311223A1 (en) * | 2009-06-05 | 2010-12-09 | Chun Jung Hwan | Method Of Dicing Wafer Using Plasma |
| US7985661B2 (en) | 2007-08-07 | 2011-07-26 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US7989319B2 (en) | 2007-08-07 | 2011-08-02 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US8012857B2 (en) | 2007-08-07 | 2011-09-06 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US8384231B2 (en) | 2010-01-18 | 2013-02-26 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
| US8962452B2 (en) | 2007-08-07 | 2015-02-24 | Semiconductor Components Industries, Llc | Semiconductor die singulation apparatus and method |
| US9136173B2 (en) | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
| US9165833B2 (en) | 2010-01-18 | 2015-10-20 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
| US9275957B2 (en) | 2010-01-18 | 2016-03-01 | Semiconductor Components Industries, Llc | EM protected semiconductor die |
| US9385041B2 (en) | 2014-08-26 | 2016-07-05 | Semiconductor Components Industries, Llc | Method for insulating singulated electronic die |
| US9418894B2 (en) | 2014-03-21 | 2016-08-16 | Semiconductor Components Industries, Llc | Electronic die singulation method |
| US9484260B2 (en) | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
| US10366923B2 (en) | 2016-06-02 | 2019-07-30 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
| US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
| US10818551B2 (en) | 2019-01-09 | 2020-10-27 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5141390B2 (en) | 2008-06-19 | 2013-02-13 | ヤマハ株式会社 | Speaker device and speaker system |
| CN102760699B (en) * | 2011-04-27 | 2014-11-05 | 无锡华润安盛科技有限公司 | Method of cutting wafer used for preparation of sensor chip into grains |
| JP6504750B2 (en) * | 2014-05-07 | 2019-04-24 | 株式会社ディスコ | Wafer processing method |
| DE102015100783A1 (en) * | 2015-01-20 | 2016-07-21 | Infineon Technologies Ag | Method for dicing a wafer and semiconductor chip |
| DE102015002542B4 (en) | 2015-02-27 | 2023-07-20 | Disco Corporation | wafer division process |
| DE102015204698B4 (en) | 2015-03-16 | 2023-07-20 | Disco Corporation | Process for dividing a wafer |
| DE102015216619B4 (en) | 2015-08-31 | 2017-08-10 | Disco Corporation | Method for processing a wafer |
| JP6740081B2 (en) * | 2016-10-20 | 2020-08-12 | 株式会社ディスコ | Wafer processing method |
| KR102030398B1 (en) * | 2017-07-28 | 2019-10-10 | (주) 예스티 | A method and system for dicing wafer |
| JP2019079884A (en) * | 2017-10-23 | 2019-05-23 | 株式会社ディスコ | Wafer processing method |
| JP7083716B2 (en) * | 2018-07-20 | 2022-06-13 | 株式会社ディスコ | Wafer processing method |
| JP2020017629A (en) * | 2018-07-25 | 2020-01-30 | 株式会社ディスコ | Wafer processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465158B1 (en) * | 1999-10-26 | 2002-10-15 | Disco Corporation | Semiconductor wafer dividing method |
| WO2006048230A1 (en) * | 2004-11-01 | 2006-05-11 | Xsil Technology Limited | Increasing die strength by etching during or after dicing |
| US20060166465A1 (en) * | 2005-01-25 | 2006-07-27 | Takashi Ono | Method of dividing wafer |
| WO2006112524A1 (en) * | 2005-04-19 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006108428A (en) * | 2004-10-06 | 2006-04-20 | Disco Abrasive Syst Ltd | Wafer dividing method |
| JP2006253402A (en) * | 2005-03-10 | 2006-09-21 | Nec Electronics Corp | Manufacturing method of semiconductor device |
| JP2006294913A (en) * | 2005-04-12 | 2006-10-26 | Disco Abrasive Syst Ltd | Cutting method of wafer |
-
2006
- 2006-12-26 JP JP2006349189A patent/JP2008159985A/en active Pending
-
2007
- 2007-12-26 TW TW96150218A patent/TW200830392A/en unknown
- 2007-12-26 WO PCT/JP2007/075368 patent/WO2008081968A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6465158B1 (en) * | 1999-10-26 | 2002-10-15 | Disco Corporation | Semiconductor wafer dividing method |
| WO2006048230A1 (en) * | 2004-11-01 | 2006-05-11 | Xsil Technology Limited | Increasing die strength by etching during or after dicing |
| US20060166465A1 (en) * | 2005-01-25 | 2006-07-27 | Takashi Ono | Method of dividing wafer |
| WO2006112524A1 (en) * | 2005-04-19 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips |
Cited By (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8962452B2 (en) | 2007-08-07 | 2015-02-24 | Semiconductor Components Industries, Llc | Semiconductor die singulation apparatus and method |
| US7985661B2 (en) | 2007-08-07 | 2011-07-26 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US7989319B2 (en) | 2007-08-07 | 2011-08-02 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US8012857B2 (en) | 2007-08-07 | 2011-09-06 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US8222120B2 (en) * | 2009-06-05 | 2012-07-17 | Sts Semiconductor & Telecommunications Co., Ltd. | Method of dicing wafer using plasma |
| US20100311223A1 (en) * | 2009-06-05 | 2010-12-09 | Chun Jung Hwan | Method Of Dicing Wafer Using Plasma |
| US9165833B2 (en) | 2010-01-18 | 2015-10-20 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
| US9275957B2 (en) | 2010-01-18 | 2016-03-01 | Semiconductor Components Industries, Llc | EM protected semiconductor die |
| US9299664B2 (en) | 2010-01-18 | 2016-03-29 | Semiconductor Components Industries, Llc | Method of forming an EM protected semiconductor die |
| US9437493B2 (en) | 2010-01-18 | 2016-09-06 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
| US8384231B2 (en) | 2010-01-18 | 2013-02-26 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
| US9136173B2 (en) | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
| US10014217B2 (en) | 2012-11-07 | 2018-07-03 | Semiconductor Components Industries, Llc | Method of singulating semiconductor wafer having a plurality of die and a back layer disposed along a major surface |
| US10770350B2 (en) | 2012-11-07 | 2020-09-08 | Semiconductor Components Industries, Llc | Method of separating a back layer on a singulated semiconductor wafer attached to carrier substrate |
| US10553491B2 (en) | 2012-11-07 | 2020-02-04 | Semiconductor Components Industries, Llc | Method of separating a back layer on a singulated semiconductor wafer attached to carrier substrates |
| US9484260B2 (en) | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
| US9564365B2 (en) | 2012-11-07 | 2017-02-07 | Semiconductor Components Industries, Llc | Method of singulating semiconductor wafer having back layer |
| US9773689B2 (en) | 2012-11-07 | 2017-09-26 | Semiconductor Components Industries, Llc | Semiconductor die singulation method using varied carrier substrate temperature |
| US10269642B2 (en) | 2012-11-07 | 2019-04-23 | Semiconductor Components Industries, Llc | Method of singulating semiconductor wafer having a plurality of die and a back layer disposed along a major surface |
| US9589844B2 (en) | 2014-03-21 | 2017-03-07 | Semiconductor Components Industries, Llc | Electronic die singulation method |
| US9917013B2 (en) | 2014-03-21 | 2018-03-13 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer |
| US10446446B2 (en) | 2014-03-21 | 2019-10-15 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
| US9418894B2 (en) | 2014-03-21 | 2016-08-16 | Semiconductor Components Industries, Llc | Electronic die singulation method |
| US10950503B2 (en) | 2014-03-21 | 2021-03-16 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
| US9847270B2 (en) | 2014-08-26 | 2017-12-19 | Semiconductor Components Industries, Llc | Method for insulating singulated electronic die |
| US9385041B2 (en) | 2014-08-26 | 2016-07-05 | Semiconductor Components Industries, Llc | Method for insulating singulated electronic die |
| US10366923B2 (en) | 2016-06-02 | 2019-07-30 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
| US10796961B2 (en) | 2016-06-02 | 2020-10-06 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
| US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
| US10854516B2 (en) | 2017-05-24 | 2020-12-01 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
| US10818551B2 (en) | 2019-01-09 | 2020-10-27 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
| US11651998B2 (en) | 2019-01-09 | 2023-05-16 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200830392A (en) | 2008-07-16 |
| JP2008159985A (en) | 2008-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2008081968A1 (en) | Manufacturing method of semiconductor chip | |
| TWI282118B (en) | Dividing method of semiconductor wafer | |
| US7767554B2 (en) | Method of manufacturing semicondictor chip | |
| US7906410B2 (en) | Method of manufacturing semiconductor chip using laser light and plasma dicing | |
| TWI427687B (en) | Wafer processing method | |
| JP2003257896A (en) | Method for dicing semiconductor wafer | |
| JP2001148358A (en) | Semiconductor wafer and deviding method thereof | |
| JP2008098228A (en) | Manufacturing method of semiconductor chip | |
| US10083867B2 (en) | Method of processing a wafer | |
| US20090186465A1 (en) | Wafer dividing method | |
| JP6987448B2 (en) | Manufacturing method for small diameter wafers | |
| KR20210033485A (en) | Substrate processing system and substrate processing method | |
| WO2020012986A1 (en) | Substrate processing system and substrate processing method | |
| JP2003209080A (en) | Semiconductor wafer protecting member and grinding method for semiconductor wafer | |
| US20050054274A1 (en) | Semiconductor wafer processing method and processing apparatus | |
| JP6731793B2 (en) | Wafer processing system | |
| TWI772493B (en) | Substrate processing system and substrate processing method | |
| WO2019151041A1 (en) | Substrate processing system, substrate processing method and computer storage medium | |
| TWI762698B (en) | Substrate processing method | |
| CN109979879B (en) | Semiconductor chip manufacturing method | |
| JP6796983B2 (en) | Mask forming method and wafer processing method | |
| TW201921545A (en) | Substrate processing system and substrate processing method | |
| JP7450426B2 (en) | Processing method of workpiece | |
| US11894271B2 (en) | Method of processing wafer | |
| JP7477325B2 (en) | Processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07860563 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 07860563 Country of ref document: EP Kind code of ref document: A1 |