WO2008091737A1 - Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors - Google Patents
Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors Download PDFInfo
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- WO2008091737A1 WO2008091737A1 PCT/US2008/050697 US2008050697W WO2008091737A1 WO 2008091737 A1 WO2008091737 A1 WO 2008091737A1 US 2008050697 W US2008050697 W US 2008050697W WO 2008091737 A1 WO2008091737 A1 WO 2008091737A1
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- Prior art keywords
- oxide layer
- region
- transistor
- forming
- layer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 59
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 111
- 229910052757 nitrogen Inorganic materials 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 42
- 239000002159 nanocrystal Substances 0.000 claims description 41
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000002955 isolation Methods 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 11
- 230000008901 benefit Effects 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000012010 growth Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000002829 nitrogen Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Definitions
- the present invention relates generally to methods of forming semiconductor devices, and more particularly to semiconductor processes for forming nanoclusters or silicon dots.
- NVM non-volatile memory
- the nanocrystals that are deposited need to be preserved during subsequent processing.
- further processing required for various transistor types creates difficulties with preserving the nanocrystals.
- the thinnest gate dielectrics are for the logic transistors that are normally for the fastest speeds.
- Another thickness is for the transistors used as the inputs and outputs of voltage signals to and from the integrated circuit. The largest thickness is for the high voltage transistors that are used for the highest voltages in the particular integrated circuit such as for programming and erasing the NVM transistors.
- FIG. 1 is a cross section of a semiconductor device according to an embodiment of the invention.
- FIG. 2 is a cross section of the semiconductor device of FIG. 1 after subsequent processing
- FIG. 3 is a cross section of the semiconductor device of FIG. 2 after subsequent processing
- FIG. 4 is a cross section of the semiconductor device of FIG. 3 after subsequent processing
- FIG. 5 is a cross section of the semiconductor device of FIG. 4 after subsequent processing
- FIG. 6 is a cross section of the semiconductor device of FIG. 5 after subsequent processing
- FIG. 7 is a cross section of the semiconductor device of FIG. 6 after subsequent processing
- FIG. 8 is a cross section of the semiconductor device of FIG. 7 after subsequent processing
- FIG. 9 is a cross section of the semiconductor device of FIG. 8 after subsequent processing
- FIG. 10 is a cross section of the semiconductor device of FIG. 9 after subsequent processing
- FIG. 11 is a cross section of the semiconductor device of FIG. 10 after subsequent processing
- FIG. 12 is a cross section of the semiconductor device of FIG. 11 after subsequent processing.
- a semiconductor device has at least three different types of transistors one of which is an NVM transistor that uses nanocrystals for charge storage.
- One of the transistor types is a high voltage transistor that has a relatively thick gate dielectric.
- This thick gate dielectric has a very thin nitrogen-rich oxide layer, preferably formed using decoupled plasma nithdation, that is sufficiently uniform to cover the thick gate dielectric.
- This nitrogen-rich oxide layer has minimal impact on the electrical characteristics of the gate dielectric because it is very thin but provides a good etch stop because it has substantially the etch characteristics of nitride and is uniform. Also because it is nitrogen-rich oxide it suffers minimal damage during subsequent formation of the gate dielectric of the NVM transistor.
- a gate dielectric, thinner than the gate dielectric of the high voltage transistor, of a regular transistor is formed after the gate dielectric of the NVM transistor. This thinner gate dielectric causes less problem with degradation of the nanocrystals than would the process for forming the gate dielectric of the high voltage transistor. This is better understood with reference to the drawings and the following description.
- FIG. 1 Shown in FIG. 1 is a semiconductor device 10 comprising a semiconductor substrate 12, an oxide layer 18 on substrate 12, a region 14 in substrate 12, a region 16 in substrate 12, and an isolation region 17 surrounding a portion of substrate 12.
- Substrate 12 is preferably silicon but could be another semiconductor material or combination of materials such as silicon germanium (SiGe).
- Region 14 is a well region for forming high voltage transistors.
- Region 16 is a well region for forming transistors used in providing inputs and outputs (I/O transistors) of semiconductor device 10.
- Oxide layer 18 is the principal portion of a gate dielectric for high voltage transistors formed in region 14.
- Oxide is a preferred material for gate dielectrics but another gate dielectric material that has high selectivity to an etch chemistry that is used to etch oxide and nanocrystals can be used.
- Region 14 is preferably doped for optimizing the high voltage transistors.
- Region 16 is doped for optimizing the I/O transistors.
- Isolation region 17 is of an oxide trench penetrating into substrate 12. The portion of substrate 12 surrounded by isolation region 17 is for forming non-volatile memory (NVM) transistors.
- Oxide layer 18 is preferably about 150 Angstroms thick. The thickness chosen is related to how high the voltage is that will be used by the high voltage transistors.
- Regions 14 and 16 are preferably about 3 to 5 thousand Angstroms deep. This depth may vary even further.
- Isolation 17 is about 2 to 4 thousand Angstroms in depth. Typically the isolation need not be as deep as the well, but there may be instances where isolation is as deep as the well.
- the lateral dimension of regions 14 and 16 and the distance across region 17 can vary greatly depending upon the number of transistors and the sizes of those transistors that are to be formed in those locations.
- a well may contain an entire memory array or just one transistor.
- regions 14 and 16 preferably have isolation regions similar to isolation 17 surrounding them.
- FIG. 2 Shown in FIG. 2 is semiconductor device 10 after performing decoupled plasma nitridation (DPN) on oxide layer 18 to form a nitrogen-rich oxide layer 20 on oxide layer 18.
- This nitrogen-rich oxide layer is preferably very thin, no more than 10 Angstroms, be sufficiently uniform to completely cover oxide layer 18, and have a nitrogen concentration not more than 10 atomic percent.
- DPN is capable of achieving this uniformity while achieving a thickness less than 10 Angstroms.
- Further typical nitride deposition processes are not capable of forming such a thin layer or of having the desired low concentration of nitrogen.
- Nitrogen-rich oxide layer 20 although not stoichiometric silicon nitride, has many of the characteristics of nitride. In particular, it has high selectivity to certain etchants that are used for etching oxide. For example, hydrofluoric acid etches oxide very much faster than nitrogen-rich oxide such as layer 20.
- An effective DPN process or achieving this balance is to expose the wafer to a remote nitrogen plasma with plasma power between 200W and 600W, nitrogen partial pressure between 1 mTorr and 50mTorr and wafer temperature between 25C and 300C.
- FIG. 3 Shown in FIG. 3 is semiconductor device 10 after performing a patterned implant inside isolation 17. The result is a region 22 that is a well that is doped for the purpose of forming NVM transistors.
- FIG. 4 Shown in FIG. 4 is semiconductor device 10 after performing a patterned etch of nitrogen-rich oxide layer 20 and oxide layer 18 over region 22. The etch is aligned to isolation 17 so alignment is easily achieved.
- FIG. 5 Shown in FIG. 5 is semiconductor device 10 after forming a gate dielectric 24 on region 22 by growing oxide and forming a charge storage layer comprised of a plurality of nanocrystals 26 on gate dielectric 24 and over nitrogen-rich oxide layer 20 and an oxide layer 30 over and around plurality of nanocrystals 26.
- Oxide layer 30 is a deposited oxide, preferably what is commonly called high temperature oxide (HTO). Oxide layer 30 is about 150 Angstroms thick.
- Nanocrystal 28 is a nanocrystal of plurality of nanocrystals 26 that is over region 22 and on gate dielectric 24. Because oxide layer 30 is deposited, there is not very much free oxygen to react with nanocrystals 26 during the deposition of oxide layer 30.
- FIG. 6 Shown in FIG. 6 is semiconductor device 10 after etching the charge storage layer by etching oxide layer 30 and nanocrystals 26 to leave oxide layer 30 and nanocrystals 26 over gate dielectric 24.
- This etch is preferably a wet etch of hydrofluoric acid. This is very effective for etching oxide and highly selective to nitride. Thus, the etch removes oxide layer 30 and nanocrystals 26 and except over region 22 which is masked off during this patterned etch. Nitrogen-rich oxide layer 20 thus protects oxide layer 18 over region 14. If nitrogen-rich oxide layer 20 were not present, the etchant that removes oxide layer 30 would also necessarily etch into layer 18 which is oxide.
- FIG. 7 Shown in FIG. 7 is semiconductor device 10 after performing a patterned etch over region 16 to expose region 16.
- Gate dielectric 32 is preferably about 50 Angstroms thick.
- Region 34 functions as a well for forming logic transistors. These transistors are for the fast logic circuits of an integrated circuit having thinner gate dielectrics than the I/O transistors have. Region 34 preferably has isolation, not shown, similar to isolation 17 around it.
- FIG. 10 Shown in FIG. 10 is semiconductor device 10 after performing a patterned etch over region 34 to expose region 34.
- Gate dielectric 36 is preferably about 20 Angstroms thick.
- transistor 38 Shown in FIG.12 is semiconductor device 10 after forming a transistor 38, which is a high voltage transistor, over and in region 14; a transistor 40, which is an NVM transistor, over and in region 22; transistor 42, which is an I/O transistor, over and in region 16; and a transistor 44, which is a logic transistor, over an in region 34.
- the high voltage transistor has oxide layer 18 and nitrogen-rich oxide layer 20 as its gate dielectric.
- the NVM transistor has a gate dielectric of oxide layer 24 and a storage layer of oxide layer 30 over and around nanocrystals such as nanocrystal 28.
- the I/O transistor has oxide layer 32 as its gate dielectric.
- the logic transistor has oxide layer 36 as its gate dielectric.
- the nitrogen-rich oxide layer 20 can be made both thin so as to have minimal affect on transistor characteristics and sufficiently uniform to protect the gate dielectric.
- the formation of the NVM gate dielectric after formation of the thick grown gate dielectric of the high voltage transistor avoids the nanocrystals and NVM gate dielectric being subjected to oxygen during that relatively long oxide growth at high temperature.
- the shorter oxide growths for the I/O and logic transistors are performed after the removal of the nanocrystals so there is reduced negative impact by the oxide growth on the NVM gate dielectric and nanocrystals and the gate dielectrics for the I/O and logic transistors are not subjected to the etch that removes the charge storage layer that includes the nanocrystals.
- a semiconductor device is made on a semiconductor substrate.
- a first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate.
- a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate.
- a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.
- the method may form nanocrystals over the semiconductor substrate. Further the method may include forming a fourth insulating layer over the first insulating layer prior to the step of forming the second insulating layer and removing the nanocrystals over the first region and the third region prior to the step of forming the third insulating layer.
- the method may include removing the first and fourth insulating layer from over the second region prior to the step of forming the second insulating layer. Further the method include removing the first and fourth insulating layer from over the third region after the step of removing the first and fourth layer from over the second region and prior to the step of forming the third insulating layer. As an alternative the method may further be characterized by the step of forming the fourth insulating layer comprising performing a step of decoupled plasma nitridation on the first layer. In addition the method may be further characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer comprising nitrogen- rich oxide.
- the method may be characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer not exceeding 10 Angstroms in thickness.
- the method may be further characterized by the step of forming the fourth insulating layer being further characterized by the fourth insulating layer having a nitrogen concentration not exceeding 10 atomic percent.
- the method may be further characterized by the step of removing the nanocrystals comprising performing a wet etch using hydrofluoric acid.
- the method may be further characterized by the step of forming the first insulating layer comprising growing oxide on the semiconductor substrate.
- the method may further comprise forming a fifth insulating layer, after the step of forming the second insulating layer, on the semiconductor substrate for use as a gate dielectric for an I/O transistor.
- a method of making a semiconductor device on a semiconductor substrate A first oxide layer is grown on the semiconductor substrate. Plasma nithdation is performed on the first oxide layer to form a nitrogen- rich oxide layer on the first oxide layer. The first oxide layer and the nitrogen-rich layer are selectively removed to leave the first oxide layer and the nitrogen-rich oxide layer over a first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over a second region of the substrate. A second oxide layer is grown over the second region.
- a nanocrystal layer is formed over the semiconductor substrate after the step of growing the second oxide layer.
- the nanocrystal layer is removed from over the first region and a third region of the substrate.
- selectively removing the first oxide layer and the nitrogen-rich oxide layer to leave the first oxide layer and the nitrogen-rich oxide layer over the first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over the third region of the substrate.
- a third oxide layer is grown over the third region.
- a first transistor of a first type is formed in and over the first region using the first oxide layer and nitrogen- rich oxide layer as a gate dielectric of the first transistor.
- a second transistor of a second type is formed in and over the second region using the second oxide layer as a gate dielectric of the second transistor.
- a third transistor of a third type is formed in and over the third region using the third oxide layer as a gate dielectric of the third transistor.
- the method may be further characterized by the step of growing the first oxide layer being further characterized by the first oxide layer having a first thickness, the step of growing the second oxide layer being further characterized by the second oxide layer having a second thickness less than the first thickness, and the step of growing the third oxide layer being further characterized by the third oxide layer having a third thickness less than the second thickness.
- the method may be further characterized by the step of forming the first transistor being further characterized by the first transistor being a high voltage transistor, the step of forming the second transistor is further characterized by the second transistor being a non-volatile memory transistor, and the step of forming the third transistor is further characterized by the third transistor being a logic transistor.
- the method may be further characterized by the step of removing the nanocrystal layer further comprising removing the nanocrystal layer from over a fourth region of the substrate and the method may further comprise selectively removing, after the step of removing the nanocrystals, the first oxide layer and the nitrogen-rich oxide layer to leave the first oxide layer and the nitrogen-rich oxide layer over the first region of the substrate and remove the first oxide layer and the nitrogen-rich oxide layer from over the fourth region of the substrate, growing a fourth oxide layer over the fourth region, and forming a fourth transistor of a fourth type on and over the fourth region using the fourth oxide layer as a gate dielectric of the fourth transistor.
- the method may be further characterized by the step of performing decoupled plasma nitridation being further characterized by the nitrogen-rich oxide layer being not more than 10 Angstroms in thickness. Also the method may be further characterized by the step of performing decoupled plasma nitridation being further characterized by the nitrogen-rich oxide layer having a nitrogen concentration not exceeding 10 atomic percent
- a semiconductor device comprises a high voltage transistor, a non-volatile memory transistor; an a logic transistor.
- the high voltage transistor has a gate dielectric comprising an oxide layer and a nitrogen-rich oxide layer, wherein the nitrogen-rich oxide layer is not more than 10 Angstroms thick and has a concentration of nitrogen not in excess of 10 atomic percent; wherein the oxide layer has a first thickness.
- the non-volatile memory transistor has a gate dielectric of a second thickness less than the first thickness.
- the logic transistor has a gate dielectric of a third thickness less than the second thickness.
- the semiconductor device may further comprise an I/O transistor having a gate dielectric of a fourth thickness greater than the third thickness and less than the first thickness.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08727504.6A EP2108189B1 (en) | 2007-01-26 | 2008-01-10 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors |
JP2009547344A JP5517628B2 (en) | 2007-01-26 | 2008-01-10 | Method of manufacturing a semiconductor device comprising a high voltage transistor, a non-volatile memory transistor, and a logic transistor |
KR1020097015607A KR101364214B1 (en) | 2007-01-26 | 2008-01-10 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors |
CN2008800012618A CN101569006B (en) | 2007-01-26 | 2008-01-10 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US11/627,725 | 2007-01-26 | ||
US11/627,725 US7816211B2 (en) | 2007-01-26 | 2007-01-26 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors |
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WO2008091737A1 true WO2008091737A1 (en) | 2008-07-31 |
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PCT/US2008/050697 WO2008091737A1 (en) | 2007-01-26 | 2008-01-10 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors |
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US (1) | US7816211B2 (en) |
EP (1) | EP2108189B1 (en) |
JP (1) | JP5517628B2 (en) |
KR (1) | KR101364214B1 (en) |
CN (1) | CN101569006B (en) |
TW (1) | TWI442480B (en) |
WO (1) | WO2008091737A1 (en) |
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US9072153B2 (en) | 2010-03-29 | 2015-06-30 | Gigaphoton Inc. | Extreme ultraviolet light generation system utilizing a pre-pulse to create a diffused dome shaped target |
KR20120064482A (en) | 2010-12-09 | 2012-06-19 | 삼성전자주식회사 | Non-volatile memory device with high speed operation and low power consumption |
TWI691019B (en) * | 2019-03-19 | 2020-04-11 | 華邦電子股份有限公司 | Flash memory device and method for manufacturing the same |
CN111199919B (en) * | 2019-12-20 | 2021-05-14 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device formed by same |
JP2022043897A (en) | 2020-09-04 | 2022-03-16 | キオクシア株式会社 | Semiconductor storage device |
TWI812974B (en) * | 2020-09-04 | 2023-08-21 | 日商鎧俠股份有限公司 | semiconductor memory device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050287729A1 (en) * | 2004-06-25 | 2005-12-29 | Steimle Robert F | Method of forming a nanocluster charge storage device |
KR20060057958A (en) * | 2004-11-24 | 2006-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
US20060160311A1 (en) | 2005-01-14 | 2006-07-20 | Rao Rajesh A | Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices |
US20060194438A1 (en) * | 2004-06-25 | 2006-08-31 | Rao Rajesh A | Method of forming a nanocluster charge storage device |
Family Cites Families (4)
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US7474002B2 (en) * | 2001-10-30 | 2009-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having dielectric film having aperture portion |
KR20030044394A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with dual gate dielectric layer |
US7176094B2 (en) | 2002-03-06 | 2007-02-13 | Chartered Semiconductor Manufacturing Ltd. | Ultra-thin gate oxide through post decoupled plasma nitridation anneal |
US6958265B2 (en) | 2003-09-16 | 2005-10-25 | Freescale Semiconductor, Inc. | Semiconductor device with nanoclusters |
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US20050287729A1 (en) * | 2004-06-25 | 2005-12-29 | Steimle Robert F | Method of forming a nanocluster charge storage device |
US20060194438A1 (en) * | 2004-06-25 | 2006-08-31 | Rao Rajesh A | Method of forming a nanocluster charge storage device |
KR20060057958A (en) * | 2004-11-24 | 2006-05-29 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
US20060160311A1 (en) | 2005-01-14 | 2006-07-20 | Rao Rajesh A | Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices |
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See also references of EP2108189A4 |
Also Published As
Publication number | Publication date |
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TWI442480B (en) | 2014-06-21 |
EP2108189A1 (en) | 2009-10-14 |
US20080179658A1 (en) | 2008-07-31 |
EP2108189A4 (en) | 2011-03-30 |
JP5517628B2 (en) | 2014-06-11 |
KR20090106550A (en) | 2009-10-09 |
TW200847298A (en) | 2008-12-01 |
US7816211B2 (en) | 2010-10-19 |
EP2108189B1 (en) | 2018-06-27 |
CN101569006B (en) | 2011-03-09 |
CN101569006A (en) | 2009-10-28 |
JP2010517306A (en) | 2010-05-20 |
KR101364214B1 (en) | 2014-02-21 |
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