WO2008129424A3 - Ultra-thin stacked chios packaging - Google Patents

Ultra-thin stacked chios packaging Download PDF

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Publication number
WO2008129424A3
WO2008129424A3 PCT/IB2008/001626 IB2008001626W WO2008129424A3 WO 2008129424 A3 WO2008129424 A3 WO 2008129424A3 IB 2008001626 W IB2008001626 W IB 2008001626W WO 2008129424 A3 WO2008129424 A3 WO 2008129424A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
stable base
packaging
chios
ultra
Prior art date
Application number
PCT/IB2008/001626
Other languages
French (fr)
Other versions
WO2008129424A2 (en
Inventor
John Trezza
Original Assignee
Cufer Asset Ltd Llc
John Trezza
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cufer Asset Ltd Llc, John Trezza filed Critical Cufer Asset Ltd Llc
Priority to KR1020127002724A priority Critical patent/KR101245928B1/en
Priority to EP08762937A priority patent/EP2361439A2/en
Priority to KR1020097023473A priority patent/KR101157726B1/en
Priority to CN2008800129833A priority patent/CN101663747B/en
Priority to JP2010504906A priority patent/JP4970593B2/en
Publication of WO2008129424A2 publication Critical patent/WO2008129424A2/en
Publication of WO2008129424A3 publication Critical patent/WO2008129424A3/en

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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

A packaging method involves attaching a first chip (1002) to a stable base' (600), forming contact pads (902) at locations on the stable base, applying a planarizing medium (1102) onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths (1302, 1304) on the medium, attaching a second chip (1402) to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material (1502) on top of the planarizing medium.
PCT/IB2008/001626 2007-04-23 2008-06-20 Ultra-thin stacked chios packaging WO2008129424A2 (en)

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KR1020127002724A KR101245928B1 (en) 2007-04-23 2008-06-20 Ultra-thin stacked chips packaging
EP08762937A EP2361439A2 (en) 2007-04-23 2008-06-20 Ultra-thin chip packaging
KR1020097023473A KR101157726B1 (en) 2007-04-23 2008-06-20 Ultra-thin stacked chips packaging
CN2008800129833A CN101663747B (en) 2007-04-23 2008-06-20 Ultra-thin chip packaging
JP2010504906A JP4970593B2 (en) 2007-04-23 2008-06-20 Ultra-thin chip packaging

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US11/738,817 2007-04-23
US11/738,817 US7960210B2 (en) 2007-04-23 2007-04-23 Ultra-thin chip packaging

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KR101157726B1 (en) 2012-06-21
US20080258284A1 (en) 2008-10-23
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KR20100020939A (en) 2010-02-23
JP4970593B2 (en) 2012-07-11

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