WO2008130541A3 - Semiconductor light emitting device packages and methods - Google Patents

Semiconductor light emitting device packages and methods Download PDF

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Publication number
WO2008130541A3
WO2008130541A3 PCT/US2008/004849 US2008004849W WO2008130541A3 WO 2008130541 A3 WO2008130541 A3 WO 2008130541A3 US 2008004849 W US2008004849 W US 2008004849W WO 2008130541 A3 WO2008130541 A3 WO 2008130541A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
bond pad
light emitting
methods
emitting device
Prior art date
Application number
PCT/US2008/004849
Other languages
French (fr)
Other versions
WO2008130541A2 (en
Inventor
Ban P Loh
Nathaniel O Cannon
Norbert Hiller
John Edmond
Mitch Jackson
Nicholas W Mendendorp
Original Assignee
Cree Inc
Ban P Loh
Nathaniel O Cannon
Norbert Hiller
John Edmond
Mitch Jackson
Mendendorp Jr Nicholas W
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc, Ban P Loh, Nathaniel O Cannon, Norbert Hiller, John Edmond, Mitch Jackson, Mendendorp Jr Nicholas W filed Critical Cree Inc
Priority to EP08742905.6A priority Critical patent/EP2147468B1/en
Priority to JP2010504064A priority patent/JP5512509B2/en
Priority to CN2008800208799A priority patent/CN101689590B/en
Publication of WO2008130541A2 publication Critical patent/WO2008130541A2/en
Publication of WO2008130541A3 publication Critical patent/WO2008130541A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting
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    • H01ELECTRIC ELEMENTS
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.
PCT/US2008/004849 2007-04-18 2008-04-15 Semiconductor light emitting device packages and methods WO2008130541A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP08742905.6A EP2147468B1 (en) 2007-04-18 2008-04-15 Semiconductor light emitting device packages and methods
JP2010504064A JP5512509B2 (en) 2007-04-18 2008-04-15 Semiconductor light emitting device package and method
CN2008800208799A CN101689590B (en) 2007-04-18 2008-04-15 Semiconductor light emitting device packages and methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/788,001 US7964888B2 (en) 2007-04-18 2007-04-18 Semiconductor light emitting device packages and methods
US11/788,001 2007-04-18

Publications (2)

Publication Number Publication Date
WO2008130541A2 WO2008130541A2 (en) 2008-10-30
WO2008130541A3 true WO2008130541A3 (en) 2008-12-18

Family

ID=39639394

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/004849 WO2008130541A2 (en) 2007-04-18 2008-04-15 Semiconductor light emitting device packages and methods

Country Status (6)

Country Link
US (3) US7964888B2 (en)
EP (1) EP2147468B1 (en)
JP (1) JP5512509B2 (en)
CN (2) CN101689590B (en)
TW (2) TW201507208A (en)
WO (1) WO2008130541A2 (en)

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US20080258168A1 (en) 2008-10-23

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