WO2008143937A3 - Asymmetric transmit/receive data rate circuit interface - Google Patents

Asymmetric transmit/receive data rate circuit interface Download PDF

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Publication number
WO2008143937A3
WO2008143937A3 PCT/US2008/006238 US2008006238W WO2008143937A3 WO 2008143937 A3 WO2008143937 A3 WO 2008143937A3 US 2008006238 W US2008006238 W US 2008006238W WO 2008143937 A3 WO2008143937 A3 WO 2008143937A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
circuit
rate
data rate
receive data
Prior art date
Application number
PCT/US2008/006238
Other languages
French (fr)
Other versions
WO2008143937A2 (en
Inventor
Brian S Leibowitz
Jared Levan Zerbe
Original Assignee
Rambus Inc
Brian S Leibowitz
Jared Levan Zerbe
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Brian S Leibowitz, Jared Levan Zerbe filed Critical Rambus Inc
Publication of WO2008143937A2 publication Critical patent/WO2008143937A2/en
Publication of WO2008143937A3 publication Critical patent/WO2008143937A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Dram (AREA)

Abstract

A system implements asymmetric data transfer between circuit blocks. The asymmetric data rate is between receivers and transmitters of different integrated circuits across a set of channels. In an embodiment, a first circuit or memory controller includes a transmission circuit to transmit data at a first data, rate over a data channel 8 to a reception circuit of a second circuit or a memory 6. The first circuit or memory controller also includes a reception circuit to receive data at a second data rate, different from the first data rate, over a data channel from a transmission circuit of the second circuit or memory. Thus, data is transferred at a greater rate per channel in one direction between circuits compared to the other direction. For example, a data transfer rate for either a read data operation or a write data operation exceeds the transfer rate of the other operation.
PCT/US2008/006238 2007-05-17 2008-05-15 Asymmetric transmit/receive data rate circuit interface WO2008143937A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93052407P 2007-05-17 2007-05-17
US60/930,524 2007-05-17

Publications (2)

Publication Number Publication Date
WO2008143937A2 WO2008143937A2 (en) 2008-11-27
WO2008143937A3 true WO2008143937A3 (en) 2009-04-09

Family

ID=39708670

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/006238 WO2008143937A2 (en) 2007-05-17 2008-05-15 Asymmetric transmit/receive data rate circuit interface

Country Status (1)

Country Link
WO (1) WO2008143937A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180095699A1 (en) * 2016-10-01 2018-04-05 National Tsing Hua University Memory system, memory device thereof, and method for writing to and reading from memory device thereof
US10446198B2 (en) 2017-10-02 2019-10-15 Micron Technology, Inc. Multiple concurrent modulation schemes in a memory system
US10355893B2 (en) 2017-10-02 2019-07-16 Micron Technology, Inc. Multiplexing distinct signals on a single pin of a memory device
US11403241B2 (en) 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
US10725913B2 (en) 2017-10-02 2020-07-28 Micron Technology, Inc. Variable modulation scheme for memory device access or operation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075393A (en) * 1997-07-22 2000-06-13 Fujitsu Limited Clock synchronous semiconductor device system and semiconductor devices used with the same
US20020023191A1 (en) * 2000-08-21 2002-02-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and memory system using the same
US20030021164A1 (en) * 2001-03-09 2003-01-30 Samsung Electronics Co., Ltd. Semiconductor memory device having different data rates in read operation and write operation
US6542555B2 (en) * 1997-06-20 2003-04-01 Massachusetts Institute Of Technology Digital transmitter with equalization
US20060041704A1 (en) * 2004-08-23 2006-02-23 Choi Joo S Dual port memory with asymmetric inputs and outputs, device, system and method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542555B2 (en) * 1997-06-20 2003-04-01 Massachusetts Institute Of Technology Digital transmitter with equalization
US6075393A (en) * 1997-07-22 2000-06-13 Fujitsu Limited Clock synchronous semiconductor device system and semiconductor devices used with the same
US20020023191A1 (en) * 2000-08-21 2002-02-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and memory system using the same
US20030021164A1 (en) * 2001-03-09 2003-01-30 Samsung Electronics Co., Ltd. Semiconductor memory device having different data rates in read operation and write operation
US20060041704A1 (en) * 2004-08-23 2006-02-23 Choi Joo S Dual port memory with asymmetric inputs and outputs, device, system and method

Also Published As

Publication number Publication date
WO2008143937A2 (en) 2008-11-27

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