WO2009037691A2 - Programming orders for reducing distortion in arrays of multi-level analog memory cells - Google Patents

Programming orders for reducing distortion in arrays of multi-level analog memory cells Download PDF

Info

Publication number
WO2009037691A2
WO2009037691A2 PCT/IL2008/001188 IL2008001188W WO2009037691A2 WO 2009037691 A2 WO2009037691 A2 WO 2009037691A2 IL 2008001188 W IL2008001188 W IL 2008001188W WO 2009037691 A2 WO2009037691 A2 WO 2009037691A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory cells
programming
order
programmed
cells
Prior art date
Application number
PCT/IL2008/001188
Other languages
French (fr)
Other versions
WO2009037691A3 (en
Inventor
Ofir Shalvi
Eyal Gurgi
Original Assignee
Anobit Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anobit Technologies filed Critical Anobit Technologies
Publication of WO2009037691A2 publication Critical patent/WO2009037691A2/en
Publication of WO2009037691A3 publication Critical patent/WO2009037691A3/en
Priority to US12/721,585 priority Critical patent/US8174905B2/en
Priority to US13/412,780 priority patent/US8300478B2/en
Priority to US13/412,731 priority patent/US8437185B2/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5648Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

  • PROGRAMMING ORDERS FOR REDUCING DISTORTION IN ARRAYS OF MULTILEVEL ANALOG MEMORY CELLS
  • the present invention relates generally to memory devices, and particularly to methods and systems for programming arrays of multi-level analog memory cells.
  • Flash memories use arrays of analog memory cells for storing data.
  • Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage.
  • the storage value represents the information stored in the cell.
  • each analog memory cell holds a certain amount of electrical charge.
  • the range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values.
  • Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
  • Some memory devices which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states.
  • SLC Single-Level Cell
  • Multi-Level Cell (MLC) devices store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states. Flash memory devices are described, for example, by Bez et al., in "Introduction to
  • Multi-level Flash Memory Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference.
  • Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, New York, pages 169-172, which is incorporated herein by reference.
  • the paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
  • NROM Nitride Read Only Memory
  • SSDM Solid State Devices and Materials
  • FG Floating Gate
  • FRAM Ferroelectric RAM
  • MRAM magnetic RAM
  • CTF Charge Trap Flash
  • PRAM phase change RAM
  • FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in "Future Memory
  • MIEL Microelectronics
  • PCT International Publication WO 2007/146010 whose disclosure is incorporated herein by reference, describes a method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The lower page of predetermined memory cells is programmed with first predetermined data, and the upper page is programmed with second predetermined data. The upper page of the predetermined memory cells is re-programmed with the second predetermined data.
  • U.S. Patent Application Publication 2003/0002348 whose disclosure is incorporated herein by reference, describes a non- volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element.
  • a flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates.
  • the memory is operated to minimize the effect of charge coupled between adjacent floating gates by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states.
  • the set is programmed beginning with a word line WLn adjacent to a select gate line for the set.
  • the next word line WLn+ 1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+ 1 is programmed.
  • WLn+ 1 is then programmed.
  • Programming continues according to the sequence ⁇ WLn+4, WLn+3, WLn+6, WLn+5,... ⁇ until all but the last word line for the set have been programmed. The last word line is then programmed.
  • the method includes programming i-valued data to three or more memory cells contiguously arranged along a first direction of the matrix before programming (i+l)-valued data to any of the three or more memory cells, wherein i is less than n, and wherein the three or more memory cells are programmed during three or more respectively distinct program periods, and after programming the i-valued data to the three or more memory cells, programming (i+l)-valued data to a particular memory cell among the three or more memory cells.
  • Embodiments of the present invention provide a method for data storage, including: predefining an order of programming a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, wherein the order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming level, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels; and storing data in the memory cells by programming the memory cells in accordance with the predefined order.
  • the given row is divided into at least first and second subsets of the memory cells for storing at least first and second memory pages.
  • the first subset includes odd-order memory cells of the row and the second subset includes even- order memory cells of the row.
  • the order alternates among the subsets when programming the memory cells in the given row. Further alternatively or additionally, the order specifies that the memory cells in the first subset are programmed to assume the programming levels other than the highest levels only after all the memory cells in the second subset are programmed to assume the programming levels other than the highest levels.
  • the method when the memory cells in the given rows are subject to cross-coupling interference from the memory cells in the neighboring rows, the method includes reading the data stored in the neighboring rows and processing the read data so as to cancel the cross-coupling interference.
  • a method for data storage including: defining different first and second orders of programming of a plurality of analog memory cells; storing first data by programming the analog memory cells in accordance with the first order; evaluating a predefined switching condition with respect to the memory cells; and responsively to meeting the switching condition, switching from the first order to the second order, and storing second data by programming the analog memory cells in accordance with the second order.
  • the switching condition may depend on a number of programming and erasure cycles that were applied to the memory cells, on a time that elapsed since a last erasure operation that was applied to the memory cells, on a time that elapsed since a last programming operation that was applied to the memory cells, on an expected time discontinuity in programming the memory cells, on a level of distortion in the memory cells, or on an operating condition of the memory cells.
  • the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and one of the first and second orders specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest level.
  • each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and the second order specifies that all the memory cells in a given row are programmed to contain at least a certain number of the programming levels before any of the memory cells in the given row are programmed to contain a full number of the programming levels.
  • apparatus for data storage including: a memory, which includes a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell; and a control module, which is coupled to predefine a programming order specifying that, for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming level, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels, and to store data in the memory cells by programming the memory cells in accordance with the predefined programming order.
  • apparatus for data storage including: a memory, which includes a plurality of analog memory cells; and a control module, which is coupled to define different first and second orders of programming the analog memory cells, to store first data by programming the analog memory cells in accordance with the first order, to evaluate a predefined switching condition with respect to the memory cells and, responsively to meeting the switching condition, to switch from the first order to the second order and to store second data by programming the analog memory cells in accordance with the second order.
  • Fig. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention
  • Fig. 2 is a graph showing threshold voltage distributions in multi-level analog memory cells, in accordance with an embodiment of the present invention
  • Fig. 3 is a diagram that schematically illustrates an array of multi-level analog memory cells, in accordance with an embodiment of the present invention.
  • Figs. 4 and 5 are flow charts that schematically illustrate methods for programming arrays of multi-level analog memory cells, in accordance with embodiments of the present invention.
  • Arrays of analog memory cells often suffer from distortion effects, such as cross- coupling interference and programming disturb.
  • the order in which the cells are programmed affects the level of distortion in the cells. For example, when the cells are programmed using a closed-loop Program and Verify (P&V) process, distortion that is already present when the cells are programmed is inherently compensated for. Thus, if cells that potentially cause distortion to a certain target cell are programmed before the target cell, the distortion in the target cell will be compensated for by the P&V process.
  • P&V Program and Verify
  • the level of program disturb in a given row of cells may depend on the order in which the rows are programmed in the array.
  • the level of program disturb in the N row may be higher if the N row is programmed later than both the (N+ 1) row and the (N-I) row, in comparison to programming the N row when either the (N+ 1) row or the (N-I) row is still erased.
  • the program disturb in a given cell depends on its bit line voltage.
  • Embodiments of the present invention that are described hereinbelow provide improved methods and systems for programming arrays of multi-level analog memory cells.
  • a control module accepts data for storage and stores the data in an array of multi-level analog memory cells, in accordance with a predefined programming order.
  • the array comprises multiple memory cells that are arranged in rows and columns. The cells along each row are connected to a common word line and the cells along each column are connected to a common bit line.
  • the programming orders used by the control module provide an improved trade-off of cross-coupling interference and program disturb. These programming orders are based on two principles:
  • the array is programmed in a monotonic (increasing or decreasing) order of word lines, so that all bits in a given word line are programmed before continuing to the next (higher or lower) word line.
  • all bits other than the bits mapped to the programming level having the highest storage values are programmed first, in all the cells in the word line.
  • the bits associated with the highest storage values are programmed only after programming of the other bits is completed for all cells in the word line.
  • Principle (1) ensures that when a given word line is programmed, the cells in neighboring word lines on at least one side of this word line will be in an erased state. As a result, program disturb effects are reduced.
  • Principle (2) reduces the cross-coupling interference among memory cells within a given word line. Since the bits associated with the highest analog values are programmed last, potentially-interfering cells in the word line are already partially-programmed when the potentially-interfered cells are programmed to their final values. As a result, the P&V process compensates for the majority of the cross-coupling interference within the word line.
  • a given word line stores multiple memory pages.
  • the memory device may store one page in the odd-order cells of the word line, and another page in the even-order cells.
  • programming typically alternates between the odd and even pages in the word line, until all but the pages associated with the highest analog values are programmed.
  • programming orders for four-level, eight-level and sixteen-level cells are described below.
  • control module changes the programming order during the life cycle of the memory array, in order to adapt to different conditions and circumstances.
  • the control module initially stores data in the array using a certain initial programming order.
  • the control module evaluates a predefined switching condition. If the condition is met, the control module switches to a different programming order. Different criteria and switching conditions are described further below.
  • SYSTEM DESCRIPTION Fig. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention.
  • System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules ("disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.
  • SSD Solid State Disks
  • System 20 comprises a memory device 24, which stores data in a memory cell array 28.
  • the memory cell array comprises multiple analog memory cells 32.
  • analog memory cell is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge.
  • Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells.
  • Memory cells 32 comprise Multi-Level Cells (MLC, also referred to as multi-bit cells), each storing multiple data bits.
  • MLC Multi-Level Cells
  • analog values or storage values The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values.
  • analog values or storage values Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.
  • System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels.
  • the programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value.
  • a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values to the cell.
  • Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to storage values and writes them into memory cells 32.
  • the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells.
  • the R/W unit typically (although not necessarily) programs the cells using an iterative Program and Verify (P&V) process, as is known in the art.
  • P&V Program and Verify
  • R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits.
  • Data is typically written to and read from the memory cells in groups that are referred to as pages.
  • Memory device 24 comprises one or more page buffers 38, which are used for caching data pages during data storage and retrieval.
  • MSP 40 Memory Signal Processor 40
  • MSP 40 comprises an interface 44 for communicating with memory device 24, and a signal processing unit 48, which processes the data that is written into and read from device 24.
  • unit 48 produces the storage values for storing in the memory cells and provides these values to R/W unit 36.
  • unit 48 provides the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device.
  • MSP 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device.
  • MSP 40, and in particular unit 48, may be implemented in hardware.
  • MSP 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.
  • Fig. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.
  • memory device 24 and MSP 40 are implemented as two separate Integrated Circuits (ICs).
  • the memory device and MSP may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC).
  • MCP Multi-Chip Package
  • SoC System on Chip
  • some or all of the MSP circuitry may reside on the same die on which the memory array is disposed.
  • some or all of the functionality of MSP 40 can be implemented in software and carried out by a processor or other element of the host system, or by a suitable memory controller.
  • a single MSP 40 may be connected to multiple memory devices 24.
  • the MSP may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device 24.
  • the MSP (or any other controller or processor that carries out some or all of the methods described herein) comprises a general-purpose processor, which is programmed in software to carry out the functions described herein.
  • the software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory.
  • Memory cells 32 of array 28 are typically arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively.
  • the array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Cells are typically erased in groups of word lines that are referred to as erasure blocks.
  • R/W unit 36 programs memory cells 32 using an iterative Program and Verify (P&V) process.
  • P&V Program and Verify
  • an entire memory page is written by applying a sequence of programming pulses to a group of memory cells that are mapped to this page.
  • the level of the programming pulses increases incrementally from pulse to pulse.
  • the storage values programmed in the cells are read (“verified”) after each pulse, and the iterations continue until the desired levels are reached.
  • Arrays of analog memory cells suffer from various types of distortion of interference.
  • floating-gate memory cells often suffer from cross-coupling interference from neighboring cells.
  • Cross-coupling interference causes a change in the storage value read from an interfered cell due to changes in the charge levels of one or more interfering cells.
  • Another distortion mechanism commonly referred to as program disturb or disturb noise, causes a change in the charge of a cell due to voltages applied to the cell when programming other cells in the array.
  • the level of distortion in an array of memory cells depends on the relative order in which the cells are programmed. For example, P&V processes are closed-loop processes, which inherently compensate for distortion that is present at the time the cells are being programmed.
  • the P&V process will inherently compensate for at least some of the distortion caused by the potentially-interfering cell.
  • the potentially-interfering cell is programmed later than the potentially-interfered cell (i.e., if the potentially-interfering cell is not programmed at the time the potentially-interfered cell is programmed)
  • the P&V process will not compensate for the distortion.
  • the P&V process applied to the potentially-interfered cell will compensate for only part of the distortion.
  • the level of program disturb in a given row of cells may depend on the order in which the rows are programmed in the array.
  • the level of program disturb in the N row may be higher if the N row is programmed later than both the (N+ 1) row and the (N-I) row, in comparison to programming the N row when either the (N+ 1)
  • Embodiments of the present invention provide improved methods and systems for programming arrays of multi-level analog memory cells. The methods and systems described herein program the cells in orders that reduce both cross-coupling interference and program disturb.
  • Fig. 2 is a graph showing threshold voltage distributions in a group of multi-level analog memory cells, in accordance with an embodiment of the present invention.
  • the cells comprise four-level cells, with each cell capable of storing two bits.
  • the first bit written to the cell is referred to as a Least Significant Bit (LSB) and the second bit written to the cell is referred to as a Most Significant Bit (MSB).
  • LSB and MSB are used, however, purely for the sake of clarity, and do not imply that some bits are more important than others. Any other convenient terminology for referring to individual bits in the cell can also be used.
  • the top graph in Fig. 2 shows the threshold voltage distribution of the cells when all the cells are erased, i.e., before any programming is performed. At this stage, all the cells assume a single erased level 56, in which the threshold voltages are statistically distributed around a certain nominal erased level.
  • the middle graph in Fig. 2 shows the threshold voltage distribution of the cells when only the LSBs are programmed.
  • cells that are to store an LSB value of "1" are not subjected to any programming, and remain at a level 58A similar to the erased level.
  • Cells that are to store an LSB value of "0" are programmed to assume a level 58B.
  • the bottom graph in Fig. 2 shows the threshold voltage distribution of the cells after both the LSBs and MSBs are programmed.
  • charge is added to the cell, causing the cell to assume a level 6OB.
  • the threshold voltage of a cell that was programmed with only the first bit is lower than the threshold voltage of the cell after programming both bits.
  • a group of cells in which only the first bits are programmed has, on average, lower storage values that a group of cells that is fully-programmed. In other words, cells that are partially-programmed have lower analog storage values than cells that are fully- programmed.
  • Fig. 2 refers to a particular programming scheme of a 2 bits/cell array.
  • the property according to which cells that are programmed with only a subset of the bits have lower storage values than cells that are fully-programmed is equally applicable to various other programming schemes and to memory cells storing higher numbers of bit.
  • embodiments that use 3 bits/cell memory cells storing an LSB, Central Significance Bit (CSB) and MSB are described further below.
  • a memory array typically comprises a large number of memory cells that are arranged in rows and columns.
  • the cells along each row are connected to a word line, and the cells along each column are connected to a bit line.
  • a page of data is typically written simultaneously to a group of cells along a word line.
  • each word line stores a single page.
  • different bits of a multi-level cell are mapped to different pages.
  • one page can be stored in the LSBs of the cells and another page can be stored in the MSBs.
  • a page stored in the LSBs of the cells is referred to as an LSB page, and a page stored in the MSBs is referred to as an MSB page for brevity.
  • some memory device configurations partition the cells along each word line into two or more groups, e.g., into odd-order and even-order cells, and store different pages in the different groups.
  • a row of 2 bits/cell memory cells may store four memory pages - one page in the LSBs of the odd-order cells, a second page in the MSBs of the odd-order cell, a third page in the LSBs of the even-order cells and a fourth page in the MSBs of the even-order cells.
  • Configurations that divide each word line into four groups or into any other number of groups, are also feasible.
  • the cells along each word line is partitioned into groups in an interleaved manner.
  • Fig. 3 is a diagram that schematically illustrates an array 64 of multi-level analog memory cells 66, in accordance with an exemplary embodiment of the present invention.
  • Cells 66 are connected by word lines 68 and bit lines 70.
  • cells 66 comprise 2 bits/cell memory cells, and each word line is divided into odd- and even-order cells. The odd- order cells are shaded in the figure.
  • each word line 68 stores four memory pages, referred to as LSB/ODD, LSB/EVEN, MSB/ODD and MSB/EVEN.
  • the array is programmed in a monotonic (increasing or decreasing) order of word lines, so that all pages (bits) in a given word line are programmed before continuing to the next (higher or lower) word line.
  • the lower-order pages are programmed first for all the cells in the word line.
  • the highest-significance bits are programmed only after programming of lower-significance bits is completed for all cells in the word line.
  • Principle (1) above ensures that when a given word line is programmed, the cells in neighboring word lines on at least one side of this word line will be in an erased state. As a result, program disturb effects are reduced.
  • Principle (2) above reduces the cross-coupling interference among memory cells within a given word line (also referred to as horizontal cross-coupling, because the interfering cells belong to the same word line as the interfered cell).
  • principle (2) above is extended, so as to ensure that the one or more highest programming levels are programmed only after the programming levels other than the highest levels are programmed, for all the cells in the given word line.
  • a given word line may store multiple pages, such as in odd-order and even- order cells.
  • programming typically alternates between the odd and even pages in the word line, until all but the highest programming levels (MSB pages) are programmed.
  • MSB pages highest programming levels
  • principle (2) above means that, within a given word line of an M-bit MLC device, the first M-I bits of all cells are programmed first. The M bits of the cells in the word line are programmed only after programming of the first M-I bits is completed.
  • the table defines an order for programming an array of 3 bits/cell memory cells.
  • the array has N word lines.
  • the cells in each word lines are partitioned into odd- and even-order cells, so that each word line stored six pages.
  • the word lines are programmed in a monotonically-increasing order starting from word line 0.
  • the order of programming is EVEN/LSB, ODD/LSB, EVEN/CSB, ODD/CSB, EVEN/MSB and finally ODD/MSB.
  • the word lines can be programmed in a monotonically- decreasing order.
  • the odd-order page in a given bit can be programmed before the corresponding even-order bit. Any other suitable variation to this order may be applied, while meeting principles (1) and (2) above.
  • the programming order is set and carried out within memory device 24.
  • R/W unit 36 comprises a control module that defines the programming order, maps pages to groups of memory cells 32 accordingly, and stores data in the memory cells in accordance with the order.
  • the programming order is set and carried out by the MSP or by another controller that sends data for storage in device 24.
  • the MSP or controller comprises a control module (which may be implemented in hardware and/or in software) that defines the programming order and controls the memory device to store data in the memory cells in accordance with the appropriate order.
  • Fig. 4 is a flow chart that schematically illustrates a method for programming a block of M bits/cell analog memory cells, in accordance with an embodiment of the present invention.
  • the description that follows assumes that the programming order is set and carried out by R/W unit 36. As noted above, however, the method may also be carried out by an MSP or other controller that controls the memory device.
  • the method of Fig. 4 begins with R/W unit 36 accepting data for storage in array 28, at an input step 90.
  • the R/W unit stores the data starting from a certain initial word line.
  • the R/W unit first stores data in the M-I lower-significance bits of the cells in the word line, at a first programming step 94.
  • the M-I lower-significance bits (pages) of the word line can be programmed in any suitable order, such as the exemplary orders described above.
  • the R/W unit alternates between odd and even cells (bit lines).
  • the R/W unit checks whether all M-I lower-significance bits of the cells in the word line were programmed, at a low-order checking step 98. If not, the method loops back to step 94 above.
  • the R/W unit programs the highest-significance bits (the MSB pages), at a second programming step 102. At this stage, the current word line is fully-programmed.
  • the R/W unit checks whether all data has been stored, at a completion checking step 106. If all data has been stored, the method terminates, at a termination step 110.
  • the R/W unit progresses to the next word line, at an incrementing step 114.
  • the method then loops back to step 94 above, and R/W unit 36 begins to store data in the memory cells of the next word line.
  • the programming order defines that data is stored in ascending order of word lines. Alternatively, however, data can be stored in the word lines in descending order.
  • system 20 may read the storage values of the cells in one or more neighboring word lines and use these values to compensate for the cross-coupling.
  • Cross-coupling compensation can be carried out in different ways.
  • the MSP may adjust the read thresholds used for reading the potentially-interfered word line based on the values read from the potentially-interfering word lines, or it may correct the storage values of the cells in the potentially-interfered word line based on the values read from the potentially-interfering word lines.
  • the MSP may compute soft metrics for decoding an Error Correction Code (ECC) that encodes the data in the cells of potentially- interfered word line based on the values read from the potentially-interfering word lines, or carry out any other process that reduces or cancels the vertical cross-coupling using data or storage values read from one or more potentially-interfering word lines.
  • ECC Error Correction Code
  • the R/W unit When performing digital cancellation of vertical cross-coupling interference using the techniques described above, the R/W unit typically reads the pages of one or more potentially- interfering neighboring word lines in addition to reading the potentially-interfered word line. The R/W unit then caches the potentially-interfered pages and the potentially-interfering pages in page buffers 38 in order to apply interference cancellation.
  • Some of the programming orders described herein are particularly suitable for combining with interference cancellation. When pages are read sequentially in accordance with such orders, the potentially-interfering pages are read in close proximity to the potentially-interfered page. As a result, the size of buffers 38 can be reduced.
  • a higher-significance bit of a given cell is decoded based on the read results of a lower-significance bit that was read previously. For example, in some reading schemes the LSB page is read first, and the CSB page is read and decoded based on the read results of the LSB page.
  • Some of the programming orders described herein, in which CSB pages are programmed (and read) in close proximity to the LSB pages of the same cells, are particularly suitable for combining with such reading schemes. When using these orders, the size of page buffers 38 can be reduced. Reducing the size of the page buffers is particularly important in multi-die or multi-plane memory configurations.
  • a certain programming order may be optimal for reducing certain types of interference under certain conditions, but may not be optimal under different circumstances.
  • the interference in a memory array may change over time.
  • a programming order that is optimal for a newly-deployed array may not be optimal several years later.
  • the level of program disturb typically increases with the number of Programming and Erasure (P/E) cycles that the cells have gone through.
  • P/E Programming and Erasure
  • Other conditions of the array such as temperature, also have an effect on distortion. A change in these conditions may cause a given programming order to become sub-optimal.
  • the control unit modifies the order in which pages are programmed during the lifecycle of the memory, i.e., after the memory has been installed and is operating in a host system.
  • Various triggers and criteria can be used for triggering a switch from one programming order to another.
  • the control unit may switch to a different programming order based on the number of P/E cycles the memory cells have gone through (e.g., when the number of P/E cycles exceeds a certain threshold), based on the time that elapsed since the last programming operation or based on the time that elapsed since the last erase operation.
  • the control unit may measure or estimate the distortion level in the cells (or estimate separate distortion levels attributed to different distortion mechanisms), and switch to a different programming order in response to the measured distortion levels.
  • control unit may switch between the following two programming orders (or programming schemes):
  • Order 1 First the LSB, CSB and MSB pages of the odd cells of wordline N are programmed, then the LSB, CSB and MSB pages of the even cells of wordline N, then the LSB, CSB and MSB pages of the odd cells of wordline N+l, and so on.
  • Order 2 A group of cells are programmed to contain at least a certain number of levels before the neighboring cells are programmed to the full number of levels.
  • An example of this type of order is the programming order described above, in which first the LSB page of the odd cells of wordline N is programmed, then the LSB page of the even cells of the line, then the CSB page of the odd cells, CSB page of the even cells, MSB page of the odd cells, MSB page of the even cells, and only then wordline N+l.
  • order 1 may allow faster programming than order 2, since the cells can be programmed at once to eight levels (rather than programmed to two levels, then to four levels and only then to eight levels). Therefore order 1 is chosen when the level of distortions in the cells is small, and the device can tolerate higher floating-gate interference. When the level of distortions grows higher (for example, in cells in which the level of retention errors is high due to a large number of past program and erase operations), the controller chooses order 2.
  • control unit may use one programming order when sequentially programming a large group of pages, and another programming order when programming single pages or small groups of pages in an intermittent manner.
  • control unit may choose the programming order depending on the expected time discontinuity when programming the cells.
  • some programming orders provide lower cross- coupling interference between partially-programmed cells at the expense of other performance parameters. These programming orders may be preferable when the cells are programmed to different levels with large time gaps. There fore, if it is known in advance that the data accepted for storage at a given time will program a group of cells only partially, it may be preferable to use a programming order having lower cross-coupling interference between partially-programmed cells. In other cases, i.e., when the data accepted for storage will fully- program the cells in question, cross-coupling between partially-programmed cells is not a major concern. In such cases, it may be preferable to use a different programming order that improves other performance parameters.
  • Certain operating conditions of the memory device can also be used as criteria for changing the programming order.
  • the programming orders may comprise any suitable orders, such as the orders described herein and/or the orders described in the Background section above.
  • Fig. 5 is a flow chart that schematically illustrates a method for programming array 28 of multi-level analog memory cells 32, in accordance with an embodiment of the present invention.
  • the method begins with the control unit setting an initial page programming order, at an initialization step 120.
  • system 20 stores data in array 28 in accordance with the initial order, at an initial storage step 124.
  • the control unit tracks the number of P/E cycles of the cells, and checks whether the number of P/E cycles exceeds a predefined threshold, at a switch checking step 128. If the number of P/E cycles has not yet exceeded the threshold, the method loops back to step 124, and the system continues to store data in accordance with the initial programming order.
  • the control unit switches to an alternative page programming order, at a switching step 132.
  • the alternative programming order is better suited for reducing disturb noise, possibly at the expense of some other performance degradation.
  • the system now begins to store data in array 28 in accordance with the alternative programming order, at an alternative storage step 136.
  • control unit may switch between programming orders multiple times, as desired. For example, the control unit may continually track the level of distortion in the array and match the page programming order to the current distortion level.
  • HDD Hard Disk Drives

Abstract

A method for data storage includes predefining an order of programming a plurality of analog memory cells (32) that are arranged in rows (68). The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.

Description

PROGRAMMING ORDERS FOR REDUCING DISTORTION IN ARRAYS OF MULTILEVEL ANALOG MEMORY CELLS
FIELD OF THE INVENTION
The present invention relates generally to memory devices, and particularly to methods and systems for programming arrays of multi-level analog memory cells.
BACKGROUND OF THE INVENTION
Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states. Flash memory devices are described, for example, by Bez et al., in "Introduction to
Flash Memory," Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in "Multilevel Flash Cells and their Trade-Offs," Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, New York, pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?" Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, September 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in "A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate", Proceedings of the
2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, California, February 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory - PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in "Future Memory
Technology including Emerging New Memories," Proceedings of the 24 International
Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Some known methods and systems define specific orders or sequences of programming arrays of analog memory cells, in order to reduce the level of interference in the cells. For example, PCT International Publication WO 2007/146010, whose disclosure is incorporated herein by reference, describes a method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The lower page of predetermined memory cells is programmed with first predetermined data, and the upper page is programmed with second predetermined data. The upper page of the predetermined memory cells is re-programmed with the second predetermined data.
U.S. Patent Application Publication 2003/0002348, whose disclosure is incorporated herein by reference, describes a non- volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states.
U.S. Patent 6,781,877, whose disclosure is incorporated herein by reference, describes techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This technique is said to minimize the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
U.S. Patent Application Publication 2008/0049506, whose disclosure is incorporated herein by reference, describes a method for programming a set of storage elements. The set is programmed beginning with a word line WLn adjacent to a select gate line for the set. After programming the first word line, the next word line WLn+ 1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+ 1 is programmed. WLn+ 1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5,...} until all but the last word line for the set have been programmed. The last word line is then programmed.
U.S. Patent Application Publication 2007/0253249, whose disclosure is incorporated herein by reference, describes a method of programming a nonvolatile memory device comprising a plurality of n- valued nonvolatile memory cells arranged in a matrix, wherein n is a natural number greater than or equal to two. The method includes programming i-valued data to three or more memory cells contiguously arranged along a first direction of the matrix before programming (i+l)-valued data to any of the three or more memory cells, wherein i is less than n, and wherein the three or more memory cells are programmed during three or more respectively distinct program periods, and after programming the i-valued data to the three or more memory cells, programming (i+l)-valued data to a particular memory cell among the three or more memory cells.
Other programming orders for multilevel Flash devices are proposed by Takeuchi et al., in "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories," IEEE Journal of Solid-State Circuits, volume 33, issue 8, August, 1998, pages 1228-1238, which is incorporated herein by reference.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a method for data storage, including: predefining an order of programming a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, wherein the order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming level, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels; and storing data in the memory cells by programming the memory cells in accordance with the predefined order.
In some embodiments, the given row is divided into at least first and second subsets of the memory cells for storing at least first and second memory pages. In one embodiment, the first subset includes odd-order memory cells of the row and the second subset includes even- order memory cells of the row. Additionally or alternatively, the order alternates among the subsets when programming the memory cells in the given row. Further alternatively or additionally, the order specifies that the memory cells in the first subset are programmed to assume the programming levels other than the highest levels only after all the memory cells in the second subset are programmed to assume the programming levels other than the highest levels.
In a disclosed embodiment, when the memory cells in the given rows are subject to cross-coupling interference from the memory cells in the neighboring rows, the method includes reading the data stored in the neighboring rows and processing the read data so as to cancel the cross-coupling interference.
There is also provided, in accordance with an embodiment of the present invention, a method for data storage, including: defining different first and second orders of programming of a plurality of analog memory cells; storing first data by programming the analog memory cells in accordance with the first order; evaluating a predefined switching condition with respect to the memory cells; and responsively to meeting the switching condition, switching from the first order to the second order, and storing second data by programming the analog memory cells in accordance with the second order.
The switching condition may depend on a number of programming and erasure cycles that were applied to the memory cells, on a time that elapsed since a last erasure operation that was applied to the memory cells, on a time that elapsed since a last programming operation that was applied to the memory cells, on an expected time discontinuity in programming the memory cells, on a level of distortion in the memory cells, or on an operating condition of the memory cells.
In one embodiment, the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and one of the first and second orders specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest level.
In another embodiment, each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and the second order specifies that all the memory cells in a given row are programmed to contain at least a certain number of the programming levels before any of the memory cells in the given row are programmed to contain a full number of the programming levels.
There is additionally provided, in acco rdance with an embodiment of the present invention, apparatus for data storage, including: a memory, which includes a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell; and a control module, which is coupled to predefine a programming order specifying that, for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming level, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels, and to store data in the memory cells by programming the memory cells in accordance with the predefined programming order.
There is further provided, in accordance with an embodiment of the present invention, apparatus for data storage, including: a memory, which includes a plurality of analog memory cells; and a control module, which is coupled to define different first and second orders of programming the analog memory cells, to store first data by programming the analog memory cells in accordance with the first order, to evaluate a predefined switching condition with respect to the memory cells and, responsively to meeting the switching condition, to switch from the first order to the second order and to store second data by programming the analog memory cells in accordance with the second order.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;
Fig. 2 is a graph showing threshold voltage distributions in multi-level analog memory cells, in accordance with an embodiment of the present invention; Fig. 3 is a diagram that schematically illustrates an array of multi-level analog memory cells, in accordance with an embodiment of the present invention; and
Figs. 4 and 5 are flow charts that schematically illustrate methods for programming arrays of multi-level analog memory cells, in accordance with embodiments of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS
OVERVIEW
Arrays of analog memory cells often suffer from distortion effects, such as cross- coupling interference and programming disturb. In many cases, the order in which the cells are programmed affects the level of distortion in the cells. For example, when the cells are programmed using a closed-loop Program and Verify (P&V) process, distortion that is already present when the cells are programmed is inherently compensated for. Thus, if cells that potentially cause distortion to a certain target cell are programmed before the target cell, the distortion in the target cell will be compensated for by the P&V process.
As another example, the level of program disturb in a given row of cells may depend on the order in which the rows are programmed in the array. Typically, the level of program disturb in the N row may be higher if the N row is programmed later than both the (N+ 1) row and the (N-I) row, in comparison to programming the N row when either the (N+ 1) row or the (N-I) row is still erased. Specifically, the program disturb in a given cell depends on its bit line voltage.
Embodiments of the present invention that are described hereinbelow provide improved methods and systems for programming arrays of multi-level analog memory cells. In some embodiments, a control module accepts data for storage and stores the data in an array of multi-level analog memory cells, in accordance with a predefined programming order. The array comprises multiple memory cells that are arranged in rows and columns. The cells along each row are connected to a common word line and the cells along each column are connected to a common bit line. The programming orders used by the control module provide an improved trade-off of cross-coupling interference and program disturb. These programming orders are based on two principles:
1. The array is programmed in a monotonic (increasing or decreasing) order of word lines, so that all bits in a given word line are programmed before continuing to the next (higher or lower) word line.
2. Within a given word line, all bits other than the bits mapped to the programming level having the highest storage values (usually threshold voltages) are programmed first, in all the cells in the word line. The bits associated with the highest storage values are programmed only after programming of the other bits is completed for all cells in the word line.
Principle (1) ensures that when a given word line is programmed, the cells in neighboring word lines on at least one side of this word line will be in an erased state. As a result, program disturb effects are reduced. Principle (2) reduces the cross-coupling interference among memory cells within a given word line. Since the bits associated with the highest analog values are programmed last, potentially-interfering cells in the word line are already partially-programmed when the potentially-interfered cells are programmed to their final values. As a result, the P&V process compensates for the majority of the cross-coupling interference within the word line.
In some memory device configurations, a given word line stores multiple memory pages. For example, the memory device may store one page in the odd-order cells of the word line, and another page in the even-order cells. In such configurations, programming typically alternates between the odd and even pages in the word line, until all but the pages associated with the highest analog values are programmed. Several examples of programming orders for four-level, eight-level and sixteen-level cells are described below.
In some embodiments, the control module changes the programming order during the life cycle of the memory array, in order to adapt to different conditions and circumstances. The control module initially stores data in the array using a certain initial programming order. At some point in time, the control module evaluates a predefined switching condition. If the condition is met, the control module switches to a different programming order. Different criteria and switching conditions are described further below.
SYSTEM DESCRIPTION Fig. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules ("disk-on-key" devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.
System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory cell array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term "analog memory cell" is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. Memory cells 32 comprise Multi-Level Cells (MLC, also referred to as multi-bit cells), each storing multiple data bits.
The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.
System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values to the cell. Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. The R/W unit typically (although not necessarily) programs the cells using an iterative Program and Verify (P&V) process, as is known in the art. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. Memory device 24 comprises one or more page buffers 38, which are used for caching data pages during data storage and retrieval.
The storage and retrieval of data in and out of memory device 24 is performed by a Memory Signal Processor (MSP) 40. MSP 40 comprises an interface 44 for communicating with memory device 24, and a signal processing unit 48, which processes the data that is written into and read from device 24. In some embodiments, unit 48 produces the storage values for storing in the memory cells and provides these values to R/W unit 36. Alternatively, unit 48 provides the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device.
MSP 40 communicates with a host 52, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. MSP 40, and in particular unit 48, may be implemented in hardware. Alternatively, MSP 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.
The configuration of Fig. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.
In the exemplary system configuration shown in Fig. 1, memory device 24 and MSP 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and MSP may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC). Further alternatively, some or all of the MSP circuitry may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of MSP 40 can be implemented in software and carried out by a processor or other element of the host system, or by a suitable memory controller. In some implementations, a single MSP 40 may be connected to multiple memory devices 24. In yet another embodiment, some or all of the MSP functionality may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device 24. Typically, the MSP (or any other controller or processor that carries out some or all of the methods described herein) comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory.
Memory cells 32 of array 28 are typically arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively. The array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Cells are typically erased in groups of word lines that are referred to as erasure blocks.
In some embodiments, R/W unit 36 programs memory cells 32 using an iterative Program and Verify (P&V) process. In a typical P&V process, an entire memory page is written by applying a sequence of programming pulses to a group of memory cells that are mapped to this page. The level of the programming pulses increases incrementally from pulse to pulse. The storage values programmed in the cells are read ("verified") after each pulse, and the iterations continue until the desired levels are reached.
INTERFERENCE AND PROGRAMMING ORDER IN MULTI-LEVEL MEMORY CELLS
Arrays of analog memory cells, and in particular Multi-Level Cell (MLC) arrays, suffer from various types of distortion of interference. For example, floating-gate memory cells often suffer from cross-coupling interference from neighboring cells. Cross-coupling interference causes a change in the storage value read from an interfered cell due to changes in the charge levels of one or more interfering cells. Another distortion mechanism, commonly referred to as program disturb or disturb noise, causes a change in the charge of a cell due to voltages applied to the cell when programming other cells in the array. In many cases, the level of distortion in an array of memory cells depends on the relative order in which the cells are programmed. For example, P&V processes are closed-loop processes, which inherently compensate for distortion that is present at the time the cells are being programmed. Therefore, if a potentially-interfered cell is programmed using a P&V process after a potentially-interfering cell has already been programmed, the P&V process will inherently compensate for at least some of the distortion caused by the potentially-interfering cell. On the other hand, if the potentially-interfering cell is programmed later than the potentially-interfered cell (i.e., if the potentially-interfering cell is not programmed at the time the potentially-interfered cell is programmed), then the P&V process will not compensate for the distortion. In intermediate cases, e.g., when the potentially-interfering cell is partially- programmed at the time the potentially-interfered cell is programmed, the P&V process applied to the potentially-interfered cell will compensate for only part of the distortion.
As another example, the level of program disturb in a given row of cells may depend on the order in which the rows are programmed in the array. Typically, the level of program disturb in the N row may be higher if the N row is programmed later than both the (N+ 1) row and the (N-I) row, in comparison to programming the N row when either the (N+ 1)
row or the (N-I) row are still erased. Specifically, the level of program disturb in a given cell depends on the cell's bit line voltage. Embodiments of the present invention provide improved methods and systems for programming arrays of multi-level analog memory cells. The methods and systems described herein program the cells in orders that reduce both cross-coupling interference and program disturb.
The methods and systems described herein use the fact that programming only a subset of the bits of a multi-level cell means programming the cell to a lower storage value. In other words, each additional bit programmed to a multi-level cell increases its storage value. This property is demonstrated in Fig. 2.
Fig. 2 is a graph showing threshold voltage distributions in a group of multi-level analog memory cells, in accordance with an embodiment of the present invention. In the present example, the cells comprise four-level cells, with each cell capable of storing two bits. The first bit written to the cell is referred to as a Least Significant Bit (LSB) and the second bit written to the cell is referred to as a Most Significant Bit (MSB). The terms LSB and MSB are used, however, purely for the sake of clarity, and do not imply that some bits are more important than others. Any other convenient terminology for referring to individual bits in the cell can also be used.
The top graph in Fig. 2 shows the threshold voltage distribution of the cells when all the cells are erased, i.e., before any programming is performed. At this stage, all the cells assume a single erased level 56, in which the threshold voltages are statistically distributed around a certain nominal erased level.
The middle graph in Fig. 2 shows the threshold voltage distribution of the cells when only the LSBs are programmed. In accordance with the programming scheme of Fig. 2, cells that are to store an LSB value of "1" are not subjected to any programming, and remain at a level 58A similar to the erased level. Cells that are to store an LSB value of "0" are programmed to assume a level 58B.
The bottom graph in Fig. 2 shows the threshold voltage distribution of the cells after both the LSBs and MSBs are programmed. For cells that store an LSB=" 1" value (cells in level 58A), an MSB=" 1" value is stored by refraining from adding charge to the cells, thus retaining the cells at a level 60A. In order to program an MSB="0" value to a cell that stores an LSB=" 1" value, charge is added to the cell, causing the cell to assume a level 6OB. In order to program MSB="0" to a cell that stores an LSB="0" value, charge is added to the cell, causing the cell to transition from level 58B to a level 6OC. Programming MSB="1" to a cell that stores an LSB="0" value is accomplished by adding charge to the cell, so as to cause the cell to transition from level 58B to a level 6OD.
As can be appreciated from this example, the threshold voltage of a cell that was programmed with only the first bit is lower than the threshold voltage of the cell after programming both bits. A group of cells in which only the first bits are programmed has, on average, lower storage values that a group of cells that is fully-programmed. In other words, cells that are partially-programmed have lower analog storage values than cells that are fully- programmed.
The example of Fig. 2 refers to a particular programming scheme of a 2 bits/cell array. However, the property according to which cells that are programmed with only a subset of the bits have lower storage values than cells that are fully-programmed is equally applicable to various other programming schemes and to memory cells storing higher numbers of bit. For example, embodiments that use 3 bits/cell memory cells storing an LSB, Central Significance Bit (CSB) and MSB are described further below.
As noted above, a memory array typically comprises a large number of memory cells that are arranged in rows and columns. The cells along each row are connected to a word line, and the cells along each column are connected to a bit line. A page of data is typically written simultaneously to a group of cells along a word line.
In some memory configurations, each word line (row) stores a single page. In other configurations, different bits of a multi-level cell are mapped to different pages. For example, in a group of 2 bits/cell memory cells, one page can be stored in the LSBs of the cells and another page can be stored in the MSBs. In the description that follows, a page stored in the LSBs of the cells is referred to as an LSB page, and a page stored in the MSBs is referred to as an MSB page for brevity. Additionally or alternatively, some memory device configurations partition the cells along each word line into two or more groups, e.g., into odd-order and even-order cells, and store different pages in the different groups. Thus, a row of 2 bits/cell memory cells may store four memory pages - one page in the LSBs of the odd-order cells, a second page in the MSBs of the odd-order cell, a third page in the LSBs of the even-order cells and a fourth page in the MSBs of the even-order cells. Configurations that divide each word line into four groups or into any other number of groups, are also feasible. Typically although not necessarily, the cells along each word line is partitioned into groups in an interleaved manner.
Fig. 3 is a diagram that schematically illustrates an array 64 of multi-level analog memory cells 66, in accordance with an exemplary embodiment of the present invention. Cells 66 are connected by word lines 68 and bit lines 70. In the present example, cells 66 comprise 2 bits/cell memory cells, and each word line is divided into odd- and even-order cells. The odd- order cells are shaded in the figure. Thus, each word line 68 stores four memory pages, referred to as LSB/ODD, LSB/EVEN, MSB/ODD and MSB/EVEN.
PAGE PROGRAMMING ORDERS FOR REDUCED INTERFERENCE The programming orders defined herein provide an improved trade-off of cross- coupling interference and program disturb. These programming orders are based on two principles:
1. The array is programmed in a monotonic (increasing or decreasing) order of word lines, so that all pages (bits) in a given word line are programmed before continuing to the next (higher or lower) word line.
2. Within a given word line, the lower-order pages (bits) are programmed first for all the cells in the word line. The highest-significance bits (MSB page or pages) are programmed only after programming of lower-significance bits is completed for all cells in the word line. Principle (1) above ensures that when a given word line is programmed, the cells in neighboring word lines on at least one side of this word line will be in an erased state. As a result, program disturb effects are reduced. Principle (2) above reduces the cross-coupling interference among memory cells within a given word line (also referred to as horizontal cross-coupling, because the interfering cells belong to the same word line as the interfered cell). Since the MSB pages are programmed last, potentially-interfering cells in the word line are already partially- programmed when the potentially-interfered cells are programmed to their final values. As a result, the P&V process compensates for the majority of the cross-coupling interference within the word line.
In some embodiments, principle (2) above is extended, so as to ensure that the one or more highest programming levels are programmed only after the programming levels other than the highest levels are programmed, for all the cells in the given word line.
Note that a given word line may store multiple pages, such as in odd-order and even- order cells. In such configurations, programming typically alternates between the odd and even pages in the word line, until all but the highest programming levels (MSB pages) are programmed. In bit programming terminology, principle (2) above means that, within a given word line of an M-bit MLC device, the first M-I bits of all cells are programmed first. The M bits of the cells in the word line are programmed only after programming of the first M-I bits is completed.
The following table demonstrates a possible programming order that follows principles (1) and (2) above:
Word line Bit EVEN ODD
Figure imgf000015_0001
Figure imgf000016_0001
The table defines an order for programming an array of 3 bits/cell memory cells. The array has N word lines. The cells in each word lines are partitioned into odd- and even-order cells, so that each word line stored six pages. In accordance with the table, the word lines are programmed in a monotonically-increasing order starting from word line 0. Within each word line, the order of programming is EVEN/LSB, ODD/LSB, EVEN/CSB, ODD/CSB, EVEN/MSB and finally ODD/MSB.
In alternative embodiments, the word lines can be programmed in a monotonically- decreasing order. Further alternatively, the odd-order page in a given bit can be programmed before the corresponding even-order bit. Any other suitable variation to this order may be applied, while meeting principles (1) and (2) above.
Another possible programming order is described in the following table:
Word line Bit EVEN ODD
Figure imgf000016_0002
Figure imgf000017_0001
In this programming order, there is no alternation between odd and even pages when programming the LSB and CSB. This order is sometimes preferable, because the CSB page in a given word line is programmed immediately following the LSB page. This proximity may simplify page buffering operations carried out when programming the cells. On the other hand, this advantage may come at the expense of increased cross-coupling when the cells are not fully-programmed, e.g., the cross-coupling when programming the even-order CSB page. As in the previous example, various variations can be applied to the programming order, as long as principles (1) and (2) above are met.
The following three tables show exemplary programming orders for 4 bits/cell memory cells:
Word line Bit EVEN ODD
Figure imgf000017_0002
In some embodiments, the programming order is set and carried out within memory device 24. In these embodiments, R/W unit 36 comprises a control module that defines the programming order, maps pages to groups of memory cells 32 accordingly, and stores data in the memory cells in accordance with the order. In alternative embodiments, the programming order is set and carried out by the MSP or by another controller that sends data for storage in device 24. In these embodiments, the MSP or controller comprises a control module (which may be implemented in hardware and/or in software) that defines the programming order and controls the memory device to store data in the memory cells in accordance with the appropriate order.
Fig. 4 is a flow chart that schematically illustrates a method for programming a block of M bits/cell analog memory cells, in accordance with an embodiment of the present invention. The description that follows assumes that the programming order is set and carried out by R/W unit 36. As noted above, however, the method may also be carried out by an MSP or other controller that controls the memory device.
The method of Fig. 4 begins with R/W unit 36 accepting data for storage in array 28, at an input step 90. The R/W unit stores the data starting from a certain initial word line. The R/W unit first stores data in the M-I lower-significance bits of the cells in the word line, at a first programming step 94. The M-I lower-significance bits (pages) of the word line can be programmed in any suitable order, such as the exemplary orders described above. In some embodiments, the R/W unit alternates between odd and even cells (bit lines). The R/W unit checks whether all M-I lower-significance bits of the cells in the word line were programmed, at a low-order checking step 98. If not, the method loops back to step 94 above.
Once all M-I lower-significance bits of the cells in the word line are programmed, the R/W unit programs the highest-significance bits (the MSB pages), at a second programming step 102. At this stage, the current word line is fully-programmed. The R/W unit checks whether all data has been stored, at a completion checking step 106. If all data has been stored, the method terminates, at a termination step 110.
Otherwise, i.e., when there is data remaining for storage, the R/W unit progresses to the next word line, at an incrementing step 114. The method then loops back to step 94 above, and R/W unit 36 begins to store data in the memory cells of the next word line. In the present example, the programming order defines that data is stored in ascending order of word lines. Alternatively, however, data can be stored in the word lines in descending order.
Some of the programming orders described above are optimal for reducing program disturb and horizontal cross-coupling (cross-coupling from other cells in the same word line), but do not always account for vertical cross-coupling (cross-coupling from cells in neighboring word lines). In order to reduce vertical cross-coupling in the cells in a given word line, system 20 may read the storage values of the cells in one or more neighboring word lines and use these values to compensate for the cross-coupling. Cross-coupling compensation can be carried out in different ways. For example, the MSP may adjust the read thresholds used for reading the potentially-interfered word line based on the values read from the potentially-interfering word lines, or it may correct the storage values of the cells in the potentially-interfered word line based on the values read from the potentially-interfering word lines. Alternatively, the MSP may compute soft metrics for decoding an Error Correction Code (ECC) that encodes the data in the cells of potentially- interfered word line based on the values read from the potentially-interfering word lines, or carry out any other process that reduces or cancels the vertical cross-coupling using data or storage values read from one or more potentially-interfering word lines. Cross-coupling cancellation methods that can be used for this purpose are described, for example in PCT International Publication WO 2007/132453, entitled "Distortion Estimation and Cancellation in Memory Devices," filed May 10, 2007, PCT International Publication PCT/IL2007/001059, entitled "Estimation of Non-Linear Distortion in Memory Devices," filed August 27, 2007, PCT International Publication WO 2007/132457, entitled "Combined Distortion Estimation and Error Correction Coding for Memory Devices," filed May 10, 2007, and U.S. Patent Application serial Number 11/995,814, entitled "Reading Memory Cells using Multiple Thresholds," filed January 15, 2008, whose disclosures are incorporated herein by reference.
When performing digital cancellation of vertical cross-coupling interference using the techniques described above, the R/W unit typically reads the pages of one or more potentially- interfering neighboring word lines in addition to reading the potentially-interfered word line. The R/W unit then caches the potentially-interfered pages and the potentially-interfering pages in page buffers 38 in order to apply interference cancellation. Some of the programming orders described herein are particularly suitable for combining with interference cancellation. When pages are read sequentially in accordance with such orders, the potentially-interfering pages are read in close proximity to the potentially-interfered page. As a result, the size of buffers 38 can be reduced.
In some MLC reading schemes, a higher-significance bit of a given cell is decoded based on the read results of a lower-significance bit that was read previously. For example, in some reading schemes the LSB page is read first, and the CSB page is read and decoded based on the read results of the LSB page. Some of the programming orders described herein, in which CSB pages are programmed (and read) in close proximity to the LSB pages of the same cells, are particularly suitable for combining with such reading schemes. When using these orders, the size of page buffers 38 can be reduced. Reducing the size of the page buffers is particularly important in multi-die or multi-plane memory configurations.
MODIFYING THE PROGRAMMING ORDER DURING THE LIFECYCLE OF THE
MEMORY An explained and demonstrated above, different programming orders have different advantages and disadvantages. A certain programming order may be optimal for reducing certain types of interference under certain conditions, but may not be optimal under different circumstances. The interference in a memory array may change over time. In such a case, a programming order that is optimal for a newly-deployed array may not be optimal several years later. For example, the level of program disturb typically increases with the number of Programming and Erasure (P/E) cycles that the cells have gone through. Thus, it may be preferable to apply a certain programming order that is best-suited for reducing cross-coupling at the beginning of the memory's life, and switch to another programming order that is better suited for reducing program disturb at a later stage. Other conditions of the array, such as temperature, also have an effect on distortion. A change in these conditions may cause a given programming order to become sub-optimal.
In some embodiments of the present invention, the control unit (in the memory device or in the MSP or controller) modifies the order in which pages are programmed during the lifecycle of the memory, i.e., after the memory has been installed and is operating in a host system. Various triggers and criteria (referred to herein as "switching conditions") can be used for triggering a switch from one programming order to another. For example, the control unit may switch to a different programming order based on the number of P/E cycles the memory cells have gone through (e.g., when the number of P/E cycles exceeds a certain threshold), based on the time that elapsed since the last programming operation or based on the time that elapsed since the last erase operation. As another example, the control unit may measure or estimate the distortion level in the cells (or estimate separate distortion levels attributed to different distortion mechanisms), and switch to a different programming order in response to the measured distortion levels.
In one embodiment, the control unit may switch between the following two programming orders (or programming schemes):
• Order 1 : First the LSB, CSB and MSB pages of the odd cells of wordline N are programmed, then the LSB, CSB and MSB pages of the even cells of wordline N, then the LSB, CSB and MSB pages of the odd cells of wordline N+l, and so on. • Order 2: A group of cells are programmed to contain at least a certain number of levels before the neighboring cells are programmed to the full number of levels. An example of this type of order is the programming order described above, in which first the LSB page of the odd cells of wordline N is programmed, then the LSB page of the even cells of the line, then the CSB page of the odd cells, CSB page of the even cells, MSB page of the odd cells, MSB page of the even cells, and only then wordline N+l.
While order 2 is more robust than order 1 against floating-gate interference, order 1 may allow faster programming than order 2, since the cells can be programmed at once to eight levels (rather than programmed to two levels, then to four levels and only then to eight levels). Therefore order 1 is chosen when the level of distortions in the cells is small, and the device can tolerate higher floating-gate interference. When the level of distortions grows higher (for example, in cells in which the level of retention errors is high due to a large number of past program and erase operations), the controller chooses order 2.
Further alternatively, the control unit may use one programming order when sequentially programming a large group of pages, and another programming order when programming single pages or small groups of pages in an intermittent manner. In other words, the control unit may choose the programming order depending on the expected time discontinuity when programming the cells.
For example, as explained above, some programming orders provide lower cross- coupling interference between partially-programmed cells at the expense of other performance parameters. These programming orders may be preferable when the cells are programmed to different levels with large time gaps. There fore, if it is known in advance that the data accepted for storage at a given time will program a group of cells only partially, it may be preferable to use a programming order having lower cross-coupling interference between partially-programmed cells. In other cases, i.e., when the data accepted for storage will fully- program the cells in question, cross-coupling between partially-programmed cells is not a major concern. In such cases, it may be preferable to use a different programming order that improves other performance parameters.
Certain operating conditions of the memory device, such as temperature, can also be used as criteria for changing the programming order. The programming orders may comprise any suitable orders, such as the orders described herein and/or the orders described in the Background section above.
Fig. 5 is a flow chart that schematically illustrates a method for programming array 28 of multi-level analog memory cells 32, in accordance with an embodiment of the present invention. The method begins with the control unit setting an initial page programming order, at an initialization step 120. Initially, system 20 stores data in array 28 in accordance with the initial order, at an initial storage step 124.
The control unit tracks the number of P/E cycles of the cells, and checks whether the number of P/E cycles exceeds a predefined threshold, at a switch checking step 128. If the number of P/E cycles has not yet exceeded the threshold, the method loops back to step 124, and the system continues to store data in accordance with the initial programming order.
If, on the other hand, the number of P/E cycles exceeds the threshold, the control unit switches to an alternative page programming order, at a switching step 132. In the present example, the alternative programming order is better suited for reducing disturb noise, possibly at the expense of some other performance degradation. The system now begins to store data in array 28 in accordance with the alternative programming order, at an alternative storage step 136.
Although Fig. 5 shows a single switching operation during the memory's lifetime, the control unit may switch between programming orders multiple times, as desired. For example, the control unit may continually track the level of distortion in the array and match the page programming order to the current distortion level.
Although the embodiments described herein mainly address data storage and retrieval in solid-state memory devices, the principles of the present invention can also be used for storing and retrieving data in Hard Disk Drives (HDD) and other data storage media and devices.
It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. A method for data storage, comprising: predefining an order of programming a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, wherein the order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming levels, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels; and storing data in the memory cells by programming the memory cells in accordance with the predefined order.
2. The method according to claim 1, wherein the given row is divided into at least first and second subsets of the memory cells for storing at least first and second memory pages.
3. The method according to claim 2, wherein the first subset comprises odd-order memory cells of the row and the second subset comprises even-order memory cells of the row.
4. The method according to claim 2, wherein the order alternates among the subsets when programming the memory cells in the given row.
5. The method according to claim 2, wherein the order specifies that the memory cells in the first subset are programmed to assume the programming levels other than the highest levels only after all the memory cells in the second subset are programmed to assume the programming levels other than the highest levels.
6. The method according to claim 1 or 2, wherein the memory cells in the given rows are subject to cross-coupling interference from the memory cells in the neighboring rows, and comprising reading the data stored in the neighboring rows and processing the read data so as to cancel the cross-coupling interference.
7. The method according to claim 1 or 2, wherein storing the data comprises initially programming the memory cells in accordance with an initial order that is different from the predefined order, evaluating a switching condition with respect to the memory cells, and switching to programming the memory cells in accordance with the predefined order responsively to meeting the switching condition.
8. A method for data storage, comprising: defining different first and second orders of programming of a plurality of analog memory cells; storing first data by programming the analog memory cells in accordance with the first order; evaluating a predefined switching condition with respect to the memory cells; and responsively to meeting the switching condition, switching from the first order to the second order, and storing second data by programming the analog memory cells in accordance with the second order.
9. The method according to claim 8, wherein the switching condition depends on a number of programming and erasure cycles that were applied to the memory cells.
10. The method according to claim 8, wherein the switching condition depends on a time that elapsed since a last erasure operation that was applied to the memory cells.
11. The method according to claim 8, wherein the switching condition depends on a time that elapsed since a last programming operation that was applied to the memory cells.
12. The method according to claim 8, wherein the switching condition depends on an expected time discontinuity in programming the memory cells.
13. The method according to claim 8, wherein the switching condition depends on a level of distortion in the memory cells.
14. The method according to claim 8, wherein the switching condition depends on an operating condition of the memory cells.
15. The method according to claims 8-14, wherein the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and wherein one of the first and second orders specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest level.
16. The method according to claims 8-14, wherein the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and wherein the second order specifies that all the memory cells in a given row are programmed to contain at least a certain number of the programming levels before any of the memory cells in the given row are programmed to contain a full number of the programming levels.
17. Apparatus for data storage, comprising: a memory, which comprises a plurality of analog memory cells that are arranged in rows, wherein the memory cells in each row are associated with a respective word line, and wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell; and a control module, which is coupled to predefine a programming order specifying that, for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume one or more highest programming levels, which correspond to respective largest analog values among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest levels, and to store data in the memory cells by programming the memory cells in accordance with the predefined programming order.
18. The apparatus according to claim 17, wherein the given row is divided into at least first and second subsets of the memory cells for storing at least first and second memory pages.
19. The apparatus according to claim 18, wherein the first subset comprises odd-order memory cells of the row and the second subset comprises even-order memory cells of the row.
20. The apparatus according to claim 18, wherein the order alternates among the subsets when programming the memory cells in the given row.
21. The apparatus according to claim 18, wherein the order specifies that the memory cells in the first subset are programmed to assume the programming levels other than the highest levels only after all the memory cells in the second subset are programmed to assume the programming levels other than the highest levels.
22. The apparatus according to claim 17 or 18, wherein the memory cells in the given rows are subject to cross-coupling interference from the memory cells in the neighboring rows, and wherein the control module is coupled to read the data stored in the neighboring rows and to process the read data so as to cancel the cross-coupling interference.
23. The apparatus according to claim 17 or 18, wherein the control module is coupled to initially program the memory cells in accordance with an initial order that is different from the predefined order, to evaluate a switching condition with respect to the memory cells, and to switch to programming the memory cells in accordance with the predefined order responsively to meeting the switching condition.
24. Apparatus for data storage, comprising: a memory, which comprises a plurality of analog memory cells; and a control module, which is coupled to define different first and second orders of programming the analog memory cells, to store first data by programming the analog memory cells in accordance with the first order, to evaluate a predefined switching condition with respect to the memory cells and, responsively to meeting the switching condition, to switch from the first order to the second order and to store second data by programming the analog memory cells in accordance with the second order.
25. The apparatus according to claim 24, wherein the switching condition depends on a number of programming and erasure cycles that were applied to the memory cells.
26. The apparatus according to claim 24, wherein the switching condition depends on a time that elapsed since a last erasure operation that was applied to the memory cells.
27. The apparatus according to claim 24, wherein the switching condition depends on a time that elapsed since a last programming operation that was applied to the memory cells.
28. The apparatus according to claim 24, wherein the switching condition depends on an expected time discontinuity in programming the memory cells.
29. The apparatus according to claim 24, wherein the switching condition depends on a level of distortion in the memory cells.
30. The apparatus according to claim 24, wherein the switching condition depends on an operating condition of the memory cells.
31. The apparatus according to claims 24-30, wherein the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and wherein one of the first and second orders specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the analog values, only after programming all the memory cells in the given row to assume the programming levels other than the highest level.
32. The apparatus according to claim 24-30, wherein the memory cells are arranged in rows, wherein the memory cells in each row are associated with a respective word line, wherein each memory cell is programmable to assume programming levels corresponding to respective analog values written to the memory cell, and wherein the second order specifies that all the memory cells in a given row are programmed to contain at least a certain number of the programming levels before any of the memory cells in the given row are programmed to contain a full number of the programming levels.
PCT/IL2008/001188 2007-09-19 2008-09-03 Programming orders for reducing distortion in arrays of multi-level analog memory cells WO2009037691A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/721,585 US8174905B2 (en) 2007-09-19 2010-03-11 Programming orders for reducing distortion in arrays of multi-level analog memory cells
US13/412,780 US8300478B2 (en) 2007-09-19 2012-03-06 Reducing distortion using joint storage
US13/412,731 US8437185B2 (en) 2007-09-19 2012-03-06 Programming orders for reducing distortion based on neighboring rows

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US97345307P 2007-09-19 2007-09-19
US60/973,453 2007-09-19
US1242407P 2007-12-08 2007-12-08
US61/012,424 2007-12-08
US1293307P 2007-12-12 2007-12-12
US61/012,933 2007-12-12
US5449308P 2008-05-20 2008-05-20
US61/054,493 2008-05-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/721,585 Continuation-In-Part US8174905B2 (en) 2007-09-19 2010-03-11 Programming orders for reducing distortion in arrays of multi-level analog memory cells

Publications (2)

Publication Number Publication Date
WO2009037691A2 true WO2009037691A2 (en) 2009-03-26
WO2009037691A3 WO2009037691A3 (en) 2010-03-04

Family

ID=40468551

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2008/001188 WO2009037691A2 (en) 2007-09-19 2008-09-03 Programming orders for reducing distortion in arrays of multi-level analog memory cells

Country Status (1)

Country Link
WO (1) WO2009037691A2 (en)

Cited By (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7697326B2 (en) 2006-05-12 2010-04-13 Anobit Technologies Ltd. Reducing programming error in memory devices
US7706182B2 (en) 2006-12-03 2010-04-27 Anobit Technologies Ltd. Adaptive programming of analog memory cells using statistical characteristics
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US7821826B2 (en) 2006-10-30 2010-10-26 Anobit Technologies, Ltd. Memory cell readout using successive approximation
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8050086B2 (en) 2006-05-12 2011-11-01 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8239735B2 (en) 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8270246B2 (en) 2007-11-13 2012-09-18 Apple Inc. Optimized selection of memory chips in multi-chips memory devices
US8315092B2 (en) 2010-01-27 2012-11-20 Fusion-Io, Inc. Apparatus, system, and method for determining a read voltage threshold for solid-state storage media
US8369141B2 (en) 2007-03-12 2013-02-05 Apple Inc. Adaptive estimation of memory cell read thresholds
US8380915B2 (en) 2010-01-27 2013-02-19 Fusion-Io, Inc. Apparatus, system, and method for managing solid-state storage media
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8429493B2 (en) 2007-05-12 2013-04-23 Apple Inc. Memory device with internal signap processing unit
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8493781B1 (en) 2010-08-12 2013-07-23 Apple Inc. Interference mitigation using individual word line erasure operations
US8527841B2 (en) 2009-03-13 2013-09-03 Fusion-Io, Inc. Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US8645794B1 (en) 2010-07-31 2014-02-04 Apple Inc. Data storage in analog memory cells using a non-integer number of bits per cell
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
WO2017074581A1 (en) * 2015-10-30 2017-05-04 Sandisk Technologies Llc Non-volatile memory system with multi-write direction memory units
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040105311A1 (en) * 1998-10-23 2004-06-03 Raul-Adrian Cernea Non-volatile memory with improved sensing and method therefor
US7079555B2 (en) * 1993-03-09 2006-07-18 Pulse Communications, Inc. Integrated digital loop carrier system with virtual tributary mapper circuit
US20060256626A1 (en) * 1998-06-30 2006-11-16 Werner Carl W Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7079555B2 (en) * 1993-03-09 2006-07-18 Pulse Communications, Inc. Integrated digital loop carrier system with virtual tributary mapper circuit
US20060256626A1 (en) * 1998-06-30 2006-11-16 Werner Carl W Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency
US20040105311A1 (en) * 1998-10-23 2004-06-03 Raul-Adrian Cernea Non-volatile memory with improved sensing and method therefor

Cited By (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7697326B2 (en) 2006-05-12 2010-04-13 Anobit Technologies Ltd. Reducing programming error in memory devices
US8239735B2 (en) 2006-05-12 2012-08-07 Apple Inc. Memory Device with adaptive capacity
US8570804B2 (en) 2006-05-12 2013-10-29 Apple Inc. Distortion estimation and cancellation in memory devices
US8599611B2 (en) 2006-05-12 2013-12-03 Apple Inc. Distortion estimation and cancellation in memory devices
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8050086B2 (en) 2006-05-12 2011-11-01 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7821826B2 (en) 2006-10-30 2010-10-26 Anobit Technologies, Ltd. Memory cell readout using successive approximation
USRE46346E1 (en) 2006-10-30 2017-03-21 Apple Inc. Reading memory cells using multiple thresholds
US8145984B2 (en) 2006-10-30 2012-03-27 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7706182B2 (en) 2006-12-03 2010-04-27 Anobit Technologies Ltd. Adaptive programming of analog memory cells using statistical characteristics
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US7881107B2 (en) 2007-01-24 2011-02-01 Anobit Technologies Ltd. Memory device with negative thresholds
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US8369141B2 (en) 2007-03-12 2013-02-05 Apple Inc. Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8429493B2 (en) 2007-05-12 2013-04-23 Apple Inc. Memory device with internal signap processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8270246B2 (en) 2007-11-13 2012-09-18 Apple Inc. Optimized selection of memory chips in multi-chips memory devices
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8527841B2 (en) 2009-03-13 2013-09-03 Fusion-Io, Inc. Apparatus, system, and method for using multi-level cell solid-state storage as reduced-level cell solid-state storage
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8677203B1 (en) 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8873286B2 (en) 2010-01-27 2014-10-28 Intelligent Intellectual Property Holdings 2 Llc Managing non-volatile media
US8380915B2 (en) 2010-01-27 2013-02-19 Fusion-Io, Inc. Apparatus, system, and method for managing solid-state storage media
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
US8315092B2 (en) 2010-01-27 2012-11-20 Fusion-Io, Inc. Apparatus, system, and method for determining a read voltage threshold for solid-state storage media
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8645794B1 (en) 2010-07-31 2014-02-04 Apple Inc. Data storage in analog memory cells using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8493781B1 (en) 2010-08-12 2013-07-23 Apple Inc. Interference mitigation using individual word line erasure operations
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
WO2017074581A1 (en) * 2015-10-30 2017-05-04 Sandisk Technologies Llc Non-volatile memory system with multi-write direction memory units
US9728262B2 (en) 2015-10-30 2017-08-08 Sandisk Technologies Llc Non-volatile memory systems with multi-write direction memory units
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Also Published As

Publication number Publication date
WO2009037691A3 (en) 2010-03-04

Similar Documents

Publication Publication Date Title
US8437185B2 (en) Programming orders for reducing distortion based on neighboring rows
WO2009037691A2 (en) Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8300478B2 (en) Reducing distortion using joint storage
US7924587B2 (en) Programming of analog memory cells using a single programming pulse per state transition
US7697326B2 (en) Reducing programming error in memory devices
US8059457B2 (en) Memory device with multiple-accuracy read commands
US9230681B2 (en) Selective activation of programming schemes in analog memory cell arrays
US7925936B1 (en) Memory device with non-uniform programming levels
EP2562759B1 (en) Memory device with reduced sense time readout
US9153329B2 (en) Selective re-programming of analog memory cells
US8493781B1 (en) Interference mitigation using individual word line erasure operations
US8400858B2 (en) Memory device with reduced sense time readout
US9105311B2 (en) Inter-word-line programming in arrays of analog memory cells
KR101343698B1 (en) Sparse programming of analog memory cells
US9779818B2 (en) Adaptation of high-order read thresholds
US9230680B2 (en) Applications for inter-word-line programming

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08789859

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08789859

Country of ref document: EP

Kind code of ref document: A2