WO2009053355A1 - Method of splitting a substrate - Google Patents
Method of splitting a substrate Download PDFInfo
- Publication number
- WO2009053355A1 WO2009053355A1 PCT/EP2008/064200 EP2008064200W WO2009053355A1 WO 2009053355 A1 WO2009053355 A1 WO 2009053355A1 EP 2008064200 W EP2008064200 W EP 2008064200W WO 2009053355 A1 WO2009053355 A1 WO 2009053355A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- splitting
- sector
- wave
- notch
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Definitions
- the present invention relates to a method of splitting a substrate, in particular one applicable in the fabrication of an SOI (semiconductor-on- insulator) structure by a film transfer process of the SmartCutTM type.
- SOI semiconductor-on- insulator
- the SmartCutTM process comprises, in a first step, the formation in what is called a donor substrate of a weakened zone defining the boundary of a thin film intended to be transferred onto what is called a receiver substrate.
- the donor substrate is split so as to transfer the thin film onto the receiver substrate.
- the splitting is initiated at a predetermined point on the periphery of the donor substrate, followed by propagation in the form of a splitting wave into the rest of the substrate.
- the splitting is initiated for example by means of mechanical forces, by localized heating, etc.
- This notch which is generally triangular and penetrates about 2 mm (along the diameter of the wafer), enables the orientation of the wafer to be identified during the various steps of the process.
- the notch which is made by the wafer manufacturer before the wafer is cut from the ingot, enables the crystal orientation of the substrate to be identified.
- FIG. 1 A photograph of such a line associated with the notch is shown in Figure 1.
- the notch is identified by the reference sign 4 and the process line is surrounded by dots. From analyses carried out by the Applicant, this line corresponds to the tearing of the thin transverse film, initiated around the notch by localized stresses.
- a first object of the invention is therefore to improve the process for fabricating a film transfer structure so as to prevent the formation of such a line around the notch on the final structure.
- Another object of the invention is to define a method of splitting a substrate that reduces the appearance of a line associated with the notch.
- the invention provides a process for splitting a semiconductor substrate having an identification notch on its periphery, which process comprises the steps of: (a) creating a weakened zone in the substrate;
- splitting the substrate along the weakened zone comprising the initiation, in a predetermined sector on the periphery of the substrate, of a splitting wave followed by the propagation of said wave into the substrate, said process being characterized in that:
- step (a) the weakened zone created in step (a) is obtained by the implantation of atomic species into the substrate, the substrate being held in place on a portion of its periphery, during the implantation, by a fastening device,
- step (b) in that, during the splitting step (b), said portion is placed in the splitting-wave initiation sector, and in that during step (b) the notch is positioned so that it is in the quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate centred on said initiation sector.
- Said sector in which the notch lies is thus between 135° and 225° or between 315° and 45° to the bisector of the splitting-wave initiation sector.
- step (b) the substrate is placed in a vertical position in a furnace, so that the splitting-wave initiation sector is centred on the top of the substrate and the notch is located in the lower quarter or in the upper quarter of the substrate.
- step (b) the splitting wave is initiated by means of a mechanical stress applied in the initiation sector.
- the splitting-wave initiation sector is preferably a 90° sector.
- the process further comprises, between step (a) and step (b) a step of direct bonding of said substrate to a receiver substrate, so that after step (b) the film defined by the weakened zone is transferred to the receiver substrate.
- Another subject of the invention relates to a batch of split substrates having an identification notch, characterized in that said batch is obtained by a process as described above, and in that the proportion of substrates having a process line associated with the notch is less than 12%.
- FIG. 1 is a photograph of a process line associated with the notch
- - Figure 2 illustrates schematically a splitting device
- - Figure 3 is a photograph of the front of a splitting-wave initiated in a region diametrically opposite the notch
- FIG. 4 is a photograph of the front of a splitting-wave initiated in a region oriented at 90° to the notch;
- FIGS. 5A and 5B show schematically the orientation of the notch on the wafer relative to the splitting-wave initiation sector
- - Figure 6 illustrates schematically the fixed restraint device for holding the wafer in position during the implantation
- - Figure 7 shows the occurrence of the process line on batches of wafers fabricated respectively with a notch positioned unfavourably and favourably with respect to the splitting-wave initiation sector.
- the invention relates to a process of splitting a substrate in general, it will be hereinafter described referring to the case of the fabrication of a semiconductor structure by transferring a film from a substrate (also called, in this context, "donor substrate") to a receiver substrate. It must be understood, however, that the invention is neither limited to a substrate (also called, in this context, "donor substrate") to a receiver substrate.
- SmartCutTM process nor involves necessarily a bonding of the substrate to be split to another substrate.
- the donor substrate undergoes the following steps: a) creation of a weakened zone defining a thin film to be transferred onto the receiver substrate.
- this weakened zone is formed by implanting atomic species - for example hydrogen or helium atoms - into the wafer.
- the definition of the implantation conditions (dose, energy), according to the nature of the substrate and the desired implantation depth, is within the competence of a person skilled in the art; and b) bonding - for example direct bonding (by molecular adhesion) - to the receiver substrate. Surface treatments well known to those skilled in the art may be carried out on the substrates before bonding, in order to increase the bonding energy.
- the splitting is carried out along the weakened zone in such a way that the thin film is transferred onto the receiver substrate, the remainder of the donor substrate being recovered, for example to be recycled.
- an annealing operation may be carried out or a mechanical force may be applied at a point in the weakened zone.
- the splitting is initiated in a predetermined sector on the periphery of the wafer, and then a splitting wave propagates into the rest of the wafer.
- the splitting-wave initiation sector is controlled by a person skilled in the art depending on the means employed for the splitting operation. Situation in which the splitting is initiated by application of a force
- a first possibility is to initiate the splitting by inserting a blade at one point on the periphery of the weakened zone. It is therefore a person skilled in the art who chooses and therefore directly controls the splitting-wave initiation sector. Situation in which the splitting is initiated by annealing
- a wafer 1 is placed in a vertical position in a boat 2 which can be inserted into a furnace 3, as shown in Figure 2.
- the means for keeping the wafer in position are well known to those skilled in the art and will therefore not be described in greater detail.
- the wafer 1 is placed in such a way that the notch 4 is oriented at
- This orientation of the notch 4 is not imperative, but it does correspond to the position in which the wafers are placed during the previous step of the process, i.e. the bonding step. To avoid handling the wafers, this same orientation is therefore maintained for the splitting step.
- the furnace enclosure is brought to the splitting temperature (typically between 300° and 600 0 C), by heaters (not shown). These heaters deliver uniform heat into the furnace. However, that part of the wafer 1 in contact with the boat 2 rises in temperature less easily than the upper part because of a greater mass, which absorbs the heat.
- the splitting temperature typically between 300° and 600 0 C
- the wafer 1 therefore has what is called a "hot” zone (indicated by the arrow ZC) corresponding approximately to the upper half of the wafer, located away from the boat, and what is called a "cool” zone (indicated by the arrow
- the splitting is initiated in the hottest zone of the wafer 1 , therefore in a sector R located near the top of the wafer (corresponding in Figure 2 to a 0° orientation) and propagates in the form of a wave into the wafer.
- the expression "near the top” is understood in this text to mean an angular sector R lying between -45° and +45°, more particularly between -20° and +20° and preferably between -5° and +5° with respect to the top of the wafer.
- the splitting-wave initiation sector R is therefore controlled indirectly by the conditions under which the annealing is carried out.
- the initiation of the splitting-wave takes place on average at the top of the wafer, that is to say on the bisector of the sector R.
- the Applicant has conducted splitting trials in which the orientation of the notch 4 relative to the boat 2 was varied, the splitting always being initiated in the hot zone of the wafer, that is to say, with reference to Figure 2, in a sector R centred on a 0° orientation with respect to the vertical.
- the Applicant has observed that the formation of the process line associated with the notch 4 is prevented when the notch 4 is located either in a sector oriented at between 135° and 225° with respect to the vertical, that is to say with respect to the bisector of the splitting initiation sector R, or in a sector oriented between 315° (or -45°) and 45° with respect to the bisector of the splitting initiation sector.
- This beneficial orientation corresponds in fact to two preferential sectors for positioning the notch 4.
- Figure 5A shows a first favourable position of the notch 4 in a sector S1 diametrically opposite the splitting-wave initiation sector R (the bisectors of the sectors S1 and R forming a straight line, depicted by dot-dash lines), that is to say the approximately straight path of the splitting wave terminates close to the notch 4.
- Figure 5B shows a second favourable position of the notch 4 in a sector S2 centred on the sector R (the bisectors of the sectors S2 and R being coincident), that is to say the path of the splitting wave is initiated close to the notch 4.
- the splitting wave traverses the wafer, passing over the notch 4 but without either terminating in or being initiated at the latter, and causes a process line.
- Figure 4 illustrates this configuration, the visible process line being surrounded by dots. However, the description is not in any way limited to a 0° orientation of the splitting-wave initiation as described above.
- splitting wave may propagate along different directions (with an angular amplitude of around 45°).
- the Applicant has observed that the orientation of the wafer in the implantation machine (to form the weakened zone) has an impact on the control of the splitting-wave initiation.
- a fastening device 5 is used, as shown in Figure 6, to keep the wafer in place.
- the portion of the periphery of the substrate that is held by the fastening device is typically an angular sector of about 90°.
- the fastening device is usually located diametrically opposite to the center of the wheel.
- This device constitutes a thermal contact with the substrate and can therefore remove heat therefrom.
- the angle ⁇ defines the position of the notch 4 relative to the fastening device 5. That portion of the periphery of the wafer in contact with the fastening device 5 during implantation must lie in the splitting initiation sector R, for example in the hot zone of the furnace in the case of thermal splitting.
- the direction of propagation of the splitting wave in the initiation sector is better controlled, and therefore it is possible to ensure that the path of the wave is initiated or terminates in the vicinity of the notch so as to prevent the formation of the process line.
- the notch must be located either in the portion of the wafer in contact with the fastening device or in a sector diametrically opposite to that portion.
- the process comprises the following steps: - fastening the substrate to the implantation wheel such that the notch is located either in a quarter of the periphery of the substrate diametrically opposite the fastening portion or in a quarter of the periphery of the substrate centred on the fastening portion (in the embodiment illustrated in Fig. 6, the notch is located at an angle ⁇ of, respectively, either 270° ⁇ 45° or 90° ⁇ 45°); - carrying out the implantation;
- Figure 7 shows batches of wafers produced, some with an unfavourable orientation of the notch relative to the splitting initiator (series 1 ) and others with a favourable orientation of the notch (series 2).
- the graphic in Figure 7 illustrates the minimum, average and maximum occurrences (expressed as a percentage) of the process line in the two series of batches.
- the average occurrence is reduced by a factor of close to 7.
- a batch of 25 wafers obtained according to the invention has at most three wafers with a process line.
- process lines not associated with the notch may remain on the periphery of the wafer, but these lines are shorter, rarely emergent and therefore less troublesome.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Recrystallisation Techniques (AREA)
- Dicing (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE602008005350T DE602008005350D1 (en) | 2007-10-23 | 2008-10-21 | METHOD FOR SHARING A SUBSTRATE |
CN200880112472.9A CN101836287B (en) | 2007-10-23 | 2008-10-21 | Method of splitting a substrate |
EP08843202A EP2212910B1 (en) | 2007-10-23 | 2008-10-21 | Method of splitting a substrate |
US12/676,320 US8003493B2 (en) | 2007-10-23 | 2008-10-21 | Method of splitting a substrate |
KR1020107007333A KR101490779B1 (en) | 2007-10-23 | 2008-10-21 | Method of splitting a substrate |
JP2010530427A JP5519516B2 (en) | 2007-10-23 | 2008-10-21 | How to divide a board |
AT08843202T ATE500611T1 (en) | 2007-10-23 | 2008-10-21 | METHOD FOR DIVIDING A SUBSTRATE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0758502 | 2007-10-23 | ||
FR0758502A FR2922681A1 (en) | 2007-10-23 | 2007-10-23 | METHOD FOR DETACHING A SUBSTRATE |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009053355A1 true WO2009053355A1 (en) | 2009-04-30 |
Family
ID=39586966
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2008/064200 WO2009053355A1 (en) | 2007-10-23 | 2008-10-21 | Method of splitting a substrate |
Country Status (9)
Country | Link |
---|---|
US (1) | US8003493B2 (en) |
EP (1) | EP2212910B1 (en) |
JP (1) | JP5519516B2 (en) |
KR (1) | KR101490779B1 (en) |
CN (1) | CN101836287B (en) |
AT (1) | ATE500611T1 (en) |
DE (1) | DE602008005350D1 (en) |
FR (1) | FR2922681A1 (en) |
WO (1) | WO2009053355A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8570514B2 (en) * | 2011-06-20 | 2013-10-29 | Kla-Tencor Corporation | Optical system polarizer calibration |
JP6213046B2 (en) | 2013-08-21 | 2017-10-18 | 信越半導体株式会社 | Manufacturing method of bonded wafer |
FR3036845B1 (en) * | 2015-05-28 | 2017-05-26 | Soitec Silicon On Insulator | METHOD FOR TRANSFERRING A LAYER OF A MONOCRYSTALLINE SUBSTRATE |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1331663A1 (en) * | 2002-01-16 | 2003-07-30 | S.O.I.Tec Silicon on Insulator Technologies | Method for cleaving layers of a wafer material |
EP1460691A1 (en) * | 2001-11-27 | 2004-09-22 | Shin-Etsu Handotai Co., Ltd | Method for producing cemented wafer |
US20050217560A1 (en) * | 2004-03-31 | 2005-10-06 | Tolchinsky Peter G | Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3901423A (en) * | 1973-11-26 | 1975-08-26 | Purdue Research Foundation | Method for fracturing crystalline materials |
FR2681472B1 (en) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
JP3352340B2 (en) * | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | Semiconductor substrate and method of manufacturing the same |
FR2725074B1 (en) * | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A THIN SEMI-CONDUCTIVE LAYER ON A SUBSTRATE |
FR2748851B1 (en) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A THIN FILM OF SEMICONDUCTOR MATERIAL |
SG68035A1 (en) * | 1997-03-27 | 1999-10-19 | Canon Kk | Method and apparatus for separating composite member using fluid |
US6162705A (en) * | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
KR100889886B1 (en) | 2003-01-07 | 2009-03-20 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
US7235138B2 (en) | 2003-08-21 | 2007-06-26 | Micron Technology, Inc. | Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces |
-
2007
- 2007-10-23 FR FR0758502A patent/FR2922681A1/en not_active Withdrawn
-
2008
- 2008-10-21 CN CN200880112472.9A patent/CN101836287B/en active Active
- 2008-10-21 KR KR1020107007333A patent/KR101490779B1/en active IP Right Grant
- 2008-10-21 AT AT08843202T patent/ATE500611T1/en not_active IP Right Cessation
- 2008-10-21 EP EP08843202A patent/EP2212910B1/en active Active
- 2008-10-21 WO PCT/EP2008/064200 patent/WO2009053355A1/en active Application Filing
- 2008-10-21 JP JP2010530427A patent/JP5519516B2/en active Active
- 2008-10-21 US US12/676,320 patent/US8003493B2/en active Active
- 2008-10-21 DE DE602008005350T patent/DE602008005350D1/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1460691A1 (en) * | 2001-11-27 | 2004-09-22 | Shin-Etsu Handotai Co., Ltd | Method for producing cemented wafer |
EP1331663A1 (en) * | 2002-01-16 | 2003-07-30 | S.O.I.Tec Silicon on Insulator Technologies | Method for cleaving layers of a wafer material |
US20050217560A1 (en) * | 2004-03-31 | 2005-10-06 | Tolchinsky Peter G | Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
EP2212910A1 (en) | 2010-08-04 |
KR101490779B1 (en) | 2015-02-09 |
US20100176493A1 (en) | 2010-07-15 |
JP5519516B2 (en) | 2014-06-11 |
KR20100072010A (en) | 2010-06-29 |
JP2011501452A (en) | 2011-01-06 |
EP2212910B1 (en) | 2011-03-02 |
US8003493B2 (en) | 2011-08-23 |
FR2922681A1 (en) | 2009-04-24 |
ATE500611T1 (en) | 2011-03-15 |
DE602008005350D1 (en) | 2011-04-14 |
CN101836287B (en) | 2012-12-05 |
CN101836287A (en) | 2010-09-15 |
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