WO2009104668A1 - Wiring board and semiconductor device - Google Patents

Wiring board and semiconductor device Download PDF

Info

Publication number
WO2009104668A1
WO2009104668A1 PCT/JP2009/052862 JP2009052862W WO2009104668A1 WO 2009104668 A1 WO2009104668 A1 WO 2009104668A1 JP 2009052862 W JP2009052862 W JP 2009052862W WO 2009104668 A1 WO2009104668 A1 WO 2009104668A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
resin
insulating layer
pad
low
Prior art date
Application number
PCT/JP2009/052862
Other languages
French (fr)
Japanese (ja)
Inventor
朝夫 村上
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2009554362A priority Critical patent/JP5515744B2/en
Publication of WO2009104668A1 publication Critical patent/WO2009104668A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention is based on the priority claim of Japanese Patent Application No. 2008-040335 (filed on Feb. 21, 2008), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a wiring board and a semiconductor device for mounting a semiconductor package or a semiconductor chip, and more particularly to a wiring board and a semiconductor device suitable for flip chip connection, CSP (Chip Scale Package) connection, and the like.
  • LSI Large Scale Integration
  • connection method used to package this LSI chip is also increased in number of pins. Shifting from wire bonding to flip chip connection to support high-speed signals.
  • the flip chip connection is suitable for increasing the number of pins because an electrode can be provided on the wiring side surface of the LSI chip. Further, the flip-chip connection does not require a lead wire as compared with a connection method such as wire bonding or tape automated bonding, so that the wiring length can be shortened.
  • the bump 130 formed on the electrode 121 of the LSI chip 120 and the mounting pad 112 formed on the wiring substrate 110 are firmly bonded, and then the LSI chip 120 is formed by the underfill resin 140.
  • a method of sealing between the wiring board 110 and the wiring board 110 is widely used (see FIG. 6).
  • Au, solder, or the like is used as a general bump material used for flip chip connection. Examples of solder materials include Sn—Pb eutectic solder, and other examples include Sn—Pb (excluding eutectic), Sn—Ag, Sn—Cu, Sn—Sb, Sn—Zn, Sn.
  • a conductive resin bump is used (see Patent Document 1), or a ball bump in which the metal layer 130 is applied around the resin core 131 is formed with a conductive adhesive. There exists what was joined (refer patent document 2; refer FIG. 7).
  • the possibility of improving the connection reliability is increased by sealing the gap between the LSI chip and the wiring board with an underfill resin for the purpose of relaxing the stress applied to the solder bumps.
  • the elastic modulus of the solder bump is much higher than that of the underfill resin.
  • the elastic modulus of the Sn-3AG-0.5Cu solder is about 40 GPa
  • the elastic modulus of the underfill resin is a filler.
  • the elastic modulus is increased by mixing, it is about 10 GPa. For this reason, stress is still concentrated on the solder bump having a high elastic modulus, and there is a risk that cracks may occur in the LSI circuit in the solder bump itself or in the LSI chip near the solder bump due to repeated temperature changes.
  • a protruding resin is formed on a conductive pad of a printed wiring board, and a metal thin film is formed on the surface of the resin. It is conceivable that the LSI chip and the wiring board are flip-chip connected via solder bumps using the electrode pad portion coated with the. In this case, although the stress applied to the solder bump is relieved by the presence of the resin, the conductive pad itself is fixed on the high-elasticity printed wiring board, so that there is a limit to obtaining a sufficient effect.
  • flip-chip connection is a structure suitable for high performance, so it is expected that demand will increase in the future.
  • problems such as cost reduction and mounting process reduction Remains.
  • the main problem of the present invention is to provide a wiring board and a semiconductor device capable of ensuring high reliability of a bump connection part in flip chip connection, CSP connection, or the like.
  • a wiring board for mounting a semiconductor package or a semiconductor chip wherein the insulating layer has a recess at a predetermined position, and is embedded in the recess, and more than the insulating layer.
  • a low-elasticity low-elasticity resin, and a pad disposed on the low-elasticity resin and having a region smaller than the region of the low-elasticity resin are provided.
  • the wiring board, a semiconductor chip or a semiconductor package having an electrode at a position corresponding to the pad of the wiring board, and the pad and the electrode are disposed. And a bump for electrically connecting the pad and the electrode.
  • the flip chip or CSP As shown in the figure, when the electrodes of the semiconductor chip and the mounting pads of the wiring board face each other and are connected via bumps, even if there is a difference in the thermal expansion coefficient between the semiconductor chip and the wiring board, the connection part is on the low elastic resin As a result, the mounting pad can absorb the stress due to the difference in coefficient of linear expansion between the semiconductor chip and the wiring board. This stress relaxation effect is effective not only in preventing the destruction of the bumps but also in preventing the occurrence of cracks in the semiconductor chip and the wiring board.
  • FIG. 1A is a cross-sectional view taken along a line XX and FIG. 2B is a plan view schematically showing the configuration of a part of a wiring board according to a first embodiment of the present invention; It is sectional drawing which showed typically the structure of a part of semiconductor device which mounted the semiconductor chip in the wiring board based on Example 1 of this invention. It is process sectional drawing which showed typically the manufacturing method of the wiring board which concerns on Example 1 of this invention. It is the top view which showed the structure of a part of wiring board which concerns on Example 2 of this invention.
  • FIG. 6 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 1.
  • FIG. 10 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 2.
  • an insulating layer having a recess at a predetermined position (13 in FIG. 2), and embedded in the recess, is less elastic than the insulating layer (13 in FIG. 2).
  • 12 the following forms are also possible. It is preferable that a metal layer provided at least on the bottom surface of the recess is provided in the insulating layer. It is preferable to provide wiring formed on the insulating layer and the low-elasticity resin and connected to the pad.
  • An outer peripheral portion made of the same material as the pad is disposed on the insulating layer in the outer periphery of the low elastic resin region, and between the mounting pad and the outer peripheral portion in the low elastic resin region. And one or a plurality of connection portions that are made of the same material as the pad and connect the mounting pad and the outer peripheral portion. It is preferable to provide wiring formed on the insulating layer and connected to the outer peripheral portion.
  • the connecting portion is preferably formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
  • the semiconductor device includes a bump.
  • FIG. 1 is a perspective view schematically showing a partial configuration of a wiring board according to the first embodiment of the present invention.
  • 2A and 2B are a cross-sectional view taken along a line XX ′ and a plan view of FIG. 2B schematically showing a partial configuration of the wiring board according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view schematically showing a partial configuration of the semiconductor device in which the semiconductor chip is mounted on the wiring board according to the first embodiment of the present invention.
  • a wiring layer (not shown) is formed in an insulating layer 13, and a mounting pad 12 and a wiring 12 a are formed at predetermined positions on the surface of the insulating layer 13. It is a multilayer wiring board.
  • the wiring board 10 is not limited to a printed wiring board, and can be applied to other wiring boards such as a ceramic board.
  • the wiring board 10 includes an insulating layer 13, a low elastic resin 11, a mounting pad 12, and a metal layer 14 as main components.
  • the insulating layer 13 has a wiring layer (not shown) and a metal layer 14 formed therein, and a mounting pad 12 and a wiring 12a are formed at predetermined positions on the surface.
  • the insulating layer 13 is formed with a bottomed hole (corresponding to 13a in FIG. 4B) in the layer between the metal layer 14 and the mounting pad 12, and has a lower elasticity than the insulating layer 13 in the hole.
  • An elastic resin 11 is embedded.
  • the hole in the insulating layer 13 is formed to be a larger area than the area of the mounting pad 12.
  • an epoxy resin for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide Resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like can be used.
  • the low elastic resin 11 is an insulating resin having a lower elasticity than the insulating layer 13, and is embedded in a hole (corresponding to 13a in FIG. 4B) formed in the insulating layer 13.
  • the low elastic resin 11 is an area larger than the area of the mounting pad 12.
  • a mounting pad 12 is formed in the region of the surface of the low elastic resin 11.
  • the low elastic resin 11 can be a resin whose elastic modulus is kept low in the apparatus operating temperature range.
  • a silicone resin, a composite resin obtained by adding a thermoplastic component to an epoxy resin, a low melt viscosity epoxy resin, or the like can be used. Can be used.
  • the mounting pad 12 is a pad for mounting the semiconductor chip 20 via the bump 30 and is joined to the bump 30 (see FIG. 3).
  • the mounting pad 12 is formed in the region of the surface of the low elastic resin 11. As a result, the joint between the mounting pad 12 and the bump 30 floats on the low-elasticity resin 11, and the stress due to the difference in linear expansion coefficient between the semiconductor chip 20 and the insulating layer 13 can be relaxed.
  • the mounting pad 12 has a wiring 12a drawn out from the outer periphery, and is configured integrally with the wiring 12a.
  • the wiring 12 a is formed on the insulating layer 13 and the low elastic resin 11.
  • the metal layer 14 is a layer made of metal formed in the insulating layer 13.
  • the metal layer 14 can be formed at the same time as a wiring layer (not shown) formed in the insulating layer 13, and the same material (for example, copper) as the wiring layer can be used.
  • the metal layer 14 serves as an etching stopper (laser stopper) when forming a hole (corresponding to 13a in FIG. 4B) for embedding the low-elasticity resin 11 in the insulating layer 13.
  • the semiconductor chip 20 is a semiconductor component such as an LSI chip and has an electrode 21 on the surface on the wiring board 10 side (see FIG. 3).
  • the electrode 21 is electrically connected to the mounting pad 12 via the bump 30 and is bonded to the bump 30.
  • a semiconductor package may be mounted on the wiring board 10 instead of the semiconductor chip 20.
  • the bumps 30 are conductive members that electrically connect the electrodes 21 of the semiconductor chip 20 and the mounting pads 12 of the wiring board 10 (see FIG. 3).
  • a general material used for flip chip connection can be used for the bump 30, and for example, Au, solder, or the like can be used.
  • FIG. 4 is a process cross-sectional view schematically showing the method for manufacturing a wiring board according to the first embodiment of the present invention.
  • a printed wiring board will be described as an example of the wiring board 10.
  • the wiring board 10 in which no wiring exists in the outermost layer is formed by a known printed wiring board forming method (step A1; see FIG. 4A).
  • a pattern of the metal layer 14 in a region larger than the region of the mounting pad 12 is formed in the insulating layer 13 around the position of the mounting pad (12 in FIG. 4D).
  • the metal layer 14 serves as a laser stopper that is necessary when forming a hole (13a in FIG. 4C) for embedding the low-elasticity resin (11 in FIG. 4C) in step A2.
  • the pattern of the metal layer 14 may be the same shape as the planar shape of the mounting pad (12 in FIG. 4D), and is not limited to a circle but may be various shapes such as a square shape. Further, the pattern of the metal layer 14 is made larger than the region of the hole 13a in consideration of the positional deviation at the time of laser drilling.
  • a hole 13a is formed by a laser (not shown) so as to be an area larger than the area of the mounting pad 12 around the position of the mounting pad (12 in FIG. 4D) (step A2; (See FIG. 4B).
  • a laser a carbon dioxide laser, an excimer laser, or the like can be used. Laser drilling stops at the pattern of the metal layer 14, and a hole 13a having a certain depth can be obtained.
  • a laser method is shown here, but the method is not limited to this method, and the hole 13a can be formed by a photographic technique using a photosensitive material as the insulating layer 13. Various construction methods can be used.
  • a desired resin is filled in the hole (13a in FIG. 4B) by a printing method using a squeegee, and stored in a heating furnace for a predetermined time, and the resin is cured to form a low-elasticity resin 11.
  • the hole filling method is not limited to a printing method, and it is sufficient that a desired resin can be formed in the hole 13a.
  • the mounting pad 12 and the wiring 12a are formed on the insulating layer 13 and the low elastic resin 11 by a known circuit forming method (step A4; see FIG. 4D). At this time, the mounting pad 12 is formed in the region of the low elastic resin 11. That is, the entire mounting pad 12 is formed on the low-elasticity resin 11 except for the extracted wiring 12a.
  • solder resist is formed at a desired position by a known solder resist forming method as necessary.
  • the wiring substrate 10 similar to that of FIG. 1 can be obtained.
  • bumps 30 are formed on the electrodes 21 of the semiconductor chip 20, and then a known flip chip is formed.
  • the connection method the mounting pads 12 and the bumps 30 of the wiring board 10 are bonded. Since the wiring board 10 has a structure that relieves stress, the material of the bump 30 is not particularly limited, and a conventionally used solder bump or the like can be used.
  • a flip-chip connection form is shown here, a form such as CSP (Chip Scale Package), BGA (Ball Grid Arrey), or a bare chip may be used depending on the electronic component to be mounted, and is not particularly limited. .
  • CSP Chip Scale Package
  • BGA Ball Grid Arrey
  • bare chip may be used depending on the electronic component to be mounted, and is not particularly limited.
  • the mounting pad 12 is formed in the region of the low elastic resin 11, it is possible to create a state where the mounting pad 12 is floating on the low elastic resin 11. Therefore, even if the material of the bump 30 formed on the electrode 21 of the semiconductor device 20 is a conventional high-elasticity solder, the stress generated by the difference in thermal expansion between the semiconductor device 20 and the wiring board 10 is absorbed by the low-elasticity resin 11. And can be relaxed.
  • This stress relaxation effect has an effect of preventing not only the destruction of the bumps 30 but also the occurrence of cracks in the semiconductor device 20 and the wiring substrate 10. As a result, it is possible to provide a highly reliable connection structure for a semiconductor device having a fragile insulating layer such as an ASIC for high end which will be developed in the future.
  • FIG. 5 is a plan view showing a partial configuration of the wiring board according to the second embodiment of the present invention.
  • the mounting pads (12 in FIG. 2; excluding the wiring 12a) are arranged in the region of the low elastic resin (11 in FIG. 2).
  • the mounting pads are mounted in the region of the low elastic resin 11.
  • the pad 12, the outer peripheral part 12b, and the connection part 12c are arranged.
  • Other configurations are the same as those of the first embodiment.
  • a mounting pad 12, a wiring 12a, an outer peripheral part 12b, and a connection part 12c made of a conductor (for example, copper) are integrally arranged.
  • the mounting pad 12 is disposed in the center, and a connection portion 12c for connecting the mounting pad 12 and the outer peripheral portion 12b is disposed in a part of the region between the mounting pad 12 and the outer peripheral portion 12b.
  • An outer peripheral portion 12 b is disposed on the insulating layer 13 on the outer periphery of the region of the low elastic resin 11.
  • the outer peripheral part 12b is arrange
  • the planar shape of the portion where the low-elasticity resin 11 is exposed is, for example, C-shaped (see FIG. 5A), arch-shaped (see FIG. 5B), or wedge-shaped (see FIG. 5C). Can be.
  • C-shape see FIG. 5A
  • arch type see FIG. 5B
  • wedge type windmill type; see FIG.
  • connection portions 12c there are four connection portions 12c, and the width of the connection portion 12c changes.
  • the planar shape of the portion where the low-elasticity resin 11 is exposed is not limited to the pattern of FIG. 5, and the shape and the number of connections can be freely combined according to the effect.
  • the connecting portion 12c can be formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
  • the mounting pad 12 on the low elastic resin 11 is stressed by dividing the mounting pad 12 and the outer peripheral portion 12b and connecting the mounting pad 12 and the outer peripheral portion 12b with one or a plurality of connection portions 12c. It becomes easier to follow the physical movement when buffering.
  • connection parts 12c even if buffering in a certain direction is achieved, even if the connection part 12c loaded in that direction breaks, the other connection parts 12c can be electrically connected. As a result, connection reliability can be improved.

Abstract

High reliability of a bump connecting section is ensured for flip-chip connection, CSP connection and the like. A wiring board is provided with an insulating layer having a recessed section at a prescribed position; a low-elasticity resin which is embedded in the recessed section and has an elasticity lower than that of the insulating layer; a pad which is for a region smaller than that of the low elasticity resin and is arranged on the low elasticity resin; a metal layer which is arranged at last on the bottom surface of the recessed section in the insulating layer; and wiring which is formed on the insulating layer and the low elasticity resin and connected to the pad.

Description

配線基板及び半導体装置Wiring substrate and semiconductor device
［関連出願の記載］
　本発明は、日本国特許出願：特願２００８－０４０３３５号（２００８年２月２１日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
　本発明は、半導体パッケージ又は半導体チップを実装するための配線基板及び半導体装置に関し、特に、フリップチップ接続、ＣＳＰ（Chip Scale Package）接続等に適した配線基板及び半導体装置に関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese Patent Application No. 2008-040335 (filed on Feb. 21, 2008), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a wiring board and a semiconductor device for mounting a semiconductor package or a semiconductor chip, and more particularly to a wiring board and a semiconductor device suitable for flip chip connection, CSP (Chip Scale Package) connection, and the like.
　近年、電子機器の高性能化、多機能化を支えるＬＳＩ（Large Scale Integration）チップは多ピン化が進行しており、このＬＳＩチップをパッケージ化するために用いられる接続手法も、多ピン化、高速信号に対応できるようにワイヤボンディングからフリップチップ接続へと移行している。フリップチップ接続は、ＬＳＩチップの配線側の面に電極を設けることができるため、多ピン化に適している。また、フリップチップ接続は、ワイヤボンディングやテープオートメイティッドボンディングのような接続手法と比較し、引き出し線を必要としないため、配線長の短縮化が可能である。 In recent years, LSI (Large Scale Integration) chips that support higher performance and multi-functionality of electronic devices have been increased in number of pins, and the connection method used to package this LSI chip is also increased in number of pins. Shifting from wire bonding to flip chip connection to support high-speed signals. The flip chip connection is suitable for increasing the number of pins because an electrode can be provided on the wiring side surface of the LSI chip. Further, the flip-chip connection does not require a lead wire as compared with a connection method such as wire bonding or tape automated bonding, so that the wiring length can be shortened.
　フリップチップ接続のプロセスとしては、ＬＳＩチップ１２０の電極１２１上に形成されたバンプ１３０と配線基板１１０上に形成された実装パッド１１２とを強固に接合し、その後、アンダーフィル樹脂１４０によりＬＳＩチップ１２０と配線基板１１０の間を封止する手法が広く用いられている（図６参照）。フリップチップ接続に使用される一般的なバンプの材料には、Ａｕやはんだ等が用いられている。はんだの材料の例として、Ｓｎ－Ｐｂ共晶はんだがあり、それ以外にも、例えば、Ｓｎ－Ｐｂ（共晶を除く）、Ｓｎ－Ａｇ、Ｓｎ－Ｃｕ、Ｓｎ－Ｓｂ、Ｓｎ－Ｚｎ、Ｓｎ－Ｂｉ、及びこれらの材料に特定の添加元素をさらに加えた材料を挙げることができ、これらを適宜用いることができる。また、他のバンプの材質の例として、例えば、導電性樹脂バンプを使用したもの（特許文献１参照）や、樹脂コア１３１の周囲に金属層１３０が施されたボールバンプを導電性接着剤で接合したもの（特許文献２参照；図７参照）等がある。 As a flip chip connection process, the bump 130 formed on the electrode 121 of the LSI chip 120 and the mounting pad 112 formed on the wiring substrate 110 are firmly bonded, and then the LSI chip 120 is formed by the underfill resin 140. A method of sealing between the wiring board 110 and the wiring board 110 is widely used (see FIG. 6). Au, solder, or the like is used as a general bump material used for flip chip connection. Examples of solder materials include Sn—Pb eutectic solder, and other examples include Sn—Pb (excluding eutectic), Sn—Ag, Sn—Cu, Sn—Sb, Sn—Zn, Sn. -Bi and materials obtained by further adding specific additive elements to these materials can be given, and these can be used as appropriate. As another example of the material of the bump, for example, a conductive resin bump is used (see Patent Document 1), or a ball bump in which the metal layer 130 is applied around the resin core 131 is formed with a conductive adhesive. There exists what was joined (refer patent document 2; refer FIG. 7).
　一方、フリップチップ接続されるＬＳＩチップの多くは、ＬＳＩチップ－配線基板間の熱膨張差による応力を緩和するため、ＬＳＩチップと配線基板の間の隙間を樹脂封止することにより、接続信頼性を確保する必要がある。樹脂封止する例は、特許文献３等で開示されている。 On the other hand, in many LSI chips that are flip-chip connected, in order to relieve stress due to the difference in thermal expansion between the LSI chip and the wiring board, the connection reliability is improved by sealing the gap between the LSI chip and the wiring board. It is necessary to ensure. An example of resin sealing is disclosed in Patent Document 3 and the like.
特開２０００－３３２０５３号公報JP 2000-332053 A 特開平１０－１７３００６号公報JP 10-173006 A 特開平１１－２３３５５８号公報Japanese Patent Laid-Open No. 11-233558 特開２００４－１１１７５３号公報JP 2004-111753 A
　なお、上記特許文献１－４の全開示内容はその引用をもって本書に繰込み記載する。以下の分析は、本発明によって与えられたものである。
　バンプを用いた従来技術において、ＬＳＩチップ－配線基板間がはんだバンプを介してフリップチップ接続される場合、弾性率が高いはんだバンプは、ＬＳＩチップ－配線基板間の熱膨張差により高い応力が発生し、はんだバンプ自身又ははんだバンプ近傍のＬＳＩチップにおけるＬＳＩ回路を破壊するおそれがある。特に、ハイエンド向け大型ＡＳＩＣ（Application Specific Integrated Circuit）を中心にＬＳＩチップにおける絶縁層のＬｏｗ－ｋ（低誘電率）化によるＬＳＩ回路の脆弱化が進行しており、特に、応力によるＬＳＩ回路の破壊が顕著になっている。 Note that the entire disclosure of Patent Documents 1-4 is incorporated herein by reference. The following analysis is given by the present invention.
In the conventional technology using bumps, when the LSI chip and the wiring board are flip-chip connected via the solder bump, the solder bump having a high elastic modulus generates a high stress due to the difference in thermal expansion between the LSI chip and the wiring board. However, the LSI circuit in the solder bump itself or the LSI chip near the solder bump may be destroyed. In particular, LSI circuits are becoming weaker due to low-k (low dielectric constant) insulation layers in LSI chips, especially large-scale ASICs (Application Specific Integrated Circuits) for high-end applications. Has become prominent.
　そこで、はんだバンプにかかる応力を緩和する目的でＬＳＩチップと配線基板の隙間をアンダーフィル樹脂で封止することで接続信頼性を向上させる可能性は高くなる。ところが、はんだバンプの弾性率はアンダーフィル樹脂と比較してはるかに高く、例えば、Ｓｎ－３ＡＧ－０．５Ｃｕはんだの弾性率は約４０ＧＰａであるのに対し、アンダーフィル樹脂の弾性率は充填剤を混入して高弾性率化した場合でも１０ＧＰａ程度である。このため、弾性率の高いはんだバンプに依然として応力が集中して、繰返しの温度変化等により、はんだバンプ自身又ははんだバンプ近傍のＬＳＩチップにおけるＬＳＩ回路にクラックが発生するおそれがある。 Therefore, the possibility of improving the connection reliability is increased by sealing the gap between the LSI chip and the wiring board with an underfill resin for the purpose of relaxing the stress applied to the solder bumps. However, the elastic modulus of the solder bump is much higher than that of the underfill resin. For example, the elastic modulus of the Sn-3AG-0.5Cu solder is about 40 GPa, whereas the elastic modulus of the underfill resin is a filler. Even in the case where the elastic modulus is increased by mixing, it is about 10 GPa. For this reason, stress is still concentrated on the solder bump having a high elastic modulus, and there is a risk that cracks may occur in the LSI circuit in the solder bump itself or in the LSI chip near the solder bump due to repeated temperature changes.
　そこで、バンプの弾性率を下げる試みとして、例えば、特許文献１に記載の導電性樹脂バンプを用いて、ＬＳＩチップと配線基板をフリップチップ接続することが考えられる。この場合、導電性樹脂を使用することにより、はんだバンプに比較し低弾性化を図ることが可能となる。ところが、この手法では、導電性樹脂に重量比で８０ｗｔ％（重量％）の多量の金属粒子を添加して、導電性を確保しているため、この多量の金属粒子の影響でバンプ自体の弾性率が上昇し、バンプ材質の低弾性化の効果が小さくなる。例を挙げると、エポキシ樹脂自身の弾性率は２ＧＰａ程度であっても、この従来例のように金属フィラーを多量に混入した場合、導電性樹脂としての弾性率は、１０ＧＰａ程度まで上昇してしまう。 Thus, as an attempt to lower the elastic modulus of the bump, for example, it is conceivable to use an electrically conductive resin bump described in Patent Document 1 to flip-chip connect the LSI chip and the wiring board. In this case, by using a conductive resin, it is possible to achieve low elasticity compared to solder bumps. However, in this method, since a large amount of metal particles of 80 wt% (weight%) is added to the conductive resin to ensure conductivity, the elasticity of the bump itself is affected by the large amount of metal particles. The rate increases, and the effect of reducing the elasticity of the bump material is reduced. For example, even if the elastic modulus of the epoxy resin itself is about 2 GPa, when a large amount of metal filler is mixed as in this conventional example, the elastic modulus as a conductive resin increases to about 10 GPa. .
　また、バンプの低弾性化に代わる接続部の低応力化の試みとして、特許文献４のように、プリント配線基板の導電性パッド上に突起状の樹脂を形成し、その樹脂の表面に金属薄膜を被覆した電極パッド部を用いて、はんだバンプを介してＬＳＩチップと配線基板をフリップチップ接続することが考えられる。この場合、樹脂が存在することによりはんだバンプにかかる応力は緩和されるが、導電性パッド自体は高弾性なプリント配線基板上に固定されているため、十分な効果を得るには限界がある。 Further, as an attempt to reduce the stress of the connecting portion instead of reducing the elasticity of the bump, as in Patent Document 4, a protruding resin is formed on a conductive pad of a printed wiring board, and a metal thin film is formed on the surface of the resin. It is conceivable that the LSI chip and the wiring board are flip-chip connected via solder bumps using the electrode pad portion coated with the. In this case, although the stress applied to the solder bump is relieved by the presence of the resin, the conductive pad itself is fixed on the high-elasticity printed wiring board, so that there is a limit to obtaining a sufficient effect.
　以上述べたように、フリップチップ接続は、高性能化に適した構造であるため、将来的に需要増が見込まれるが、高信頼性を確保するとともに、低コスト化、実装工程削減等の課題が残っている。 As mentioned above, flip-chip connection is a structure suitable for high performance, so it is expected that demand will increase in the future. However, while securing high reliability, problems such as cost reduction and mounting process reduction Remains.
　本発明の主な課題は、フリップチップ接続やＣＳＰ接続等においてバンプ接続部の高信頼性を確保することができる配線基板及び半導体装置を提供することである。 The main problem of the present invention is to provide a wiring board and a semiconductor device capable of ensuring high reliability of a bump connection part in flip chip connection, CSP connection, or the like.
　本発明の第１の視点においては、半導体パッケージ又は半導体チップを実装するための配線基板であって、所定の位置に凹部を有する絶縁層と、前記凹部内に埋め込まれるとともに、前記絶縁層よりも低弾性な低弾性樹脂と、前記低弾性樹脂上に配設されるとともに、前記低弾性樹脂の領域よりも小さい領域のパッドと、を備えることを特徴とする。 According to a first aspect of the present invention, there is provided a wiring board for mounting a semiconductor package or a semiconductor chip, wherein the insulating layer has a recess at a predetermined position, and is embedded in the recess, and more than the insulating layer. A low-elasticity low-elasticity resin, and a pad disposed on the low-elasticity resin and having a region smaller than the region of the low-elasticity resin are provided.
　本発明の第２の視点においては、半導体装置において、前記配線基板と、前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、を備えることを特徴とする。 In a second aspect of the present invention, in the semiconductor device, the wiring board, a semiconductor chip or a semiconductor package having an electrode at a position corresponding to the pad of the wiring board, and the pad and the electrode are disposed. And a bump for electrically connecting the pad and the electrode.
　本発明によれば、絶縁層上の実装パッドの下には実装パッドの領域よりも大きな領域の低弾性樹脂が存在し、低弾性樹脂が絶縁層よりも低弾性であるため、フリップチップやＣＳＰのように、半導体チップの電極と配線基板の実装パッドが向かい合ってバンプを介して接続する場合、半導体チップと配線基板の熱膨張係数の差がある場合でも、接続部は低弾性樹脂の上に浮いた構造となり、実装パッドが半導体チップと配線基板との間の線膨張係数差による応力を吸収することが可能になる。この応力緩和効果は、バンプの破壊防止のみでなく、半導体チップや配線基板のクラックの発生を防止する効果がある。 According to the present invention, since the low elastic resin in a region larger than the region of the mounting pad exists below the mounting pad on the insulating layer, and the low elastic resin has lower elasticity than the insulating layer, the flip chip or CSP As shown in the figure, when the electrodes of the semiconductor chip and the mounting pads of the wiring board face each other and are connected via bumps, even if there is a difference in the thermal expansion coefficient between the semiconductor chip and the wiring board, the connection part is on the low elastic resin As a result, the mounting pad can absorb the stress due to the difference in coefficient of linear expansion between the semiconductor chip and the wiring board. This stress relaxation effect is effective not only in preventing the destruction of the bumps but also in preventing the occurrence of cracks in the semiconductor chip and the wiring board.
本発明の実施例１に係る配線基板の一部の構成を模式的に示した斜視図である。It is the perspective view which showed typically the one part structure of the wiring board based on Example 1 of this invention. 本発明の実施例１に係る配線基板の一部の構成を模式的に示した（Ａ）Ｘ－Ｘ間の断面図、（Ｂ）平面図である。1A is a cross-sectional view taken along a line XX and FIG. 2B is a plan view schematically showing the configuration of a part of a wiring board according to a first embodiment of the present invention; 本発明の実施例１に係る配線基板に半導体チップを実装した半導体装置の一部の構成を模式的に示した断面図である。It is sectional drawing which showed typically the structure of a part of semiconductor device which mounted the semiconductor chip in the wiring board based on Example 1 of this invention. 本発明の実施例１に係る配線基板の製造方法を模式的に示した工程断面図である。It is process sectional drawing which showed typically the manufacturing method of the wiring board which concerns on Example 1 of this invention. 本発明の実施例２に係る配線基板の一部の構成を示した平面図である。It is the top view which showed the structure of a part of wiring board which concerns on Example 2 of this invention. 従来例１に係る半導体装置の一部の構成を模式的に示した断面図である。FIG. 6 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 1. 従来例２に係る半導体装置の一部の構成を模式的に示した断面図である。FIG. 10 is a cross-sectional view schematically showing a partial configuration of a semiconductor device according to Conventional Example 2.
符号の説明Explanation of symbols
　１０、１１０　配線基板
　１１　低弾性樹脂
　１２、１１２　実装パッド（パッド）
　１２ａ、１１２ａ　配線
　１２ｂ　外周部
　１２ｃ　結線部
　１３、１１３　絶縁層（基板）
　１３ａ　穴
　１４　金属層
　２０、１２０　半導体チップ（ＬＳＩチップ）
　２１、１２１　電極
　３０、１３０　バンプ（金属層）
　１３１　樹脂コア
　１４０　アンダーフィル樹脂 10, 110 Wiring board 11 Low elastic resin 12, 112 Mounting pad (pad)
12a, 112a Wiring 12b Outer peripheral part 12c Connection part 13, 113 Insulating layer (substrate)
13a hole 14 metal layer 20, 120 semiconductor chip (LSI chip)
21, 121 Electrode 30, 130 Bump (metal layer)
131 Resin core 140 Underfill resin
　本発明の実施形態に係る配線基板では、所定の位置に凹部を有する絶縁層（図２の１３）と、前記凹部内に埋め込まれるとともに、前記絶縁層（図２の１３）よりも低弾性な低弾性樹脂（図２の１１）と、前記低弾性樹脂（図２の１１）上に配設されるとともに、前記低弾性樹脂（図２の１１）の領域よりも小さい領域のパッド（図２の１２）と、を備える。
　さらに、以下の形態も可能である。
　前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることが好ましい。
　前記絶縁層及び前記低弾性樹脂上に形成されるとともに、前記パッドと接続された配線を備えることが好ましい。
　前記低弾性樹脂の領域の外周の前記絶縁層上に配設されるとともに、前記パッドと同一材料よりなる外周部と、前記低弾性樹脂の領域内であって前記実装パッドと前記外周部の間の領域の一部に配設されるとともに、前記パッドと同一材料よりなり、かつ、前記実装パッドと前記外周部を結線する１又は複数の結線部と、を備えることが好ましい。
　前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることが好ましい。
　前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることが好ましい。
　前記配線基板と、前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、を備える半導体装置とすることが好ましい。 In the wiring board according to the embodiment of the present invention, an insulating layer having a recess at a predetermined position (13 in FIG. 2), and embedded in the recess, is less elastic than the insulating layer (13 in FIG. 2). A low-elasticity resin (11 in FIG. 2) and a pad (FIG. 2) that is disposed on the low-elasticity resin (11 in FIG. 2) and is smaller than the region of the low-elasticity resin (11 in FIG. 2). And 12).
Furthermore, the following forms are also possible.
It is preferable that a metal layer provided at least on the bottom surface of the recess is provided in the insulating layer.
It is preferable to provide wiring formed on the insulating layer and the low-elasticity resin and connected to the pad.
An outer peripheral portion made of the same material as the pad is disposed on the insulating layer in the outer periphery of the low elastic resin region, and between the mounting pad and the outer peripheral portion in the low elastic resin region. And one or a plurality of connection portions that are made of the same material as the pad and connect the mounting pad and the outer peripheral portion.
It is preferable to provide wiring formed on the insulating layer and connected to the outer peripheral portion.
The connecting portion is preferably formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
The wiring board, a semiconductor chip or a semiconductor package having electrodes at positions corresponding to the pads of the wiring board, and disposed between the pads and the electrodes, and electrically connect the pads and the electrodes. Preferably, the semiconductor device includes a bump.
　本発明の実施例１に係る配線基板について図面を用いて説明する。図１は、本発明の実施例１に係る配線基板の一部の構成を模式的に示した斜視図である。図２は、本発明の実施例１に係る配線基板の一部の構成を模式的に示した（Ａ）Ｘ－Ｘ´間の断面図、（Ｂ）平面図である。図３は、本発明の実施例１に係る配線基板に半導体チップを実装した半導体装置の一部の構成を模式的に示した断面図である。 The wiring board according to Example 1 of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view schematically showing a partial configuration of a wiring board according to the first embodiment of the present invention. 2A and 2B are a cross-sectional view taken along a line XX ′ and a plan view of FIG. 2B schematically showing a partial configuration of the wiring board according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view schematically showing a partial configuration of the semiconductor device in which the semiconductor chip is mounted on the wiring board according to the first embodiment of the present invention.
　図１及び図２を参照すると、配線基板１０は、絶縁層１３中に配線層（図示せず）が形成され、絶縁層１３の表面の所定の位置に実装パッド１２及び配線１２ａが形成された多層配線基板である。配線基板１０は、プリント配線基板に限定されるわけではなく、セラミック基板等の他の配線基板への適用も可能である。配線基板１０は、主な構成部として、絶縁層１３と、低弾性樹脂１１と、実装パッド１２と、金属層１４と、を有する。 Referring to FIGS. 1 and 2, in the wiring substrate 10, a wiring layer (not shown) is formed in an insulating layer 13, and a mounting pad 12 and a wiring 12 a are formed at predetermined positions on the surface of the insulating layer 13. It is a multilayer wiring board. The wiring board 10 is not limited to a printed wiring board, and can be applied to other wiring boards such as a ceramic board. The wiring board 10 includes an insulating layer 13, a low elastic resin 11, a mounting pad 12, and a metal layer 14 as main components.
　絶縁層１３は、内部に配線層（図示せず）及び金属層１４が形成されており、表面の所定の位置に実装パッド１２及び配線１２ａが形成されている。絶縁層１３は、金属層１４と実装パッド１２の間の層に有底の穴（図４（Ｂ）の１３ａに相当）が形成されており、当該穴内に絶縁層１３よりも低弾性な低弾性樹脂１１が埋め込まれている。絶縁層１３の穴は、実装パッド１２の領域よりも大きな領域となるように形成されている。絶縁層１３の材料には、例えば、絶縁性の有機材料又は無機材料が用いられ、プリント配線基板の場合には、例えば、エポキシ樹脂、エポキシアクリレート樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、フェノール樹脂、ポリイミド樹脂、ＢＣＢ（Benzocyclobutene）、ＰＢＯ（Polybenzoxazole）及びポリノルボルネン樹脂等を用いることができる。 The insulating layer 13 has a wiring layer (not shown) and a metal layer 14 formed therein, and a mounting pad 12 and a wiring 12a are formed at predetermined positions on the surface. The insulating layer 13 is formed with a bottomed hole (corresponding to 13a in FIG. 4B) in the layer between the metal layer 14 and the mounting pad 12, and has a lower elasticity than the insulating layer 13 in the hole. An elastic resin 11 is embedded. The hole in the insulating layer 13 is formed to be a larger area than the area of the mounting pad 12. As the material of the insulating layer 13, for example, an insulating organic material or an inorganic material is used. In the case of a printed wiring board, for example, an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide Resin, BCB (Benzocyclobutene), PBO (Polybenzoxazole), polynorbornene resin, and the like can be used.
　低弾性樹脂１１は、絶縁層１３よりも低弾性な絶縁樹脂であり、絶縁層１３に形成された穴（図４（Ｂ）の１３ａに相当）内に埋め込まれている。低弾性樹脂１１は、実装パッド１２の領域よりも大きな領域となっている。低弾性樹脂１１の表面の領域内には、実装パッド１２が形成されている。低弾性樹脂１１には、装置使用温度範囲において弾性率が低く保たれる樹脂を用いることができ、例えば、シリコーン樹脂、エポキシ樹脂に熱可塑性分を加えたコンポジット樹脂、低溶融粘度エポキシ樹脂等を用いることができる。 The low elastic resin 11 is an insulating resin having a lower elasticity than the insulating layer 13, and is embedded in a hole (corresponding to 13a in FIG. 4B) formed in the insulating layer 13. The low elastic resin 11 is an area larger than the area of the mounting pad 12. A mounting pad 12 is formed in the region of the surface of the low elastic resin 11. The low elastic resin 11 can be a resin whose elastic modulus is kept low in the apparatus operating temperature range. For example, a silicone resin, a composite resin obtained by adding a thermoplastic component to an epoxy resin, a low melt viscosity epoxy resin, or the like can be used. Can be used.
　実装パッド１２は、バンプ３０を介して半導体チップ２０を実装するためのパッドであり、バンプ３０と接合している（図３参照）。実装パッド１２は、低弾性樹脂１１の表面の領域内に形成されている。これにより、実装パッド１２とバンプ３０の接合部は、低弾性樹脂１１上に浮いた状態となり、半導体チップ２０と絶縁層１３との間の線膨張係数差による応力を緩和することが可能となる。実装パッド１２は、外周から配線１２ａが引き出されており、配線１２ａと一体に構成されている。配線１２ａは、絶縁層１３及び低弾性樹脂１１上に形成されている。 The mounting pad 12 is a pad for mounting the semiconductor chip 20 via the bump 30 and is joined to the bump 30 (see FIG. 3). The mounting pad 12 is formed in the region of the surface of the low elastic resin 11. As a result, the joint between the mounting pad 12 and the bump 30 floats on the low-elasticity resin 11, and the stress due to the difference in linear expansion coefficient between the semiconductor chip 20 and the insulating layer 13 can be relaxed. . The mounting pad 12 has a wiring 12a drawn out from the outer periphery, and is configured integrally with the wiring 12a. The wiring 12 a is formed on the insulating layer 13 and the low elastic resin 11.
　金属層１４は、絶縁層１３中に形成された金属よりなる層である。金属層１４は、絶縁層１３内に形成された配線層（図示せず）と同時に形成することができ、配線層と同一な材料（例えば、銅）を用いることができる。金属層１４は、絶縁層１３に低弾性樹脂１１を埋め込むための穴（図４（Ｂ）の１３ａに相当）を形成する際のエッチングストッパ（レーザストッパ）としての役割を果たす。 The metal layer 14 is a layer made of metal formed in the insulating layer 13. The metal layer 14 can be formed at the same time as a wiring layer (not shown) formed in the insulating layer 13, and the same material (for example, copper) as the wiring layer can be used. The metal layer 14 serves as an etching stopper (laser stopper) when forming a hole (corresponding to 13a in FIG. 4B) for embedding the low-elasticity resin 11 in the insulating layer 13.
　半導体チップ２０は、ＬＳＩチップ等の半導体部品であり、配線基板１０側の面に電極２１を有する（図３参照）。電極２１は、バンプ３０を介して実装パッド１２と電気的に接続されており、バンプ３０と接合している。なお、半導体チップ２０の代わりに、半導体パッケージを配線基板１０に実装するようにしてもよい。 The semiconductor chip 20 is a semiconductor component such as an LSI chip and has an electrode 21 on the surface on the wiring board 10 side (see FIG. 3). The electrode 21 is electrically connected to the mounting pad 12 via the bump 30 and is bonded to the bump 30. Note that a semiconductor package may be mounted on the wiring board 10 instead of the semiconductor chip 20.
　バンプ３０は、半導体チップ２０の電極２１と配線基板１０の実装パッド１２とを電気的に接続する導電部材である（図３参照）。バンプ３０には、フリップチップ接続に使用される一般的な材料を用いることができ、例えば、Ａｕやはんだ等を用いることができる。 The bumps 30 are conductive members that electrically connect the electrodes 21 of the semiconductor chip 20 and the mounting pads 12 of the wiring board 10 (see FIG. 3). A general material used for flip chip connection can be used for the bump 30, and for example, Au, solder, or the like can be used.
　次に、本発明の実施例１に係る配線基板の製造方法について図面を用いて説明する。図４は、本発明の実施例１に係る配線基板の製造方法を模式的に示した工程断面図である。なお、ここでは、配線基板１０としてプリント配線基板を例に説明する。 Next, a method for manufacturing a wiring board according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a process cross-sectional view schematically showing the method for manufacturing a wiring board according to the first embodiment of the present invention. Here, a printed wiring board will be described as an example of the wiring board 10.
　まず、公知のプリント配線基板形成方法により、最外層に配線が存在しない状態の配線基板１０を形成する（ステップＡ１；図４（Ａ）参照）。このとき、絶縁層１３中には実装パッド（図４（Ｄ）の１２）の位置を中心に、実装パッド１２の領域よりも大きな領域の金属層１４のパターンを形成する。 First, the wiring board 10 in which no wiring exists in the outermost layer is formed by a known printed wiring board forming method (step A1; see FIG. 4A). At this time, a pattern of the metal layer 14 in a region larger than the region of the mounting pad 12 is formed in the insulating layer 13 around the position of the mounting pad (12 in FIG. 4D).
　なお、金属層１４は、ステップＡ２において低弾性樹脂（図４（Ｃ）の１１）を埋め込むための穴（図４（Ｃ）の１３ａ）を形成する際に必要となるレーザストッパの役割を果たす。また、金属層１４のパターンは、実装パッド（図４（Ｄ）の１２）の平面形状と同様な形状としてもよく、円形に限らず、四角形状等の各種形状としてもよい。また、金属層１４のパターンは、レーザ穴あけの際の位置ずれを考慮して、穴１３ａの領域よりも大きくする。 The metal layer 14 serves as a laser stopper that is necessary when forming a hole (13a in FIG. 4C) for embedding the low-elasticity resin (11 in FIG. 4C) in step A2. . Further, the pattern of the metal layer 14 may be the same shape as the planar shape of the mounting pad (12 in FIG. 4D), and is not limited to a circle but may be various shapes such as a square shape. Further, the pattern of the metal layer 14 is made larger than the region of the hole 13a in consideration of the positional deviation at the time of laser drilling.
　次に、レーザ（図示せず）により、実装パッド（図４（Ｄ）の１２）の位置を中心に、実装パッド１２の領域よりも大きな領域となるように穴１３ａを形成する（ステップＡ２；図４（Ｂ）参照）。レーザとしては、炭酸ガスレーザ、エキシマレーザ等を用いることができる。レーザ穴あけは、金属層１４のパターンまでで止まり、一定の深さの穴１３ａを得ることができる。また、穴１３ａに関して、ここではレーザによる工法を示しているが、本工法に限ったものではなく、絶縁層１３として感光性材料を用い、写真技術により穴１３ａを形成することも可能であり、各種工法を使用することが可能である。 Next, a hole 13a is formed by a laser (not shown) so as to be an area larger than the area of the mounting pad 12 around the position of the mounting pad (12 in FIG. 4D) (step A2; (See FIG. 4B). As the laser, a carbon dioxide laser, an excimer laser, or the like can be used. Laser drilling stops at the pattern of the metal layer 14, and a hole 13a having a certain depth can be obtained. Further, regarding the hole 13a, a laser method is shown here, but the method is not limited to this method, and the hole 13a can be formed by a photographic technique using a photosensitive material as the insulating layer 13. Various construction methods can be used.
　次に、スキージを使用した刷り込み工法により、穴（図４（Ｂ）の１３ａ）内に所望の樹脂を埋め、加熱炉に所定時間保管し、樹脂を硬化して、低弾性樹脂１１を形成する（ステップＡ３；図４（Ｃ）参照）。なお、穴埋め工法としては、印刷による工法に限定されるものではなく、穴１３ａ内に所望の樹脂を形成できればよい。 Next, a desired resin is filled in the hole (13a in FIG. 4B) by a printing method using a squeegee, and stored in a heating furnace for a predetermined time, and the resin is cured to form a low-elasticity resin 11. (Step A3; see FIG. 4C). Note that the hole filling method is not limited to a printing method, and it is sufficient that a desired resin can be formed in the hole 13a.
　次に、公知の回路形成工法により、絶縁層１３及び低弾性樹脂１１上に実装パッド１２及び配線１２ａを形成する（ステップＡ４；図４（Ｄ）参照）。このとき、実装パッド１２は、低弾性樹脂１１の領域内に形成する。すなわち、引き出された配線１２ａを除いて実装パッド１２の全体が、低弾性樹脂１１上に形成された構成とする。 Next, the mounting pad 12 and the wiring 12a are formed on the insulating layer 13 and the low elastic resin 11 by a known circuit forming method (step A4; see FIG. 4D). At this time, the mounting pad 12 is formed in the region of the low elastic resin 11. That is, the entire mounting pad 12 is formed on the low-elasticity resin 11 except for the extracted wiring 12a.
　最後に、図示は省略するが、必要に応じて公知のソルダーレジスト形成方法により、所望の位置にソルダーレジストを形成する。 Finally, although not shown, a solder resist is formed at a desired position by a known solder resist forming method as necessary.
　以上のステップにより、図１と同様な配線基板１０ができるが、図３と同様な半導体装置を得るためには、半導体チップ２０の電極２１上にバンプ３０を形成し、その後、公知のフリップチップ接続工法により、配線基板１０の実装パッド１２とバンプ３０を接合することになる。なお、配線基板１０は応力を緩和する構造を持つため、バンプ３０の材料は特に限定されることはなく、従来から使用されているはんだバンプ等を用いることができる。 Through the above steps, the wiring substrate 10 similar to that of FIG. 1 can be obtained. However, in order to obtain a semiconductor device similar to that of FIG. 3, bumps 30 are formed on the electrodes 21 of the semiconductor chip 20, and then a known flip chip is formed. By the connection method, the mounting pads 12 and the bumps 30 of the wiring board 10 are bonded. Since the wiring board 10 has a structure that relieves stress, the material of the bump 30 is not particularly limited, and a conventionally used solder bump or the like can be used.
　なお、ここではフリップチップ接続の形態を示しているが、実装する電子部品に応じてＣＳＰ（Chip Scale Package）、ＢＧＡ（Ball Grid Arrey）、ベアチップ等の形態でもよく、特に限定されるものではない。 Although a flip-chip connection form is shown here, a form such as CSP (Chip Scale Package), BGA (Ball Grid Arrey), or a bare chip may be used depending on the electronic component to be mounted, and is not particularly limited. .
　実施例１によれば、低弾性樹脂１１の領域内に実装パッド１２が形成されているので、実装パッド１２が低弾性樹脂１１上に浮いている状態を作ることができる。そのため、半導体装置２０の電極２１上に形成されるバンプ３０の材質が従来の高弾性のはんだであっても、半導体装置２０と配線基板１０の熱膨張差により生じる応力を低弾性樹脂１１で吸収して緩和することができる。この応力緩和効果は、バンプ３０の破壊防止のみでなく、半導体装置２０や配線基板１０のクラックの発生も防止する効果がある。この結果、今後の進展するハイエンド向けＡＳＩＣ等の脆弱な絶縁層を持つ半導体装置に対しても信頼性の高い接続構造を提供することができる。 According to the first embodiment, since the mounting pad 12 is formed in the region of the low elastic resin 11, it is possible to create a state where the mounting pad 12 is floating on the low elastic resin 11. Therefore, even if the material of the bump 30 formed on the electrode 21 of the semiconductor device 20 is a conventional high-elasticity solder, the stress generated by the difference in thermal expansion between the semiconductor device 20 and the wiring board 10 is absorbed by the low-elasticity resin 11. And can be relaxed. This stress relaxation effect has an effect of preventing not only the destruction of the bumps 30 but also the occurrence of cracks in the semiconductor device 20 and the wiring substrate 10. As a result, it is possible to provide a highly reliable connection structure for a semiconductor device having a fragile insulating layer such as an ASIC for high end which will be developed in the future.
　本発明の実施例２に係る配線基板について図面を用いて説明する。図５は、本発明の実施例２に係る配線基板の一部の構成を示した平面図である。 A wiring board according to Example 2 of the present invention will be described with reference to the drawings. FIG. 5 is a plan view showing a partial configuration of the wiring board according to the second embodiment of the present invention.
　実施例１では低弾性樹脂（図２の１１）の領域内に実装パッド（図２の１２；配線１２ａを除く）が配置されているが、実施例２では低弾性樹脂１１の領域内に実装パッド１２、外周部１２ｂ、結線部１２ｃを配置したものである。その他の構成は、実施例１と同様である。 In the first embodiment, the mounting pads (12 in FIG. 2; excluding the wiring 12a) are arranged in the region of the low elastic resin (11 in FIG. 2). In the second embodiment, the mounting pads are mounted in the region of the low elastic resin 11. The pad 12, the outer peripheral part 12b, and the connection part 12c are arranged. Other configurations are the same as those of the first embodiment.
　絶縁層１３及び低弾性樹脂１１上には、導電体（例えば、銅）よりなる実装パッド１２、配線１２ａ、外周部１２ｂ、及び結線部１２ｃが一体となって配置されている。低弾性樹脂１１の領域内には、実装パッド１２、及び結線部１２ｃのみが配置されている。低弾性樹脂１１の領域内では、中央に実装パッド１２が配置され、実装パッド１２と外周部１２ｂの間の領域の一部に実装パッド１２と外周部１２ｂを結線する結線部１２ｃが配置されている。低弾性樹脂１１の領域の外周の絶縁層１３上には、外周部１２ｂが配置されている。外周部１２ｂは、低弾性樹脂１１を囲むように配置されており、外周側で配線１２ａと接続され、内周側で結線部１２ｃと接続されている。 On the insulating layer 13 and the low-elasticity resin 11, a mounting pad 12, a wiring 12a, an outer peripheral part 12b, and a connection part 12c made of a conductor (for example, copper) are integrally arranged. In the region of the low elastic resin 11, only the mounting pad 12 and the connection part 12c are arranged. In the region of the low elastic resin 11, the mounting pad 12 is disposed in the center, and a connection portion 12c for connecting the mounting pad 12 and the outer peripheral portion 12b is disposed in a part of the region between the mounting pad 12 and the outer peripheral portion 12b. Yes. An outer peripheral portion 12 b is disposed on the insulating layer 13 on the outer periphery of the region of the low elastic resin 11. The outer peripheral part 12b is arrange | positioned so that the low elastic resin 11 may be enclosed, is connected with the wiring 12a on the outer peripheral side, and is connected with the connection part 12c on the inner peripheral side.
　実装パッド１２、外周部１２ｂ、及び結線部１２ｃで囲まれた領域には、導電体が配置されておらず、低弾性樹脂１１の一部が露出している。低弾性樹脂１１が露出している部分の平面形状は、例えば、Ｃ字型（図５（Ａ）参照）、アーチ型（図５（Ｂ）参照）、楔型（図５（Ｃ）参照）にすることができる。Ｃ字型（図５（Ａ）参照）では、結線部１２ｃが１箇所あり、結線部１２ｃの幅が一定である。アーチ型（図５（Ｂ）参照）では、結線部１２ｃが４箇所あり、結線部１２ｃの幅が一定である。楔型（風車型；図５（Ｃ）参照）では、結線部１２ｃが４箇所あり、結線部１２ｃの幅が変化している。低弾性樹脂１１が露出している部分の平面形状は、図５のパターンに限定されるわけではなく、形状、結線数共に、その効果に合わせて自由に組み合わせることが可能である。結線部１２ｃは、直線状、曲線状、斜線状、又はこれらの組合せで形成することができる。 In the region surrounded by the mounting pad 12, the outer peripheral portion 12b, and the connection portion 12c, no conductor is disposed, and a part of the low elastic resin 11 is exposed. The planar shape of the portion where the low-elasticity resin 11 is exposed is, for example, C-shaped (see FIG. 5A), arch-shaped (see FIG. 5B), or wedge-shaped (see FIG. 5C). Can be. In the C-shape (see FIG. 5A), there is one connection portion 12c, and the width of the connection portion 12c is constant. In the arch type (see FIG. 5B), there are four connection portions 12c, and the width of the connection portion 12c is constant. In the wedge type (windmill type; see FIG. 5C), there are four connection portions 12c, and the width of the connection portion 12c changes. The planar shape of the portion where the low-elasticity resin 11 is exposed is not limited to the pattern of FIG. 5, and the shape and the number of connections can be freely combined according to the effect. The connecting portion 12c can be formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
　実施例２によれば、実装パッド１２と外周部１２ｂに分け、１又は複数の結線部１２ｃで実装パッド１２と外周部１２ｂを接続することにより、低弾性樹脂１１上の実装パッド２が応力を緩衝する際の物理的な動きに追従しやすくなる。また、結線部１２ｃが複数個所あれば、ある方向での緩衝を達成した場合に、その方向にて負荷のかかった結線部１２ｃが断線したとしても、他の結線部１２ｃで電気的な接続を継続することが可能となり、結果的に接続信頼性を向上させることができる。 According to the second embodiment, the mounting pad 12 on the low elastic resin 11 is stressed by dividing the mounting pad 12 and the outer peripheral portion 12b and connecting the mounting pad 12 and the outer peripheral portion 12b with one or a plurality of connection portions 12c. It becomes easier to follow the physical movement when buffering. In addition, if there are a plurality of connection parts 12c, even if buffering in a certain direction is achieved, even if the connection part 12c loaded in that direction breaks, the other connection parts 12c can be electrically connected. As a result, connection reliability can be improved.
　本発明は、上記実施形態を基に説明したが、上記実施形態に限定されることなく、本発明の範囲内において種々の変更、変形、改良等を含むことはいうまでもない。また、本発明の範囲内において、開示した要素の多様な組み合わせ、置換ないし選択が可能である。 Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment and includes various changes, modifications, improvements and the like within the scope of the present invention. Further, various combinations, substitutions or selections of the disclosed elements are possible within the scope of the present invention.
　本発明のさらなる課題・目的及び展開形態は、特許請求の範囲を含む本発明の全開示事項からも明らかにされる。 Further problems / objects and development forms of the present invention will be made clear from the entire disclosure of the present invention including the claims.

Claims (7)

  1. 　所定の位置に凹部を有する絶縁層と、
    　前記凹部内に埋め込まれるとともに、前記絶縁層よりも低弾性な低弾性樹脂と、
    　前記低弾性樹脂上に配設されるとともに、前記低弾性樹脂の領域よりも小さい領域のパッドと、
    を備えることを特徴とする配線基板。     An insulating layer having a recess at a predetermined position;
    A low-elasticity resin embedded in the recess and having a lower elasticity than the insulating layer;
    A pad in a region smaller than the region of the low elastic resin, disposed on the low elastic resin,
    A wiring board comprising:
  2. 　前記絶縁層中に配設されるとともに、少なくとも前記凹部の底面に配された金属層を備えることを特徴とする請求項１記載の配線基板。 The wiring board according to claim 1, further comprising a metal layer disposed in the insulating layer and disposed at least on a bottom surface of the recess.
  3. 　前記絶縁層及び前記低弾性樹脂上に形成されるとともに、前記パッドと接続された配線を備えることを特徴とする請求項１又は２記載の配線基板。 3. The wiring board according to claim 1, further comprising a wiring formed on the insulating layer and the low-elasticity resin and connected to the pad.
  4. 　前記低弾性樹脂の領域の外周の前記絶縁層上に配設されるとともに、前記パッドと同一材料よりなる外周部と、
    　前記低弾性樹脂の領域内であって前記実装パッドと前記外周部の間の領域の一部に配設されるとともに、前記パッドと同一材料よりなり、かつ、前記実装パッドと前記外周部を結線する１又は複数の結線部と、
    を備えることを特徴とする請求項１又は２記載の配線基板。     The outer peripheral portion made of the same material as the pad, and disposed on the insulating layer in the outer periphery of the low elastic resin region,
    It is disposed in a part of the region between the mounting pad and the outer peripheral portion within the region of the low elastic resin, and is made of the same material as the pad, and connects the mounting pad and the outer peripheral portion. One or more connecting parts to
    The wiring board according to claim 1, further comprising:
  5. 　前記絶縁層上に形成されるとともに、前記外周部と接続された配線を備えることを特徴とする請求項４記載の配線基板。 The wiring board according to claim 4, further comprising a wiring formed on the insulating layer and connected to the outer peripheral portion.
  6. 　前記結線部は、直線状、曲線状、斜線状、又はこれらの組合せで形成されていることを特徴とする請求項４又は５記載の配線基板。 The wiring board according to claim 4 or 5, wherein the connection portion is formed in a straight line shape, a curved line shape, a diagonal line shape, or a combination thereof.
  7. 　請求項１乃至６のいずれか一に記載の配線基板と、
    　前記配線基板のパッドと対応する位置に電極を有する半導体チップ又は半導体パッケージと、
    　前記パッドと前記電極の間に配設されるとともに、前記パッドと前記電極を電気的に接続するバンプと、
    を備えることを特徴とする半導体装置。     The wiring board according to any one of claims 1 to 6,
    A semiconductor chip or a semiconductor package having electrodes at positions corresponding to the pads of the wiring board;
    A bump disposed between the pad and the electrode and electrically connecting the pad and the electrode;
    A semiconductor device comprising:
PCT/JP2009/052862 2008-02-21 2009-02-19 Wiring board and semiconductor device WO2009104668A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009554362A JP5515744B2 (en) 2008-02-21 2009-02-19 Wiring substrate and semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-040335 2008-02-21
JP2008040335 2008-02-21

Publications (1)

Publication Number Publication Date
WO2009104668A1 true WO2009104668A1 (en) 2009-08-27

Family

ID=40985546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/052862 WO2009104668A1 (en) 2008-02-21 2009-02-19 Wiring board and semiconductor device

Country Status (2)

Country Link
JP (1) JP5515744B2 (en)
WO (1) WO2009104668A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012126852A1 (en) * 2011-03-21 2012-09-27 Osram Opto Semiconductors Gmbh Connection carrier for semiconductor chips and semiconductor component
WO2012078709A3 (en) * 2010-12-08 2012-10-18 Tessera, Inc. Compliant interconnects in wafers
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277923A (en) * 1999-03-29 2000-10-06 Nec Corp Motherboard printed wiring board and its manufacture
JP2004247549A (en) * 2003-02-14 2004-09-02 Fujitsu Ltd Manufacturing method of wiring board and multi-layer wiring board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001094227A (en) * 1999-09-20 2001-04-06 Shinko Electric Ind Co Ltd Semiconductor chip mounting wiring board and semiconductor chip mounting method using the board
JP2003198068A (en) * 2001-12-27 2003-07-11 Nec Corp Printed board, semiconductor device, electrical connection structure of printed board and component

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277923A (en) * 1999-03-29 2000-10-06 Nec Corp Motherboard printed wiring board and its manufacture
JP2004247549A (en) * 2003-02-14 2004-09-02 Fujitsu Ltd Manufacturing method of wiring board and multi-layer wiring board

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
CN103339725A (en) * 2010-12-08 2013-10-02 德塞拉股份有限公司 Compliant interconnects in wafers
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
JP2014504451A (en) * 2010-12-08 2014-02-20 テッセラ，インコーポレイテッド Compliant interconnect on wafer
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
KR20130129404A (en) * 2010-12-08 2013-11-28 테세라, 인코포레이티드 Compliant interconnects in wafers
WO2012078709A3 (en) * 2010-12-08 2012-10-18 Tessera, Inc. Compliant interconnects in wafers
US9159658B2 (en) 2011-03-21 2015-10-13 Osram Opto Semiconductors Gmbh Connection carrier for semiconductor chips and semiconductor component
WO2012126852A1 (en) * 2011-03-21 2012-09-27 Osram Opto Semiconductors Gmbh Connection carrier for semiconductor chips and semiconductor component
JP2014510413A (en) * 2011-03-21 2014-04-24 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Connection support for semiconductor chip and semiconductor element

Also Published As

Publication number Publication date
JPWO2009104668A1 (en) 2011-06-23
JP5515744B2 (en) 2014-06-11

Similar Documents

Publication Publication Date Title
JP5515744B2 (en) Wiring substrate and semiconductor device
JP4899406B2 (en) Flip chip type semiconductor device
KR101376264B1 (en) Stacked package and method for manufacturing the package
JP2008071953A (en) Semiconductor device
US8378482B2 (en) Wiring board
JP2001177010A (en) Wiring board, semiconductor device having wiring board and manufacturing method thereof and packaging method
JP2003051568A (en) Semiconductor device
JP2009064812A (en) Electrode structure in semiconductor device and related technology thereof
US20120205802A1 (en) Printed circuit board and flip chip package using the same with improved bump joint reliability
JP2005129663A (en) Multilayer circuit board
WO2015198837A1 (en) Semiconductor device and manufacturing method therefor
JP5015065B2 (en) Wiring board
JP2009026861A (en) Semiconductor device and manufacturing method thereof
JP2007250712A (en) Semiconductor device and method of manufacturing same
JP2006024842A (en) Semiconductor device
JP5375186B2 (en) WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE
JP2004128290A (en) Semiconductor device
JP6464762B2 (en) Semiconductor package substrate, semiconductor package, semiconductor package substrate manufacturing method, and semiconductor package manufacturing method
JP2006278771A (en) Semiconductor device and manufacturing method thereof
JP4321269B2 (en) Semiconductor device
JP2002289735A (en) Semiconductor device
JP2007227608A (en) Semiconductor device and method of manufacturing semiconductor device
JP5000621B2 (en) Semiconductor device
JP4830493B2 (en) Semiconductor device, mounting structure thereof, and mounting method thereof
JP5434306B2 (en) Semiconductor device and manufacturing method of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09713225

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009554362

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09713225

Country of ref document: EP

Kind code of ref document: A1