WO2009108438A3 - Semiconductor constructions, and methods of forming semiconductor constructions - Google Patents

Semiconductor constructions, and methods of forming semiconductor constructions Download PDF

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Publication number
WO2009108438A3
WO2009108438A3 PCT/US2009/032119 US2009032119W WO2009108438A3 WO 2009108438 A3 WO2009108438 A3 WO 2009108438A3 US 2009032119 W US2009032119 W US 2009032119W WO 2009108438 A3 WO2009108438 A3 WO 2009108438A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor constructions
oxide
over
methods
forming
Prior art date
Application number
PCT/US2009/032119
Other languages
French (fr)
Other versions
WO2009108438A2 (en
Inventor
Russell A. Benson
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020107020964A priority Critical patent/KR101115180B1/en
Priority to EP09715046A priority patent/EP2248171A4/en
Priority to CN2009801061917A priority patent/CN101952963B/en
Publication of WO2009108438A2 publication Critical patent/WO2009108438A2/en
Publication of WO2009108438A3 publication Critical patent/WO2009108438A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials.
PCT/US2009/032119 2008-02-26 2009-01-27 Semiconductor constructions, and methods of forming semiconductor constructions WO2009108438A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020107020964A KR101115180B1 (en) 2008-02-26 2009-01-27 Semiconductor constructions, and methods of forming semiconductor constructions
EP09715046A EP2248171A4 (en) 2008-02-26 2009-01-27 Semiconductor constructions, and methods of forming semiconductor constructions
CN2009801061917A CN101952963B (en) 2008-02-26 2009-01-27 Semiconductor constructions, and methods of forming semiconductor constructions

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/037,560 US7700469B2 (en) 2008-02-26 2008-02-26 Methods of forming semiconductor constructions
US12/037,560 2008-02-26

Publications (2)

Publication Number Publication Date
WO2009108438A2 WO2009108438A2 (en) 2009-09-03
WO2009108438A3 true WO2009108438A3 (en) 2009-10-29

Family

ID=40997448

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/032119 WO2009108438A2 (en) 2008-02-26 2009-01-27 Semiconductor constructions, and methods of forming semiconductor constructions

Country Status (6)

Country Link
US (2) US7700469B2 (en)
EP (1) EP2248171A4 (en)
KR (1) KR101115180B1 (en)
CN (1) CN101952963B (en)
TW (1) TWI402915B (en)
WO (1) WO2009108438A2 (en)

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KR101934093B1 (en) * 2012-08-29 2019-01-02 삼성전자주식회사 Semiconductor device and method for manufacturing the same
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Also Published As

Publication number Publication date
TW200945442A (en) 2009-11-01
US20090212338A1 (en) 2009-08-27
TWI402915B (en) 2013-07-21
EP2248171A2 (en) 2010-11-10
KR101115180B1 (en) 2012-02-24
KR20100120303A (en) 2010-11-15
CN101952963B (en) 2012-05-30
EP2248171A4 (en) 2012-09-12
WO2009108438A2 (en) 2009-09-03
US7919863B2 (en) 2011-04-05
US7700469B2 (en) 2010-04-20
CN101952963A (en) 2011-01-19
US20100155892A1 (en) 2010-06-24

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