WO2009130648A1 - Semiconductor devices including a field reducing structure and methods of manufacture thereof - Google Patents

Semiconductor devices including a field reducing structure and methods of manufacture thereof Download PDF

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Publication number
WO2009130648A1
WO2009130648A1 PCT/IB2009/051605 IB2009051605W WO2009130648A1 WO 2009130648 A1 WO2009130648 A1 WO 2009130648A1 IB 2009051605 W IB2009051605 W IB 2009051605W WO 2009130648 A1 WO2009130648 A1 WO 2009130648A1
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Prior art keywords
region
trench
reducing structure
conductivity type
extends
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PCT/IB2009/051605
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French (fr)
Inventor
Steffen Holland
Fabian Jachmann
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Nxp B.V.
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Publication of WO2009130648A1 publication Critical patent/WO2009130648A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66128—Planar diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to semiconductor devices which include a field reducing structure which acts as a field plate and the manufacture of such devices. For example, it concerns trenched Schottky diodes and field effect power transistors.
  • the present invention concerns Schottky rectifiers with trenched electrodes, as disclosed in US-A-5612567, for example. The whole contents thereof are hereby incorporated as reference material. It is also directed at trench-gate field effect transistors in which a field plate is provided in the trench below the gate electrode and is connected to it. A device of this form is disclosed for example in International Publication no. WO-A-01/08226 (our ref. PHN 17572) and US-A-5637898. The whole contents of both documents are hereby incorporated as reference material.
  • the present invention provides a semiconductor device comprising a semiconductor body having a first region of a first conductivity type; and a peak field reducing structure which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region, wherein the first region is more highly doped in a portion adjoining the field reducing structure than in another portion further from the field reducing structure.
  • a doping gradient may be introduced such that the dopant concentration in a marginal portion of the first region adjacent to the field reducing structure increases towards the field reducing structure.
  • the more highly doped portion of the first region serves to reduce the peak of the electric field adjacent to the field reducing structure of a RESURF device.
  • Introduction of additional dopant is a process that is readily controllable and adjustable by the device designer to improve the characteristics of a device.
  • the field reducing structure is in the form of an insulated electrode provided in the trench which extends into the first region of the semiconductor body.
  • a lateral doping gradient may be introduced which leads to a maximum doping concentration in the first region adjacent to the walls of the trench and a minimum in the centre of the device cell.
  • the first region may be a drift region of a Schottky diode which is contacted by an electrode that forms a Schottky barrier with the drift region.
  • the device is a trenched pn diode in which the semiconductor body includes a second region of a second, opposite conductivity type over the first region, the first and second regions defining a junction therebetween, wherein the trench extends through the second region into the first region.
  • the device is in the form of a RESURF trench-gate transistor including a third region of the first conductivity type, such that the first, second and third regions form a drain, channel- accommodating and source region, respectively, with the channel- accommodating region separating the source and drain regions adjacent the trenched electrode and the trenched electrode also acting as a gate.
  • the additional doping is localised adjacent to the lower regions of the trench sidewalls.
  • the more highly doped portion of the first region may extend at least over the bottom third of the extent of the sidewalls of the trench within the first region. In some cases, the more highly doped portion may extend over the full length of the sidewalls of the trench in the first region.
  • Embodiments of the invention may have a lateral device configuration.
  • Such a device may include a layer of insulating material over a semiconductor substrate of either conductivity type, wherein the first region is provided on the insulating layer, and the insulating layer and substrate together form the field reducing structure.
  • the device may be in the form of a lateral pn diode or transistor.
  • the semiconductor substrate and the overlying insulating layer effectively act as a field plate in this arrangement.
  • the present invention further provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
  • the present invention also provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
  • the present invention still further provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
  • Figure 1 is a cross-sectional view of a Schottky rectifier with a trenched electrode according to a first embodiment of the invention
  • Figures 2 and 3 are graphs showing potential lines in a simulation of a known device configuration and a configuration embodying the present invention, respectively;
  • Figure 4 shows a graph representing electric field profiles in the vertical direction along the trench wall of a known device and a device embodying the invention;
  • Figure 5 is a graph indicating the change of ionization rate with depth for a known device and a device embodying the invention
  • Figure 6 is a cross-sectional side view of a trench pn diode according to a second embodiment of the invention
  • Figure 7 is a cross-sectional side view of a RESURF trench-gate transistor according to a third embodiment of the invention.
  • Figure 8 is a cross-sectional side view of a lateral RESURF device according to a fourth embodiment of the invention.
  • Figure 9 is a cross-sectional side view of trenches in a semiconductor body according to a first method embodying the invention;
  • Figure 10 is a cross-sectional side view of trenches in a semiconductor body according to a second method embodying the invention.
  • Figures 11 and 12 are cross-sectional side views of a semiconductor body at successive states in the manufacture of a device according to a third method embodying the invention.
  • Figures 13 and 14 are cross-sectional side views of a semiconductor body at successive stages in the manufacture of a device according to a fourth method embodying the invention.
  • Figure 1 is a cross-sectional view of a Schottky barrier diode embodying the present invention. It includes vertical field plates in the form of trenched electrodes 2 formed of doped polysilicon. They extend into respective trenches 4 formed in the drift region 6 of the semiconductor body 8 of the device. The drift region 6 overlies a more highly doped cathode region 10.
  • a cathode electrode 12 is provided in contact with the cathode region at the bottom major surface 8b of the semiconductor body.
  • Anode electrode 14 comprises a metal and/or metal suicide that forms a Schottky barrier with the drift region 6 and contacts this region at the top major surface 8a.
  • the anode electrode 14 is electrically connected to the trench electrode 2.
  • a layer of insulating material 16 is provided between each trenched electrode and the semiconductor body 8.
  • Localised more highly doped regions 18 are provided along each sidewall of the trenches 4. They are of the same conductivity type as the remainder of the drift region 6 and, in the embodiment illustrated, these regions extend for the full length of the trench in the semiconductor body. It is preferable for this region to extend at least over the bottom third of the trench sidewalls.
  • the bulk of the drift region 6 is doped n-type at a concentration of 1x10 16 atoms/cm 3 , and the region 18 up to a maximum concentration of around 1x10 17 atoms/cm 3 .
  • the region 18 is around 0.1 micron thick and increases the breakdown voltage by about 11 % in comparison to an equivalent device in which this additional doping is not included.
  • the highest electric field concentrations tend to be found at the wall of the trench close to its lower end. Under blocking conditions, potential lines are squeezed at this location resulting in high electrical fields.
  • FIG. 2 represents a known configuration
  • Figure 3 represents a device embodying the invention which includes a region of additional doping alongside the trench wall. It can be seen that the crowding of potential lines at the corner of the trench is partially suppressed in Figure 3.
  • reverse bias can be increased by about 11 % beyond the point where breakdown is reached in the configuration of Figure 2.
  • the lower resistivity of the drift region around the trench in the device of Figure 3 embodying the invention supports current flow at the edges of the RESURF cell, which lowers the forward voltage drop significantly. For example, in the simulations of Figure 2 and Figure 3, the forward voltage drop is 18% lower in the device of Figure 3.
  • RESURF devices Due to a large parameter space, the whole potential of this technology is likely to be even higher.
  • the design of RESURF devices offers several geometrical and also material related degrees of freedom for optimization. Examples include trench depth and separation as well as oxide thickness, but also the kind if dielectric material used (e.g. silicon oxide, or silicon nitride) and doping concentrations.
  • Figures 4 and 5 show simulations of the electric field profile and ionization rates in the vertical direction alongside the trench wall of a device configuration shown in Figures 2 and 3.
  • the solid lines represent data from the Figure 2 configuration and dotted lines correspond to a device embodying the invention as simulated in Figure 3.
  • the ionization rate for the device embodying the invention at the trench bottom is essentially zero under the same conditions.
  • a trench pn-diode embodying the invention is shown in Figure 6. It primarily differs from the diode configuration of Figure 1 in that a p-type anode region 20 is formed between the trenches adjacent to top major surface 8a of the device. It forms a pn junction 22 with the drift region 6.
  • a further device configuration embodying the invention is shown in
  • Figure 7 It shows a cross-sectional side view through a RESURF trenchFET.
  • source and drain regions 30, 32 respectively, of a first conductivity type (n-type in this example) are separated by a channel-accommodating body region 34 of the opposite, second conductivity type (that is p-type in this example).
  • a gate electrode 36 is present in a trench 38 which extends through the regions 30 and 34 into an underlying portion of the drain region 40. The electrode extends deep into the drift region to form a field plate 42.
  • An insulating layer 44 separates the electrode 36 from the semiconductor body and its thickness is increased around the field plate 42.
  • Regions 46 of additional dopant are provided along the sidewalls of the trench 38 in the drift region.
  • An example of a lateral RESURF device embodying the invention is shown in Figure 8.
  • a conductive substrate 50 is covered by a thick insulating layer 52 (layer 52 may be referred to as "the BOX region").
  • Region 52 is in turn covered by a doped epitaxial layer 54.
  • Layer 52 may typically be in the form of an oxide.
  • a drift region 56 (n-type in this example) is formed in layer 54 and forms a pn junction with an anode region 58 of the opposite conductivity type (p-type in this example).
  • a more highly doped region 60 of the first conductivity type is adjacent to the top surface 62 of the epitaxial layer 54 and forms a cathode region.
  • the conductive substrate 50 effectively acts as a field plate dielecthcally coupled to the epitaxial layer 54 by the insulating layer 52.
  • Substrate 50 and layer 52 together form a peak field reducing structure which extends adjacent to the epitaxial layer 54.
  • a marginal region 64 of the drift region 56 which borders the insulating layer 52 is more highly doped than the drift region 56 in accordance with the invention. As with other configurations described herein, it serves to increase the breakdown voltage of the device and reduce its forward voltage drop.
  • Embodiments of the form depicted in Figure 8 may be manufactured in various ways. For example, during growth of the buried oxide layer 52, a thin semiconductor layer may remain on top. This layer will have the relatively high doping concentration of the substrate 50 and form the region 64. An n- doped layer can then be grown epitaxially over region 64 in which other features of the device are then formed. Optionally, prior to growth of the n- doped layer, a shallow implantation process may be carried to further increase the doping level in region 64. Alternatively, the vertical doping profile above buried layer 52 may be closely controlled during epitaxial growth of the overlying semiconductor material.
  • an alternative method involves depositing a highly doped layer of polycrystalline semiconductor material on the walls of the trench and then heating to cause out-diffusion of the dopant from the polycrystalline layer into the semiconductor body 8 to form the additional regions 18.
  • Layer 70 is then removed before forming the field plate insulating layer over the walls of the trench.
  • Figures 11 and 12 show successive stages according to a further process for forming the regions of additional doping.
  • a dopant is implanted deep into the semiconductor body at locations corresponding to the intended trench positions.
  • the substrate is then heated to out-diffuse the dopant to form regions 80 shown in Figure 11.
  • the trenches 4 are etched into the semiconductor body such that they extend into regions 80 as shown in Figure 12, to form the additional regions 18. With this approach, the additional regions may be restricted to the lower portion of the trenches.
  • Successive stages of a further approach are shown in Figures 13 and
  • Partial trenches 90 are etched initially and then the base of the trench is doped to form regions 92.
  • the semiconductor body is heated to out-diffuse the regions 92 and the trenches etched to their full depth such that they extend into the out-diffuse regions to form the additional regions 18.

Abstract

The configuration and manufacture of various RESURF semiconductor devices are described. The devices comprise a semiconductor body (8) having first region (6, 18; 40, 46; 56, 64) of a first conductivity type and a peak field reducing structure (2, 16; 42, 44; 50, 52) which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region. The first region is more highly doped in a portion (18, 46, 64) adjoining the field reducing structure than in another portion further from the field reducing structure. The more highly doped portion of the first region serves to reduce the peak of the electric field adjacent to the field reducing structure of the RESURF device. The device may be in the form of a Schottky diode, a trenched pn-diode, a trenchFET, or a lateral configuration for example.

Description

DESCRIPTION
SEMICONDUCTOR DEVICES INCLUDING A FIELD REDUCING STRUCTURE AND METHODS OF MANUFACTURE THEREOF
The present invention relates to semiconductor devices which include a field reducing structure which acts as a field plate and the manufacture of such devices. For example, it concerns trenched Schottky diodes and field effect power transistors.
The design of many semiconductor devices involves a trade-off between breakdown voltage and forward voltage drop. Within a first order of approximation, the quotient of these two values remains substantially constant. This is often referred to as "the silicon limit". A significant breakthrough in this field was the development of reduced surface field technology ("RESURF") which enables reduction of the electric field, for example at a pn junction or a Schottky barrier, by the introduction of lateral, or vertical field plates. An early article describing the RESURF principle is "Thin Layer High-voltage Devices (RESURF devices)" by J A Appels et al, Philips Journal of Research, Vol. 35 No. 1 , 1980, pages 1 to 3.
The present invention concerns Schottky rectifiers with trenched electrodes, as disclosed in US-A-5612567, for example. The whole contents thereof are hereby incorporated as reference material. It is also directed at trench-gate field effect transistors in which a field plate is provided in the trench below the gate electrode and is connected to it. A device of this form is disclosed for example in International Publication no. WO-A-01/08226 (our ref. PHN 17572) and US-A-5637898. The whole contents of both documents are hereby incorporated as reference material.
The present invention provides a semiconductor device comprising a semiconductor body having a first region of a first conductivity type; and a peak field reducing structure which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region, wherein the first region is more highly doped in a portion adjoining the field reducing structure than in another portion further from the field reducing structure.
A doping gradient may be introduced such that the dopant concentration in a marginal portion of the first region adjacent to the field reducing structure increases towards the field reducing structure.
The more highly doped portion of the first region serves to reduce the peak of the electric field adjacent to the field reducing structure of a RESURF device. Introduction of additional dopant is a process that is readily controllable and adjustable by the device designer to improve the characteristics of a device.
In preferred embodiments, the field reducing structure is in the form of an insulated electrode provided in the trench which extends into the first region of the semiconductor body. A lateral doping gradient may be introduced which leads to a maximum doping concentration in the first region adjacent to the walls of the trench and a minimum in the centre of the device cell.
The first region may be a drift region of a Schottky diode which is contacted by an electrode that forms a Schottky barrier with the drift region. In another embodiment, the device is a trenched pn diode in which the semiconductor body includes a second region of a second, opposite conductivity type over the first region, the first and second regions defining a junction therebetween, wherein the trench extends through the second region into the first region.
According to a further embodiment, the device is in the form of a RESURF trench-gate transistor including a third region of the first conductivity type, such that the first, second and third regions form a drain, channel- accommodating and source region, respectively, with the channel- accommodating region separating the source and drain regions adjacent the trenched electrode and the trenched electrode also acting as a gate.
Preferably, the additional doping is localised adjacent to the lower regions of the trench sidewalls. The more highly doped portion of the first region may extend at least over the bottom third of the extent of the sidewalls of the trench within the first region. In some cases, the more highly doped portion may extend over the full length of the sidewalls of the trench in the first region.
Embodiments of the invention may have a lateral device configuration. Such a device may include a layer of insulating material over a semiconductor substrate of either conductivity type, wherein the first region is provided on the insulating layer, and the insulating layer and substrate together form the field reducing structure. The device may be in the form of a lateral pn diode or transistor. The semiconductor substrate and the overlying insulating layer effectively act as a field plate in this arrangement.
The present invention further provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) etching a trench which extends into the first region; (b) doping the walls of the trench with a dopant of the first conductivity type; and
(c) providing an insulated electrode in the trench to form the field reducing structure.
The present invention also provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) implanting a dopant of the first conductivity type into a portion of the first region to a predetermined depth;
(b) etching a trench which extends into the region defined by the out- diffused dopant; and
(c) providing an insulated electrode in the trench to form the field reducing structure. The present invention still further provides a method of manufacturing a semiconductor device including a semiconductor body having a first region of a first conductivity type, and a peak field reducing structure which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) etching a trench which extends into the first region;
(b) doping the bottom of the trench with a dopant of the first conductivity type;
(c) heating the semiconductor body to cause out-diffusion of the dopant;
(d) etching so as to increase the depth of the trench; and
(e) providing an insulated electrode in the trench to form the field reducing structure.
Embodiments of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein: Figure 1 is a cross-sectional view of a Schottky rectifier with a trenched electrode according to a first embodiment of the invention;
Figures 2 and 3 are graphs showing potential lines in a simulation of a known device configuration and a configuration embodying the present invention, respectively; Figure 4 shows a graph representing electric field profiles in the vertical direction along the trench wall of a known device and a device embodying the invention;
Figure 5 is a graph indicating the change of ionization rate with depth for a known device and a device embodying the invention; Figure 6 is a cross-sectional side view of a trench pn diode according to a second embodiment of the invention;
Figure 7 is a cross-sectional side view of a RESURF trench-gate transistor according to a third embodiment of the invention;
Figure 8 is a cross-sectional side view of a lateral RESURF device according to a fourth embodiment of the invention; Figure 9 is a cross-sectional side view of trenches in a semiconductor body according to a first method embodying the invention;
Figure 10 is a cross-sectional side view of trenches in a semiconductor body according to a second method embodying the invention;
Figures 11 and 12 are cross-sectional side views of a semiconductor body at successive states in the manufacture of a device according to a third method embodying the invention; and
Figures 13 and 14 are cross-sectional side views of a semiconductor body at successive stages in the manufacture of a device according to a fourth method embodying the invention.
It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
Figure 1 is a cross-sectional view of a Schottky barrier diode embodying the present invention. It includes vertical field plates in the form of trenched electrodes 2 formed of doped polysilicon. They extend into respective trenches 4 formed in the drift region 6 of the semiconductor body 8 of the device. The drift region 6 overlies a more highly doped cathode region 10.
A cathode electrode 12 is provided in contact with the cathode region at the bottom major surface 8b of the semiconductor body. Anode electrode 14 comprises a metal and/or metal suicide that forms a Schottky barrier with the drift region 6 and contacts this region at the top major surface 8a. The anode electrode 14 is electrically connected to the trench electrode 2.
A layer of insulating material 16 is provided between each trenched electrode and the semiconductor body 8. Localised more highly doped regions 18 are provided along each sidewall of the trenches 4. They are of the same conductivity type as the remainder of the drift region 6 and, in the embodiment illustrated, these regions extend for the full length of the trench in the semiconductor body. It is preferable for this region to extend at least over the bottom third of the trench sidewalls.
In one example, the bulk of the drift region 6 is doped n-type at a concentration of 1x1016 atoms/cm3, and the region 18 up to a maximum concentration of around 1x1017 atoms/cm3. In this case, the region 18 is around 0.1 micron thick and increases the breakdown voltage by about 11 % in comparison to an equivalent device in which this additional doping is not included. In existing RESURF devices including trenched field plates, the highest electric field concentrations tend to be found at the wall of the trench close to its lower end. Under blocking conditions, potential lines are squeezed at this location resulting in high electrical fields. Even though the highest field strengths occur in the insulating layer around the field plate, the field in a semiconductor body at the trench walls may exceed 105 V/cm, which may lead to the development of avalanche multiplication and ultimately breakdown of the device. Increasing the periodicity of the device with a view to reducing crowding of the potential lines at the edges of the trench leads to breakdown instead at the centre of the device cell, midway between the trenches. In accordance with the present invention, these issues are addressed by provision of increased doping in the drift region at the trench walls. A lateral doping gradient is introduced that has maximum doping concentration at the trench walls and a minimum in the centre of the device cell, midway between adjacent trenches. Figures 2 and 3 show simulations of the potential distribution in a
Schottky diode. Figure 2 represents a known configuration, whilst Figure 3 represents a device embodying the invention which includes a region of additional doping alongside the trench wall. It can be seen that the crowding of potential lines at the corner of the trench is partially suppressed in Figure 3. With the device of Figure 3, reverse bias can be increased by about 11 % beyond the point where breakdown is reached in the configuration of Figure 2. Furthermore, under forward operation, the lower resistivity of the drift region around the trench in the device of Figure 3 embodying the invention supports current flow at the edges of the RESURF cell, which lowers the forward voltage drop significantly. For example, in the simulations of Figure 2 and Figure 3, the forward voltage drop is 18% lower in the device of Figure 3. Due to a large parameter space, the whole potential of this technology is likely to be even higher. The design of RESURF devices offers several geometrical and also material related degrees of freedom for optimization. Examples include trench depth and separation as well as oxide thickness, but also the kind if dielectric material used (e.g. silicon oxide, or silicon nitride) and doping concentrations.
Figures 4 and 5 show simulations of the electric field profile and ionization rates in the vertical direction alongside the trench wall of a device configuration shown in Figures 2 and 3. The solid lines represent data from the Figure 2 configuration and dotted lines correspond to a device embodying the invention as simulated in Figure 3. One can see a higher potential drop in the vertical direction for the known configuration at the bottom of the trench (at a depth of 3 to 4 microns) resulting in massive impact ionization (1023 pairs/cm3/s) as shown in Figure 5. The ionization rate for the device embodying the invention at the trench bottom is essentially zero under the same conditions.
A trench pn-diode embodying the invention is shown in Figure 6. It primarily differs from the diode configuration of Figure 1 in that a p-type anode region 20 is formed between the trenches adjacent to top major surface 8a of the device. It forms a pn junction 22 with the drift region 6. A further device configuration embodying the invention is shown in
Figure 7. It shows a cross-sectional side view through a RESURF trenchFET. In the transistor cell areas of this device, source and drain regions 30, 32 respectively, of a first conductivity type (n-type in this example) are separated by a channel-accommodating body region 34 of the opposite, second conductivity type (that is p-type in this example). A gate electrode 36 is present in a trench 38 which extends through the regions 30 and 34 into an underlying portion of the drain region 40. The electrode extends deep into the drift region to form a field plate 42. An insulating layer 44 separates the electrode 36 from the semiconductor body and its thickness is increased around the field plate 42. Regions 46 of additional dopant (n-type in this example) are provided along the sidewalls of the trench 38 in the drift region. An example of a lateral RESURF device embodying the invention is shown in Figure 8. A conductive substrate 50 is covered by a thick insulating layer 52 (layer 52 may be referred to as "the BOX region"). Region 52 is in turn covered by a doped epitaxial layer 54. Layer 52 may typically be in the form of an oxide. A drift region 56 (n-type in this example) is formed in layer 54 and forms a pn junction with an anode region 58 of the opposite conductivity type (p-type in this example). A more highly doped region 60 of the first conductivity type is adjacent to the top surface 62 of the epitaxial layer 54 and forms a cathode region.
In this embodiment, the conductive substrate 50 effectively acts as a field plate dielecthcally coupled to the epitaxial layer 54 by the insulating layer 52. Substrate 50 and layer 52 together form a peak field reducing structure which extends adjacent to the epitaxial layer 54. A marginal region 64 of the drift region 56 which borders the insulating layer 52 is more highly doped than the drift region 56 in accordance with the invention. As with other configurations described herein, it serves to increase the breakdown voltage of the device and reduce its forward voltage drop.
Embodiments of the form depicted in Figure 8 may be manufactured in various ways. For example, during growth of the buried oxide layer 52, a thin semiconductor layer may remain on top. This layer will have the relatively high doping concentration of the substrate 50 and form the region 64. An n- doped layer can then be grown epitaxially over region 64 in which other features of the device are then formed. Optionally, prior to growth of the n- doped layer, a shallow implantation process may be carried to further increase the doping level in region 64. Alternatively, the vertical doping profile above buried layer 52 may be closely controlled during epitaxial growth of the overlying semiconductor material.
A number of methods embodying the invention for forming an additional more highly doped region adjacent a trenched electrode will now be described with reference to Figures 9 to 14.
In the approach of Figure 9, after the trenches 4 have been etched into the semiconductor body 8, additional dopant is diffused into the trench body to form additional regions 18 exposing the trench walls to a suitable gas.
As depicted in the process stage shown in Figure 10, an alternative method involves depositing a highly doped layer of polycrystalline semiconductor material on the walls of the trench and then heating to cause out-diffusion of the dopant from the polycrystalline layer into the semiconductor body 8 to form the additional regions 18. Layer 70 is then removed before forming the field plate insulating layer over the walls of the trench.
Figures 11 and 12 show successive stages according to a further process for forming the regions of additional doping. In the stage shown in Figure 11 , a dopant is implanted deep into the semiconductor body at locations corresponding to the intended trench positions. The substrate is then heated to out-diffuse the dopant to form regions 80 shown in Figure 11. The trenches 4 are etched into the semiconductor body such that they extend into regions 80 as shown in Figure 12, to form the additional regions 18. With this approach, the additional regions may be restricted to the lower portion of the trenches. Successive stages of a further approach are shown in Figures 13 and
14. Partial trenches 90 are etched initially and then the base of the trench is doped to form regions 92. The semiconductor body is heated to out-diffuse the regions 92 and the trenches etched to their full depth such that they extend into the out-diffuse regions to form the additional regions 18. Although Claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention. Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The Applicants hereby give notice that new Claims may be formulated to such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom.

Claims

1. A semiconductor device comprising: a semiconductor body (8) having a first region (6, 18; 40, 46; 56, 64) of a first conductivity type; and a peak field reducing structure (2, 16; 42, 44; 50, 52) which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region, wherein the first region is more highly doped in a portion adjoining the field reducing structure than in another portion further from the field reducing structure.
2. A device of claim 1 wherein the field reducing structure (2, 16; 42, 44) is in the form of an insulated electrode provided in a trench (4, 38) which extends into the first region.
3. A device of claim 2 wherein the first region is a drift region (6, 18) contacted by a Schottky electrode (14) which forms a Schottky barrier with the drift region.
4. A device of clam 2 including in the semiconductor body a second region (20) of a second, opposite conductivity type over the first region (6, 18) , the first and second regions defining a junction (22) therebetween, wherein the trench extends through the second region into the first region.
5. A device of claim 4 including a third region (30) of the first conductivity type, such that the first, second and third regions form a drain (32, 40, 46), channel-accommodating (34) and source region (30), respectively, with the channel-accommodating region separating the source and drain regions adjacent the trenched electrode (36, 42) and the trenched electrode also acting as a gate.
6. A device of any of claims 2 to 5, wherein said more highly doped portion (18, 46) extends at least over the bottom third of the extent of the sidewalls of the trench (4, 38) in the first region.
7. A device of any of claims 2 to 5 wherein said more highly doped portion (18, 46) extends at least over the sidewalls of the trench (4, 38) in the first region.
8. A device of claim 1 including a layer of insulating material (52) over a doped semiconductor substrate (50), wherein the first region is provided on the insulating layer, and the insulating layer and substrate together form the field reducing structure.
9. A method of manufacturing a semiconductor device including a semiconductor body (8) having a first region (6, 18; 40, 46) of a first conductivity type, and a peak field reducing structure (2, 16; 42, 44) which acts as a field plate dielecthcally coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) etching a trench (4, 38) which extends into the first region;
(b) doping the walls of the trench with a dopant of the first conductivity type; and
(c) providing an insulated electrode in the trench to form the field reducing structure.
10. A method of manufacturing a semiconductor device including a semiconductor body (8) having a first region (6, 18; 40, 46) of a first conductivity type, and a peak field reducing structure (2, 16; 42, 44) which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) implanting a dopant of the first conductivity type into a portion of the first region to a predetermined depth; (b) heating the semiconductor body to cause out-diffusion of the implanted dopant;
(c) etching a trench (4, 38) which extends into the region (80) defined by the out-diffused dopant; and
(d) providing an insulated electrode in the trench to form the field reducing structure.
11. A method of manufacturing a semiconductor device including a semiconductor body (8) having a first region (6, 18; 40, 46) of a first conductivity type, and a peak field reducing structure (2, 16; 42, 44) which acts as a field plate dielectrically coupled to the first region and extends adjacent to the first region, the method including the steps of:
(a) etching a trench (90) which extends into the first region;
(b) doping the bottom of the trench with a dopant (92) of the first conductivity type; (c) heating the semiconductor body to cause out-diffusion of the dopant;
(d) etching so as to increase the depth of the trench; and
(e) providing an insulated electrode in the trench (4, 38) to form the field reducing structure.
PCT/IB2009/051605 2008-04-21 2009-04-17 Semiconductor devices including a field reducing structure and methods of manufacture thereof WO2009130648A1 (en)

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CN103378177A (en) * 2012-04-30 2013-10-30 朱江 Schottky semiconductor device with grooves and preparation method thereof
CN104124151A (en) * 2014-07-14 2014-10-29 中航（重庆）微电子有限公司 Groove structure Schottky barrier diode and production method thereof
CN113838909A (en) * 2021-08-19 2021-12-24 深圳深爱半导体股份有限公司 Groove type primitive cell structure and preparation method

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US5973360A (en) * 1996-03-20 1999-10-26 Siemens Aktiengesellschaft Field effect-controllable semiconductor component
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CN103378177A (en) * 2012-04-30 2013-10-30 朱江 Schottky semiconductor device with grooves and preparation method thereof
CN104124151A (en) * 2014-07-14 2014-10-29 中航（重庆）微电子有限公司 Groove structure Schottky barrier diode and production method thereof
CN113838909A (en) * 2021-08-19 2021-12-24 深圳深爱半导体股份有限公司 Groove type primitive cell structure and preparation method

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