WO2009136401A3 - Improved processing unit implementing both a local and a spread register file system - Google Patents

Improved processing unit implementing both a local and a spread register file system Download PDF

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Publication number
WO2009136401A3
WO2009136401A3 PCT/IL2009/000471 IL2009000471W WO2009136401A3 WO 2009136401 A3 WO2009136401 A3 WO 2009136401A3 IL 2009000471 W IL2009000471 W IL 2009000471W WO 2009136401 A3 WO2009136401 A3 WO 2009136401A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
file system
register file
address
processing unit
Prior art date
Application number
PCT/IL2009/000471
Other languages
French (fr)
Other versions
WO2009136401A2 (en
Inventor
Yoav Peleg
Original Assignee
Cosmologic Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cosmologic Ltd. filed Critical Cosmologic Ltd.
Publication of WO2009136401A2 publication Critical patent/WO2009136401A2/en
Publication of WO2009136401A3 publication Critical patent/WO2009136401A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing unit device comprising a local register file system having registers for storing mapped addresses wherein each register is assigned with an address specified by an instruction operand and a data output port from which the mapped address stored within the registers is outputted Included is a spread register file system comprising data units comprising memory cells that are assigned with memory data unit addresses Each data unit is configured to receive and decode a mapped address, determine a corresponding memory data unit address, output data to be processed from memory cells that correspond to the memory data unit address, and store data within memory cells that correspond to the memory data unit address The processing unit device includes an output port for outputting the data to be processed from the memory cells, and an execution unit for processing data outputted from the spread register file system
PCT/IL2009/000471 2008-05-07 2009-05-07 Improved processing unit implementing both a local register file system and spread register file system, and a method thereof WO2009136401A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7158308P 2008-05-07 2008-05-07
US61/071,583 2008-05-07

Publications (2)

Publication Number Publication Date
WO2009136401A2 WO2009136401A2 (en) 2009-11-12
WO2009136401A3 true WO2009136401A3 (en) 2010-03-11

Family

ID=41265109

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2009/000471 WO2009136401A2 (en) 2008-05-07 2009-05-07 Improved processing unit implementing both a local register file system and spread register file system, and a method thereof

Country Status (1)

Country Link
WO (1) WO2009136401A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050240745A1 (en) * 2003-12-18 2005-10-27 Sundar Iyer High speed memory control and I/O processor system
US20080065862A1 (en) * 1995-08-16 2008-03-13 Microunity Systems Engineering, Inc. Method and Apparatus for Performing Data Handling Operations

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080065862A1 (en) * 1995-08-16 2008-03-13 Microunity Systems Engineering, Inc. Method and Apparatus for Performing Data Handling Operations
US20050240745A1 (en) * 2003-12-18 2005-10-27 Sundar Iyer High speed memory control and I/O processor system

Also Published As

Publication number Publication date
WO2009136401A2 (en) 2009-11-12

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