WO2009158283A1 - Hysteretic buck converter having dynamic thresholds - Google Patents

Hysteretic buck converter having dynamic thresholds Download PDF

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Publication number
WO2009158283A1
WO2009158283A1 PCT/US2009/048016 US2009048016W WO2009158283A1 WO 2009158283 A1 WO2009158283 A1 WO 2009158283A1 US 2009048016 W US2009048016 W US 2009048016W WO 2009158283 A1 WO2009158283 A1 WO 2009158283A1
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WO
WIPO (PCT)
Prior art keywords
regulator circuit
output
buck switching
voltage
indication
Prior art date
Application number
PCT/US2009/048016
Other languages
French (fr)
Inventor
John L. Melanson
Lei Ding
Original Assignee
Cirrus Logic, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Cirrus Logic, Inc. filed Critical Cirrus Logic, Inc.
Priority to EP09770817.6A priority Critical patent/EP2304868B1/en
Priority to CN200980133008.2A priority patent/CN102132478B/en
Publication of WO2009158283A1 publication Critical patent/WO2009158283A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1563—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators without using an external clock
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0019—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being load current fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates generally to hysteretic buck converter control schemes, and more specifically, to a buck converter control circuit in which an indication of output current is used to adjust turn-on timing dynamically .
  • PWM pulse width modulator
  • other types of switching power regulators that deliver high current levels under high load conditions are inefficient. Since the pulse width becomes very narrow for low output current levels, the power used to operate the switching circuits and control/sensing circuits, which does not typically change with load current demand, predominates converter power consumption, making the converter very inefficient during low demand conditions.
  • Alternative controller modes are frequently implemented to operate the converter in a standby low power mode, in which the full converter dynamic performance is not available, but a minimum output voltage is maintained to provide required power supply voltage (s) when the load current demand is low.
  • Pulse- frequency modulator (PFM) circuits are frequently used in low power operating modes, as the pulse frequency can be arbitrarily reduced based upon load demand.
  • Hysteretic control circuits in which the output voltage is maintained between two predetermined set points, have been applied to provide such low-power operating modes.
  • Hysteretic converters have a wide dynamic range and potentially low power consumption, due to their activation only when the output voltage falls below an acceptable limit.
  • hysteretic controllers are sometimes used to provide the power supply control algorithm for all levels of output current, since the control circuit itself can be placed entirely in standby mode, with the low-limit voltage sensing circuit being the only circuit required to operate. The output of the low-limit voltage sensing circuit can then activate the remainder of the converter when the output voltage must be raised. Further, in any application in which the transient response of a PWM converter is not sufficiently fast for responding to load transients, hysteretic converters are also used to provide a fast response to changing load conditions.
  • a constant-width pulse is provided when the output voltage falls below a low- limit threshold, injecting a charge into the output capacitor that raises the output voltage by a predetermined amount.
  • the output current or input voltage conditions are changing, such a converter can produce an undesirable level of ripple, as the constant-width pulse is not responsive to different levels of load current or input voltage.
  • the input voltage and other power supply conditions are monitored and the width of the output pulse is controlled so that the level of ripple is controlled to a greater degree than the constant-width controllers can provide.
  • each of the above hysteretic controllers load transients or input voltage droop can cause undershoot of the low-limit threshold due to time required for the converter to respond.
  • several pulses may be required for the output voltage to recover and in the width-controlled hysteretic converter, an initial undershoot is present, which is corrected by the pulse that has been triggered.
  • the buck switching voltage regulator circuit provides improved ripple control by anticipating the magnitude of the ripple due to load current changes.
  • the circuit may be a control circuit active in a standby mode of a switching regulator, such as a PWM regulator that uses a PWM control mode during higher current output demand and enters standby mode during lower current output demand conditions.
  • a comparison circuit compares the output voltage of the converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases and the lower voltage limit is adjusted to prevent undershoot below a specified lower ripple voltage limit.
  • the turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum.
  • the output current indication may be a measurement of output current, or may be a value calculated from the input voltage and the output voltage waveform.
  • Figures 1A-1B are block diagrams depicting power switching circuits in accordance with embodiments of the present invention.
  • Figure 2A is a simplified schematic diagram of control circuit 1OA of Figure IA.
  • Figure 2B is a simplified schematic diagram of control circuit 1OB of Figure IB.
  • Figure 3A is a signal waveform diagram illustrating calculations performed within threshold generator and control circuit 20A of Figure 2A and threshold generator and control circuit 20B of Figure 2B, in discontinuous conduction mode (DCM) .
  • DCM discontinuous conduction mode
  • Figure 3B is a signal waveform diagram illustrating calculations performed within threshold generator and control circuit 2OA of Figure 2A and threshold generator and control circuit 2OB of Figure 2B, in continuous conduction mode (CCM)
  • Figures 4A-4B are signal waveform diagrams depicting signals within the circuits depicted in Figures 1A-1B and Figures 2A-2B.
  • the present invention encompasses circuits and methods for providing control of a buck switching voltage regulator, in which ripple undershoot is prevented by controlling the turn-on threshold in conformity with an indication of the output current drawn by a load.
  • the output current indication can be provided by measuring the output current directly, or as will be shown in the following description, can be calculated from the output voltage waveform and the value of the input voltage.
  • a control circuit, controller 1OA provides gate drive signals to a switching circuit SWA that couples an inductor Ll in series between an input voltage source V ⁇ N and output terminal V OUT , when transistor Pl is activated by control signal /sa.
  • Switching circuit SWA couples inductor Ll in shunt between output terminal V O u ⁇ and a common return path (ground) associated with input voltage source V ⁇ N and output terminal V 0 UT, when transistor Nl is activated by control signal sb.
  • Output capacitor Cl filters the output of the buck switching voltage regulator circuit, so that the voltage generated at output terminal V O u ⁇ is held substantially constant, except for a ripple voltage.
  • controller 1OA operates in discontinuous conduction mode (DCM) , first activating transistor Pl to charge output capacitor Cl through inductor Ll, then deactivating transistor Pl and activating transistor Nl to discharge energy stored in inductor Ll onto capacitor, and then finally deactivating transistor Nl until the voltage of output terminal V O u ⁇ falls below a threshold magnitude.
  • the threshold magnitude used to determine the turn-on time of transistor Pl is a time-varying waveform generated from an indication of the output current provided from output terminal V O u ⁇ to a load and from the magnitude of the input voltage provided from voltage source V ⁇ N , so that as the output current increases or the input voltage decreases, the time at which transistor Pl is activated occurs earlier in time and as the output current decreases or the input voltage decreases, the time at which transistor Pl is activated occurs later in time.
  • the threshold magnitude is computed from an indication of the output current, which may be a measurement of the output current generated by a sense resistor R 3 , which provides a voltage +VI LO AD that differs from the output terminal V O u ⁇ voltage in proportion to load current I 0 .
  • V O u ⁇ is also designated as -V ILOAD .
  • Controller 1OA computes the turn-off time of transistor Pl, which is also the turn-on time of transistor Nl, from the input voltage provided by voltage source V ⁇ N and the voltage of output terminal V OUT , SO that the ripple voltage at output terminal V O u ⁇ does not exceed a specified maximum.
  • the turn-off time for transistor Nl can be controlled by the current I L provided through inductor L to capacitor Cl as measured by the voltage (+/-V ⁇ L ) across resistor R L reaching a zero or a slightly negative value, to ensure there is no residual energy stored in inductor L.
  • FIG. IB a buck switching voltage regulator in accordance with another embodiment of the invention is shown.
  • the buck switching voltage regulator of Figure IB is similar to that of the buck switching voltage regulator of Figure IA, so only differences between them will be described below. Further, various features in buck switching voltage regulator of Figure IB can be used as alternatives for features illustrated in the buck switching voltage regulator of Figure IA, and vice-versa.
  • Switching circuit SWB uses two N-type transistors N2 and Nl and receives corresponding gate control signals sa and sb from a controller 1OB.
  • An N-channel pair can also be used in the buck switching voltage regulator of Figure IA, with appropriate change in the polarity of gate control signal /sa.
  • Controller 1OB receives only two control input values: the voltage of input source V ⁇ N , and the voltage of output terminal V O u ⁇ - Controller 1OB performs all switch control in conformity with the two control input signal values (V ou t,V in ) , provided by respective input source V ⁇ N and from output terminal V OUT , to generate gate control signals sa and sb.
  • a P-N switching stage such as switching circuit SWA as illustrated in Figure IA can be used with appropriate change to the polarity of gate control signal sa.
  • the turn-on time of transistor Nl can be determined from the two input control signal values (V ou t,V in ) as will be described in further detail below.
  • a pair of tri-state buffers, 26A and 26B are activated by a control signal mode provided by PWM controller 24, when load current I 0 falls below a threshold, or alternatively when PWM controller 24 is placed in standby mode via an external control signal.
  • control signal mode When control signal mode is active, the gate control outputs of PWM 24 are placed in a high-impedance state, so that the hysteretic controller implemented by the balance of circuits within controller 1OA provides gate control output signals /sa and sb.
  • a threshold generator and control circuit 2OA provides a threshold voltage to a comparator Kl, which sets a threshold magnitude (voltage signal Vi ow ) below which input control signal V out activates a start signal, which triggers the beginning edge of gate control signal /sa by activating the set input of flip-flop 22A.
  • a comparator Kl sets a threshold magnitude (voltage signal Vi ow ) below which input control signal V out activates a start signal, which triggers the beginning edge of gate control signal /sa by activating the set input of flip-flop 22A.
  • another comparator K2 activates the reset input of flip-flop 22A and the set input of a flip-flop 22B, which triggers the trailing edge of gate control signal /sa and the leading edge of gate control signal sb.
  • Threshold generator and control circuit 2OA also provides a control signal to the reset input of flip-flop 22B, to trigger the trailing edge of gate control signal sb, when inductor current I L falls below a zero or slightly negative value .
  • Controller 1OB is similar to controller 1OA of Figure 2A, so only differences between them will be described below.
  • Controller 1OB is provided as an example of a minimum-input controller, and also exemplifies a controller that provides all control in hysteretic mode. However, it is understood that the minimum-input configuration can be used in standby modes with another controller type, such as PWM controller 24, illustrated in Figure 2A.
  • Threshold generator and control circuit 2OB receives control input signals (V ou t,V in ) and generates threshold voltages V LO w and V H IGH by calculating them from control input signals (V ou t,V in ) as will be described in further detail below.
  • a timer 28 is provided, which will generally be a counter chain operated from a clock signal, to time the duration of gate control signal sa, for use in calculating an appropriate width of gate control signal sb, since controller 2OB does not directly measure inductor current I L .
  • threshold generator and control circuit 2OA of Figure 2A and threshold generator and control circuit 2OB of Figure 2B are illustrated for discontinuous conduction mode (DCM) .
  • the value of threshold voltage magnitude V LO w required to ensure that the ripple on output terminal V O u ⁇ does not fall below a specified minimum V MIN can be determined either using a measured value for output current I 0 as illustrated in control circuit 2OA of Figure 2A or by using an indication of output current I 0 calculated from control signal values (V in , V out ) as illustrated in control circuit 2OB of Figure 2B.
  • inductor current I L can be approximated as
  • gate control signal sa should be activated no later than the time at which control signal V ou t falls to a threshold level
  • V L0W I 0 2 L / 2C (V in - V ou t )
  • the load current can be measured directly, or by estimation. Since the voltage change across capacitor Cl from time t 0 to time t 2 is VHIGH - V L OW ⁇ the charge added to the capacitor can be expressed as
  • Io [(V 1n - V ou t) (t 2 - t o )]/2L - C(VHIGH - V L0W ) / (t 2 - t 0 )
  • I 0 can be calculated and used as an estimate of inductor current I L , since the difference between them is generally small except under very light load conditions.
  • Io can be calculated from the time period extending from time t 2 to time t 5 according to:
  • V L0W ( V 1n - V out ) ( t 4 - t 2 ) 2 / 2 L - I 0 ( t 5 - t 2 ) which leads to:
  • Io V out (t 4 - t 2 ) 2 /2L(t 5 - t 2 ) - C (VHIGH - V L0W ) / (t 5 - t 2 )
  • VHIGH VMAX ⁇ (IMAX ⁇ Io) (t 3 - t 2 ) /2C will provide the desired switching time.
  • Threshold magnitude V HIGH can also be expressed in terms of V M ⁇ N :
  • VHIGH V M IN + (IMAX - I 0 ) (t 2 - ti)/2C
  • I MAX The peak current
  • VHIGH VMAX " [ (IMAX “ Io) U 2 - ti) (V 1n - V out ) ] /2CV out
  • I MAX ⁇ Io can be determined from the expression for threshold magnitude V HIGH in terms of minimum voltage V M ⁇ N to yield:
  • VHIGH VMAX ⁇ (VHIGH ⁇ VMIN) (V 1n - V ou t) /V ou t and therefore
  • VHIGH VMIN + (VMAX ⁇ VMIN) V ou t/V ln
  • the above expression can be used to produce or calculate a value for threshold magnitude V HIGH as a discrete value based on previous values of control signals V 1n and V ou t or to generate a continuous waveform to control the upper threshold magnitude.
  • V LO w in order to ensure that the voltage of output terminal V O u ⁇ does not fall below minimum voltage V M IN ⁇ threshold magnitude V LO w should be set to:
  • VLOW VMIN + L ( I 0 - IMIN ) 2 / 2 C ( V 1n - V out )
  • the load current can be measured directly, or by estimation. Since the voltage change across capacitor Cl from time t 0 to time t 2 is V H IGH - V LO w, the charge added to the capacitor can be expressed as
  • V L0W (V 1n - V out ) (t 2 - t o ) 2 /2L - (I 0 - IMIN) U 2 - t 0 ) and I 0 - IMIN can be expressed as
  • I 0 - IMIN (V 1n - V out ) U 2 - t o )/2L - C (V H IGH - V LO w)/(t 2 - t 0 ) which is the same as the expression for I 0 in DCM. Since the required quantity for determining V LO w above is I 0 - IMIN, the same computation can be used for estimating the value of I 0 - I MIN in CCM that was used to estimate I 0 in DCM.
  • the alternative expression based upon the time period from time t 2 to time t$ may also alternatively be used, as follows:
  • I 0 - IMIN V out ( t 4 - t 2 ) 2 / 2 L ( t 3 - t 2 ) - C ( V H IGH - V LO w) / ( t 5 - t 2 )
  • VLOW VMIN + (Io ⁇ IMIN) U 6 - ts)/2
  • V LO w VMIN + (Io ⁇ IMIN) U 6 - ts)/2
  • V LO w VMIN + (Io ⁇ IMIN) U 6 - ts)/2
  • VLOW VMAX ⁇ (Io ⁇ IMIN) US - ts)/2
  • VLOW VMIN + V 0 Ut(Io ⁇ IMIN) (ts - ts) /2(V ln - V ou t)
  • FIG. 4A shows operation of the buck switching voltage regulator circuits of Figure IA and Figure IB, controller 1OA of Figure 2A and controller 1OB of Figure IB is illustrated and the calculations used in controllers 1OA and 1OB to determine switching times as described above are described in further detail below. Only DCM is shown, but the illustration is applicable to CCM operation, as well.
  • Figure 4A shows operation of the hysteretic converter circuits of the present invention in response to a change in load current I 0 . As load current I 0 increases, threshold voltage V LO w is increased according to the formulas above, causing the charging transistor to turn on progressively earlier.
  • Figure 4B shows operation of the hysteretic converter in response to a decreasing voltage at input source V ⁇ N , such as operation from a battery that is discharging.
  • the discharge rate is exaggerated to illustrate the effect of the decreasing input voltage on threshold voltage V LO w, which is increased to cause the charging transistor to turn on earlier, compensating for the decrease in the voltage of input source V ⁇ N .

Abstract

A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit (K1, K2) compares the output voltage (Vout) of the buck converter to a waveform (VLow) that is generated from an indication (+VILOAD) of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage (Vout) due to the increased current, preventing an excursion of the output voltage (Vout) below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold (VHIGH) that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage (Vin) and the output voltage (Vout) waveform.

Description

HYSTERETIC BUCK CONVERTER HAVING DYNAMIC THRESHOLDS
FIELD OF THE INVENTION
[0001] The present invention relates generally to hysteretic buck converter control schemes, and more specifically, to a buck converter control circuit in which an indication of output current is used to adjust turn-on timing dynamically .
BACKGROUND OF THE INVENTION
[0002] At low output current levels, pulse width modulator (PWM) controllers and other types of switching power regulators that deliver high current levels under high load conditions are inefficient. Since the pulse width becomes very narrow for low output current levels, the power used to operate the switching circuits and control/sensing circuits, which does not typically change with load current demand, predominates converter power consumption, making the converter very inefficient during low demand conditions. Alternative controller modes are frequently implemented to operate the converter in a standby low power mode, in which the full converter dynamic performance is not available, but a minimum output voltage is maintained to provide required power supply voltage (s) when the load current demand is low. Pulse- frequency modulator (PFM) circuits are frequently used in low power operating modes, as the pulse frequency can be arbitrarily reduced based upon load demand. Hysteretic control circuits, in which the output voltage is maintained between two predetermined set points, have been applied to provide such low-power operating modes. Hysteretic converters have a wide dynamic range and potentially low power consumption, due to their activation only when the output voltage falls below an acceptable limit.
[0003] Also, in low power applications in which either the complexity or the power required for PWM operation is undesirable, hysteretic controllers are sometimes used to provide the power supply control algorithm for all levels of output current, since the control circuit itself can be placed entirely in standby mode, with the low-limit voltage sensing circuit being the only circuit required to operate. The output of the low-limit voltage sensing circuit can then activate the remainder of the converter when the output voltage must be raised. Further, in any application in which the transient response of a PWM converter is not sufficiently fast for responding to load transients, hysteretic converters are also used to provide a fast response to changing load conditions.
[0004] In typical hysteretic converters, a constant-width pulse is provided when the output voltage falls below a low- limit threshold, injecting a charge into the output capacitor that raises the output voltage by a predetermined amount. However, if the output current or input voltage conditions are changing, such a converter can produce an undesirable level of ripple, as the constant-width pulse is not responsive to different levels of load current or input voltage. In other types of hysteretic converters, the input voltage and other power supply conditions are monitored and the width of the output pulse is controlled so that the level of ripple is controlled to a greater degree than the constant-width controllers can provide.
[0005] However, each of the above hysteretic controllers, load transients or input voltage droop can cause undershoot of the low-limit threshold due to time required for the converter to respond. In the constant-width converter, several pulses may be required for the output voltage to recover and in the width-controlled hysteretic converter, an initial undershoot is present, which is corrected by the pulse that has been triggered.
[0006] Therefore, it would be desirable to provide a power supply circuit and control method that reduce ripple in a hysteretic converter by controlling undershoot. DISCLOSURE OF THE INVENTION
[0007] The above stated objective of controlling undershoot in a hysteretic converter is provided in a buck switching voltage regulator circuit and a method of operation of the buck switching voltage regulator circuit.
[0008] The buck switching voltage regulator circuit provides improved ripple control by anticipating the magnitude of the ripple due to load current changes. The circuit may be a control circuit active in a standby mode of a switching regulator, such as a PWM regulator that uses a PWM control mode during higher current output demand and enters standby mode during lower current output demand conditions. A comparison circuit compares the output voltage of the converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases and the lower voltage limit is adjusted to prevent undershoot below a specified lower ripple voltage limit. The turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a value calculated from the input voltage and the output voltage waveform. [0009] The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings .
DESCRIPTION OF THE DRAWINGS
[00010] Figures 1A-1B are block diagrams depicting power switching circuits in accordance with embodiments of the present invention.
[0011] Figure 2A is a simplified schematic diagram of control circuit 1OA of Figure IA.
[0012] Figure 2B is a simplified schematic diagram of control circuit 1OB of Figure IB.
[0013] Figure 3A is a signal waveform diagram illustrating calculations performed within threshold generator and control circuit 20A of Figure 2A and threshold generator and control circuit 20B of Figure 2B, in discontinuous conduction mode (DCM) .
[0014] Figure 3B is a signal waveform diagram illustrating calculations performed within threshold generator and control circuit 2OA of Figure 2A and threshold generator and control circuit 2OB of Figure 2B, in continuous conduction mode (CCM) , [0015] Figures 4A-4B are signal waveform diagrams depicting signals within the circuits depicted in Figures 1A-1B and Figures 2A-2B.
BEST MODE FOR CARRYING OUT THE INVENTION
[0016] The present invention encompasses circuits and methods for providing control of a buck switching voltage regulator, in which ripple undershoot is prevented by controlling the turn-on threshold in conformity with an indication of the output current drawn by a load. The output current indication can be provided by measuring the output current directly, or as will be shown in the following description, can be calculated from the output voltage waveform and the value of the input voltage.
[0017] Referring now to Figure IA, a buck switching voltage regulator circuit in conformity with an embodiment of the invention is shown. A control circuit, controller 1OA provides gate drive signals to a switching circuit SWA that couples an inductor Ll in series between an input voltage source VΣN and output terminal VOUT, when transistor Pl is activated by control signal /sa. Switching circuit SWA couples inductor Ll in shunt between output terminal VOuτ and a common return path (ground) associated with input voltage source VΣN and output terminal V0UT, when transistor Nl is activated by control signal sb. Output capacitor Cl filters the output of the buck switching voltage regulator circuit, so that the voltage generated at output terminal VOuτ is held substantially constant, except for a ripple voltage. At low demand, i.e., for low load current IL supplied to a load ZL, controller 1OA operates in discontinuous conduction mode (DCM) , first activating transistor Pl to charge output capacitor Cl through inductor Ll, then deactivating transistor Pl and activating transistor Nl to discharge energy stored in inductor Ll onto capacitor, and then finally deactivating transistor Nl until the voltage of output terminal VOuτ falls below a threshold magnitude. At higher levels of load current IL, controller 1OA may operate in continuous conduction mode (CCM) as a hysteretic converter, or may transition directly to another CCM control algorithm, such as pulse-width modulation (PWM) . Even if
CCM operation is implemented for the hysteretic operation of the converter, PWM or other operation modes may be initiated after a range of load current IL is exceeded for which hysteretic CCM operation is used.
[0018] In the buck switching voltage regulator of the present invention, the threshold magnitude used to determine the turn-on time of transistor Pl is a time-varying waveform generated from an indication of the output current provided from output terminal VOuτ to a load and from the magnitude of the input voltage provided from voltage source VΣN, so that as the output current increases or the input voltage decreases, the time at which transistor Pl is activated occurs earlier in time and as the output current decreases or the input voltage decreases, the time at which transistor Pl is activated occurs later in time. The threshold magnitude is computed from an indication of the output current, which may be a measurement of the output current generated by a sense resistor R3, which provides a voltage +VILOAD that differs from the output terminal VOuτ voltage in proportion to load current I0. (For illustrative purposes VOuτ is also designated as -VILOAD.) Controller 1OA computes the turn-off time of transistor Pl, which is also the turn-on time of transistor Nl, from the input voltage provided by voltage source VΣN and the voltage of output terminal VOUT, SO that the ripple voltage at output terminal VOuτ does not exceed a specified maximum. Finally the turn-off time for transistor Nl can be controlled by the current IL provided through inductor L to capacitor Cl as measured by the voltage (+/-VΣL) across resistor RL reaching a zero or a slightly negative value, to ensure there is no residual energy stored in inductor L.
[0019] Referring now to Figure IB, a buck switching voltage regulator in accordance with another embodiment of the invention is shown. The buck switching voltage regulator of Figure IB is similar to that of the buck switching voltage regulator of Figure IA, so only differences between them will be described below. Further, various features in buck switching voltage regulator of Figure IB can be used as alternatives for features illustrated in the buck switching voltage regulator of Figure IA, and vice-versa. Switching circuit SWB uses two N-type transistors N2 and Nl and receives corresponding gate control signals sa and sb from a controller 1OB. An N-channel pair can also be used in the buck switching voltage regulator of Figure IA, with appropriate change in the polarity of gate control signal /sa. Controller 1OB receives only two control input values: the voltage of input source VΣN, and the voltage of output terminal VOuτ- Controller 1OB performs all switch control in conformity with the two control input signal values (Vout,Vin) , provided by respective input source VΣN and from output terminal VOUT, to generate gate control signals sa and sb. A P-N switching stage such as switching circuit SWA as illustrated in Figure IA can be used with appropriate change to the polarity of gate control signal sa. Since the output current is related to the voltage waveform of output terminal VOuτ and the voltage of voltage source VΣN, the turn-on time of transistor Nl can be determined from the two input control signal values (Vout,Vin) as will be described in further detail below.
[0020] Referring now to Figure 2A, details of controller 1OA of Figure IA are shown. A pair of tri-state buffers, 26A and 26B are activated by a control signal mode provided by PWM controller 24, when load current I0 falls below a threshold, or alternatively when PWM controller 24 is placed in standby mode via an external control signal. When control signal mode is active, the gate control outputs of PWM 24 are placed in a high-impedance state, so that the hysteretic controller implemented by the balance of circuits within controller 1OA provides gate control output signals /sa and sb. A threshold generator and control circuit 2OA provides a threshold voltage to a comparator Kl, which sets a threshold magnitude (voltage signal Viow) below which input control signal Vout activates a start signal, which triggers the beginning edge of gate control signal /sa by activating the set input of flip-flop 22A. When the magnitude of input control signal Vout rises above another threshold voltage VHIGH, another comparator K2 activates the reset input of flip-flop 22A and the set input of a flip-flop 22B, which triggers the trailing edge of gate control signal /sa and the leading edge of gate control signal sb. Threshold generator and control circuit 2OA also provides a control signal to the reset input of flip-flop 22B, to trigger the trailing edge of gate control signal sb, when inductor current IL falls below a zero or slightly negative value . [0021] Referring now to Figure 2B, details of controller
IOB of Figure IB are shown. Controller 1OB is similar to controller 1OA of Figure 2A, so only differences between them will be described below. Controller 1OB is provided as an example of a minimum-input controller, and also exemplifies a controller that provides all control in hysteretic mode. However, it is understood that the minimum-input configuration can be used in standby modes with another controller type, such as PWM controller 24, illustrated in Figure 2A. Threshold generator and control circuit 2OB receives control input signals (Vout,Vin) and generates threshold voltages VLOw and VHIGH by calculating them from control input signals (Vout,Vin) as will be described in further detail below. A timer 28 is provided, which will generally be a counter chain operated from a clock signal, to time the duration of gate control signal sa, for use in calculating an appropriate width of gate control signal sb, since controller 2OB does not directly measure inductor current IL.
[0022] With reference now to Figure 3A, calculations within threshold generator and control circuit 2OA of Figure 2A and threshold generator and control circuit 2OB of Figure 2B are illustrated for discontinuous conduction mode (DCM) . The value of threshold voltage magnitude VLOw required to ensure that the ripple on output terminal VOuτ does not fall below a specified minimum VMIN can be determined either using a measured value for output current I0 as illustrated in control circuit 2OA of Figure 2A or by using an indication of output current I0 calculated from control signal values (Vin, Vout) as illustrated in control circuit 2OB of Figure 2B. Assuming that output terminal voltage VOuτ is constant, while gate control signal sa is active, inductor current IL can be approximated as
IL (t) = (V1n - Vout) (t - to) /L
, where L is the inductance of inductor Ll, and therefore at time ti,
Figure imgf000015_0001
I0 = (V1n- Vout)(ti - to)/L Therefore, ti - to = I0L/ (V1n - Vout)
The actual voltage droop on output terminal VOuτ from time t0 to time ti, assuming a linear inductor current IL, is given by
ΔV = ILΔt/2C
, where C is the total output capacitance at output terminal VOUT- TO maintain the voltage at output terminal VOuτ above minimum voltage VMΣN, gate control signal sa should be activated no later than the time at which control signal Vout falls to a threshold level
VLOW = VMIN + ΔV = VMIN + I0 (ti - to)/2C Since ti - to = I0L/ (V1n - Vout) in the above approximation for constant inductor current IL, threshold magnitude VLOw can be calculated as
VL0W = I 0 2L / 2C (Vin - Vout )
Therefore, once the values of the inductor and capacitor are known, a waveform for threshold voltage VLOw can be determined from the input voltage signal V1n and control signal Vout and the load current IL, since at the time threshold magnitude VLOw is crossed, IL(ti)= I0.
[0023] To determine the load current used to calculate threshold magnitude VLOw from VLOw = Io2L/2C(Vin - Vout) , the load current can be measured directly, or by estimation. Since the voltage change across capacitor Cl from time t0 to time t2 is VHIGH - VLOWΛ the charge added to the capacitor can be expressed as
C(VHIGH - VLOW) = [(V1n- Vout)(t2 - to)2]/2L - I0 (t2 - t0) and current I0 can therefore be expressed as
Io = [(V1n- Vout) (t2 - to)]/2L - C(VHIGH - VL0W) / (t2 - t0) By measuring the time (e.g., counting clock periods) between the time that the charging switch (e.g., transistor Pl of Figure IA or transistor N2 of Figure IB) is on, I0 can be calculated and used as an estimate of inductor current IL, since the difference between them is generally small except under very light load conditions. Alternatively, Io can be calculated from the time period extending from time t2 to time t5 according to:
C ( VHIGH " VL0W) = ( V1n - Vout ) ( t 4 - t2 ) 2 / 2 L - I 0 ( t5 - t2 ) which leads to:
Io = Vout(t4 - t2)2/2L(t5 - t2) - C (VHIGH - VL0W) / (t5 - t2)
[0024] To determine the magnitude VHIGH of the voltage on output terminal VOuτ at which gate control signal sa should be de-asserted and gate control signal sb asserted, another calculation is performed. The voltage at output terminal VOuτ at time t2, at which VOuτ = VHIGH is VMAX - Q(t3 - t2) /C, where Q(t3 - t2) is the total charge added to capacitor Cl after gate control signal sa is de-asserted and gate control signal sb is asserted, which is equal to VMAX - ( IMAX - Io) (t3 - t2) /2C, where maximum current IMAX is the peak inductor current. Therefore, setting
VHIGH = VMAX ~ (IMAX ~ Io) (t3 - t2) /2C will provide the desired switching time. Threshold magnitude VHIGH can also be expressed in terms of VMΣN:
VHIGH = VMIN + (IMAX - I0) (t2 - ti)/2C The peak current, IMAX, can be determined from
IMAX = I0 + (V1n - Vout) (t2 - ti)/L and
IMAX = I0 + Vout(t3 - t2) /L
, which assume that the output voltage is not changing substantially, and that the inductor current is constant during the charging and discharging. Therefore,
(V1n - Vout) (t2 - ti) /L = Vout(t3 - t2) /L , which leads to: t3 - t2 = (t2 - ti) (V1n - Vout)/Vout
The above expression for t3 - t2 can be substituted in the above expression for VHIGH, yielding:
VHIGH = VMAX " [ (IMAX " Io) U2 - ti) (V1n - Vout) ] /2CVout
IMAX ~ Io can be determined from the expression for threshold magnitude VHIGH in terms of minimum voltage VMΣN to yield:
IMAX ~ Io = 2 C (VHIGH ~ VMiN) / (t2 ~ ti) Finally, combining the last two equations yields:
VHIGH = VMAX ~ (VHIGH ~ VMIN) (V1n - Vout) /Vout and therefore
VHIGH = VMIN + (VMAX ~ VMIN) Vout/Vln
The above expression can be used to produce or calculate a value for threshold magnitude VHIGH as a discrete value based on previous values of control signals V1n and Vout or to generate a continuous waveform to control the upper threshold magnitude.
[0025] In each of the above calculations, it was assumed that the circuit is operating in DCM, i.e., operating such that all of the energy stored in inductor Ll is discharged at times to and t5. However, under higher load conditions, the circuit of the present invention can operate in continuous conduction mode (CCM) and for optimum operation, the computation of the lower threshold magnitude VLOw is changed. However, the computation of the upper threshold magnitude VHIGH is the same as in the above description.
Referring now to Figure 3B, such operation is illustrated. In the signal diagram of Figure 3B time t4 is absent, because there is no significant period of time for which both switching transistors (charging and discharging) are off. In continuous conduction mode, assuming that output voltage V0 is constant,
Figure imgf000019_0001
after the charging transistor (e.g., transistor Pl of Figure IA or transistor N2 of Figure IB) is turned on, given a lower current IMINΓ which is the initial non-zero current value at the turn-on time, then
IL(t)= (V1n- Vout) (t - to) /L + IMIN
which according to the above definition of I0 = IL (t) for discontinuous conduction mode, leads to: t - to = (I0 - IMIN) L/ (V1n - Vout)
Therefore, in order to ensure that the voltage of output terminal VOuτ does not fall below minimum voltage VMINΛ threshold magnitude VLOw should be set to:
VLOW = VMIN + L ( I 0 - IMIN ) 2 / 2 C ( V1n - Vout )
[0026] To determine the load current in CCM, as described above for DCM, the load current can be measured directly, or by estimation. Since the voltage change across capacitor Cl from time t0 to time t2 is VHIGH - VLOw, the charge added to the capacitor can be expressed as
C(VHIGH " VL0W) = (V1n - Vout) (t2 - to)2/2L - (I0 - IMIN) U2 - t0) and I0 - IMIN can be expressed as
I0 - IMIN = (V1n- Vout) U2 - to)/2L - C (VHIGH - VLOw)/(t2 - t0) which is the same as the expression for I0 in DCM. Since the required quantity for determining VLOw above is I0 - IMIN, the same computation can be used for estimating the value of I0 - IMIN in CCM that was used to estimate I0 in DCM. The alternative expression based upon the time period from time t2 to time t$ may also alternatively be used, as follows:
I 0 - IMIN = Vout ( t 4 - t2 ) 2 / 2 L ( t3 - t2 ) - C ( VHIGH - VLOw) / ( t5 - t2 )
[0027] In CCM, it is possible to further optimize the control of threshold magnitude VLOw Since, for the time period between time t5 and time t6, the total charge lost from capacitor Cl is given by:
(I0 - IMIN) U6 - ts)/2 Lower threshold magnitude VLOw is therefore given by:
VLOW = VMIN + (Io ~ IMIN) U6 - ts)/2 Lower threshold magnitude VLOw can also be expressed as:
VLOW = VMAX ~ (Io ~ IMIN) US - ts)/2 The inductor current IL = IMIN at time t5, which occurs when V0 = VLOWΛ can be expressed as:
IMIN = Io " (V1n - Vout) (t6 - ts) /L = I0 - Vout(t5 - t3) /L and therefore
(V1n - Vout) (t6 - t5) = Vout(t5 - t3) The above relations can be combined to yield:
VLOW = VMIN + V0Ut(Io ~ IMIN) (ts - ts) /2(Vln - Vout)
= VMAX " (Io " IMIN) (t5 - t3) /2 and then,
VLOW = VMIN + (VMAX ~ VMIN) Vout/Vln which is the same as the expression for VHIGH in both CCM and DCM. Therefore, for CCM, VL0W = VHIGH.
[0028] With reference now to Figure 4A and Figure 4B, operation of the buck switching voltage regulator circuits of Figure IA and Figure IB, controller 1OA of Figure 2A and controller 1OB of Figure IB is illustrated and the calculations used in controllers 1OA and 1OB to determine switching times as described above are described in further detail below. Only DCM is shown, but the illustration is applicable to CCM operation, as well. Figure 4A shows operation of the hysteretic converter circuits of the present invention in response to a change in load current I0. As load current I0 increases, threshold voltage VLOw is increased according to the formulas above, causing the charging transistor to turn on progressively earlier. Similarly, Figure 4B shows operation of the hysteretic converter in response to a decreasing voltage at input source VΣN, such as operation from a battery that is discharging. The discharge rate is exaggerated to illustrate the effect of the decreasing input voltage on threshold voltage VLOw, which is increased to cause the charging transistor to turn on earlier, compensating for the decrease in the voltage of input source VΣN.
[0029] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention .

Claims

CLAIMSWHAT IS CLAIMED IS:
1. A buck switching voltage regulator circuit, comprising: a comparison circuit for providing a first indication when a voltage of an output of the buck switching voltage regulator circuit does not exceed a first threshold magnitude and providing a second indication when the voltage of the output of the buck switching regulator circuit exceeds a second threshold magnitude, wherein the second threshold magnitude is greater than the first threshold magnitude; an inductive storage element; a switching circuit for coupling the inductive storage element between an input of the buck switching voltage regulator circuit and the output of the buck switching voltage regulator circuit in response to the first indication, and coupling the inductive storage element between the output of the buck switching voltage regulator circuit and a return path of the output of the buck switching voltage regulator circuit in response to the second indication; and a control circuit for generating the first threshold magnitude and the second threshold magnitude, such that the first threshold magnitude increases with increases in an output current provided by the output of the buck switching voltage regulator circuit to a load and decreases with decreases in the output current, and wherein the control circuit calculates an indication of the output current and sets the first threshold magnitude in conformity therewith.
2. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit further sets the second threshold magnitude in conformity with a value of the output current .
3. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit calculates the indication of the output current from a voltage of the output of the buck switching voltage regulator circuit and a time period extending from a beginning of the second indication in a given cycle of the switching circuit and a beginning of the first indication in a next cycle of the switching circuit.
4. The buck switching voltage regulator circuit of Claim 3, wherein the control circuit calculates the indication of the output current according to the formula:
(V1n - Vout) (t2 - to)/2L - C(VHIGH - VL0W) / (t2 - t0) where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit. L is the inductance of the inductive storage element, t2 is a time of the beginning of the second indication in the given cycle, t0 is a time of the beginning of the first indication in the given cycle, VHIGH is a maximum ripple voltage value, and VLOw is a minimum ripple voltage value.
5. The buck switching voltage regulator circuit of Claim 3, wherein the control circuit calculates the indication of the output current according to the formula:
Vout(t4 " t2)2/2L(t5 - t2) - C(VHIGH - VL0W) / (t5 - t2), where Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit. L is the inductance of the inductive storage element, t2 is a time of the beginning of the second indication in the given cycle, ts is a time of the beginning of the first indication in the next cycle, VHIGH is a maximum ripple voltage value, VLOw is a minimum ripple voltage value, and t4 is a time of the end of the second indication in the given cycle.
6. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit measures the output current to provide the indication of the output current.
7. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit calculates the first threshold magnitude further in conformity with a difference between a voltage of the input of the buck switching voltage regulator circuit and the voltage of the output of the buck switching voltage regulator circuit.
8. The buck switching voltage regulator circuit of Claim 7, wherein the control circuit calculates the first threshold magnitude according to the formula:
I0 2L/2C(Vin - Vout), where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit, L is the inductance of the inductive storage element, and I0 is the indication of the output current.
9. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit is operating in a continuous conduction mode and the indication of output current is a difference between a current delivered to the output of the buck switching voltage regulator circuit and a minimum current in the inductive storage element.
10. The buck switching voltage regulator circuit of Claim 1, wherein the control circuit calculates the second threshold magnitude from the voltage of the output of the buck switching voltage regulator circuit and a voltage of the input of the buck switching voltage regulator circuit.
11. The buck switching voltage regulator circuit of Claim 10, wherein the control circuit calculates the second threshold magnitude according to the formula:
VHIGH = VMIN + ( VMAX ~ VMIN ) Vout /Vin , where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, VHIGH is a maximum ripple voltage value, and VLOw is a minimum ripple voltage value.
12. A buck switching voltage regulator circuit, comprising: a comparison circuit for providing a first indication when a voltage of an output of the buck switching voltage regulator circuit does not exceed a first threshold magnitude and providing a second indication when the voltage of the output of the buck switching regulator circuit exceeds a second threshold magnitude, wherein the second threshold magnitude is greater than the first threshold magnitude; an inductive storage element; a switching circuit for coupling the inductive storage element between an input of the buck switching voltage regulator circuit and the output of the buck switching voltage regulator circuit in response to the first indication, and coupling the inductive storage element between the output of the buck switching voltage regulator circuit and a return path of the output of the buck switching voltage regulator circuit in response to the second indication; and a control circuit for generating the first threshold magnitude as a waveform at a rate greater than or equal to a switching period of the switching circuit, wherein the first indication is generated repetitively to control a start of the switching period, and wherein the waveform is generated such that the first indication occurs earlier in time within the switching period as an output current provided by the output of the buck switching voltage regulator circuit to a load increases and occurs later in time within the switching period as the output current decreases.
13. A method for regulating the output voltage of a buck switching voltage regulator circuit, comprising: first comparing a voltage of an output of the buck switching voltage regulator circuit to a first threshold magnitude; second comparing the voltage of the output of the buck switching voltage regulator circuit to a second threshold magnitude, wherein the second threshold magnitude is greater than the first threshold magnitude; coupling an inductive storage element between an input of the buck switching voltage regulator circuit and the output of the buck switching voltage regulator circuit when the first comparing indicates that the voltage of the output of the buck switching voltage regulator circuit does not exceed the first threshold magnitude; coupling the inductive storage element between the output of the buck switching voltage regulator circuit and a return path of the output of the switching voltage regulator circuit when the second comparing indicates that the voltage of the output of the buck switching voltage regulator circuit exceeds the second threshold magnitude; and controlling values of the first threshold magnitude and the second threshold magnitude, such that the first threshold magnitude increases with increases in output current provided by the output of the buck switching voltage regulator circuit to a load and decreases with decreases in the output current, by calculating an indication of an output current provided by the output of the buck switching voltage regulator circuit to a load and setting the first threshold magnitude in conformity therewith .
14. The method of Claim 13, wherein the controlling further comprises setting the second threshold magnitude in conformity with a value of the output current .
15. The method of Claim 13, wherein the controlling calculates the indication of the output current from a voltage of the output of the buck switching voltage regulator circuit and a time period extending from a beginning of the second indication in a given cycle of the buck switching voltage regulator circuit and a beginning of the first indication in a next cycle of the buck switching voltage regulator circuit.
16. The method of Claim 15, wherein the controlling calculates the indication of the output current according to the formula:
(V1n - Vout) (t2 - to)/2L - C(VHIGH - VL0W) / (t2 - t0) where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit, L is the inductance of the inductive storage element, t2 is a time of the beginning of the second indication in the given cycle, to is a time of the beginning of the first indication in the given cycle, VHIGH is a maximum ripple voltage value, and VLOw is a minimum ripple voltage value.
17. The method of Claim 15, wherein the controlling calculates the indication of the output current according to the formula:
Vout(t4 - t2)2/2L(t5 - t2) - C(VHIGH - VL0W) / (t5 - t2), where Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit, L is the inductance of the inductive storage element, t2 is a time of the beginning of the second indication in the given cycle, ts is a time of the beginning of the first indication in the next cycle, VHIGH is a maximum ripple voltage value, VLOw is a minimum ripple voltage value, and t4 is a time of the end of the second indication in the given cycle.
18. The method of Claim 13, further comprising measuring the output current to provide the indication of the output current .
19. The method of Claim 13, wherein the controlling calculates the first threshold magnitude further in conformity with a difference between a voltage of the input of the buck switching voltage regulator circuit and the voltage of the output of the buck switching voltage regulator circuit.
20. The method of Claim 19, wherein the controlling calculates the first threshold magnitude according to the formula:
I 0 2L / 2 C ( Vin - Vout ) , where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, C is a capacitance at the output of the buck switching regulator circuit, L is the inductance of the inductive storage element, and I0 is the indication of the output current.
21. The method of Claim 13, wherein the buck switching voltage regulator circuit is operating in a continuous conduction mode and the indication of output current is a difference between a current delivered to the output of the buck switching voltage regulator circuit and a minimum current in the inductive storage element.
22. The method of Claim 13, wherein the controlling calculates the second threshold magnitude from the voltage of the output of the buck switching voltage regulator circuit and a voltage of the input of the buck switching voltage regulator circuit.
23. The method of Claim 22, wherein the controlling calculates the second threshold magnitude according to the formula:
VHIGH = VMIN + ( VMAX ~ VMIN ) Vout /Vin , where V1n is a voltage of the input of the buck switching regulator circuit, Vout is the voltage of the output of the buck switching regulator circuit, VHIGH is a maximum ripple voltage value, and VLOw is a minimum ripple voltage value.
24. A method for regulating the output voltage of a buck switching voltage regulator circuit, comprising: first comparing a voltage of an output of the buck switching voltage regulator circuit to a first threshold magnitude; second comparing the voltage of the output of the buck switching voltage regulator circuit to a second threshold magnitude, wherein the second threshold magnitude is greater than the first threshold magnitude; coupling an inductive storage element between an input of the buck switching voltage regulator circuit and the output of the buck switching voltage regulator circuit when the first comparing indicates that the voltage of the output of the buck switching voltage regulator circuit does not exceed the first threshold magnitude; coupling the inductive storage element and between the output of the buck switching voltage regulator circuit and a return path of the output of the switching voltage regulator circuit when the second comparing indicates that the voltage of the output of the buck switching voltage regulator circuit exceeds the second threshold magnitude; and generating the first threshold magnitude as a waveform at a rate greater than or equal to a switching period of the switching circuit, wherein the first indication is generated repetitively to control a start of the switching period, and wherein the waveform is generated such that the first indication occurs earlier in time within the switching period as an output current provided by the output of the buck switching voltage regulator circuit to a load increases and occurs later in time within the switching period as the output current decreases.
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