WO2010005670A3 - Methods of forming a plurality of capacitors - Google Patents

Methods of forming a plurality of capacitors Download PDF

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Publication number
WO2010005670A3
WO2010005670A3 PCT/US2009/046946 US2009046946W WO2010005670A3 WO 2010005670 A3 WO2010005670 A3 WO 2010005670A3 US 2009046946 W US2009046946 W US 2009046946W WO 2010005670 A3 WO2010005670 A3 WO 2010005670A3
Authority
WO
WIPO (PCT)
Prior art keywords
openings
masking steps
capacitors
array
forming
Prior art date
Application number
PCT/US2009/046946
Other languages
French (fr)
Other versions
WO2010005670A2 (en
Inventor
Fred D. Fishburn
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020117002912A priority Critical patent/KR101184513B1/en
Priority to EP09794877.2A priority patent/EP2297779B1/en
Priority to CN2009801265651A priority patent/CN102089877B/en
Publication of WO2010005670A2 publication Critical patent/WO2010005670A2/en
Publication of WO2010005670A3 publication Critical patent/WO2010005670A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
PCT/US2009/046946 2008-07-09 2009-06-10 Methods of forming a plurality of capacitors WO2010005670A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020117002912A KR101184513B1 (en) 2008-07-09 2009-06-10 Methods of forming a plurality of capacitors
EP09794877.2A EP2297779B1 (en) 2008-07-09 2009-06-10 Methods of forming a plurality of capacitors
CN2009801265651A CN102089877B (en) 2008-07-09 2009-06-10 Methods of forming a plurality of capacitors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/170,307 US7759193B2 (en) 2008-07-09 2008-07-09 Methods of forming a plurality of capacitors
US12/170,307 2008-07-09

Publications (2)

Publication Number Publication Date
WO2010005670A2 WO2010005670A2 (en) 2010-01-14
WO2010005670A3 true WO2010005670A3 (en) 2010-03-04

Family

ID=41505518

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/046946 WO2010005670A2 (en) 2008-07-09 2009-06-10 Methods of forming a plurality of capacitors

Country Status (6)

Country Link
US (2) US7759193B2 (en)
EP (1) EP2297779B1 (en)
KR (1) KR101184513B1 (en)
CN (1) CN102089877B (en)
TW (1) TWI384587B (en)
WO (1) WO2010005670A2 (en)

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