WO2010012566A1

WO2010012566A1 - Memory arrangement and memory architecture

Info

Publication number: WO2010012566A1
Application number: PCT/EP2009/058546
Authority: WO
Inventors: Andreas Loewe; Arne Zender; Wolfgang Niehsen
Original assignee: Robert Bosch Gmbh
Priority date: 2008-07-28
Filing date: 2009-07-07
Publication date: 2010-02-04
Also published as: DE102008040794A1

Abstract

The invention relates to a memory arrangement comprising a first memory (101), a second memory (103), a first memory access connection (105), a second memory access connection (107), and a configurable interconnection matrix element (109), which is provided to furnish interconnections which are independent of each other between the first memory (101) and the first memory access connection (105) or the second memory access connection (105), and between the second memory (101) and the first memory access connection (105) or the second memory access connection (105).

Description

description

title

Memory arrangement and memory architecture

Technical area

The present invention relates to arrangements of memories, in particular arrangements of cache memories.

State of the art

The development towards ever more powerful control units in the field of digital signal processing continues unabated. A major reason for this is the large amount of data that has to be processed by increasingly complex algorithms. In the past, the computing power required to process these algorithms could be met by increasing the clock frequencies. It turns out, however, that a significant increase of clock frequencies in future systems, especially in future ECUs, is difficult to realize because with increasing frequencies, both the power loss and the temperature increase.

A solution to this problem could be to divide individual processing steps among several process elements at a lower clock rate. In order to achieve optimal performance of such systems, however, a powerful data exchange between the individual process elements is necessary. To realize a data exchange between such process elements, for example, the pipeline operation shown in FIG. 12 can be provided. Thus, the process elements 1201 are hard-wired and arranged in a predetermined order. A disadvantage of the pipeline operation is that an exchange of the process order, for example, in an ASIC (Application Specific Integrated Circuit) is not possible. Furthermore For example, as shown in FIG. 13, the process elements 1301 may be interconnected via massively parallel buses. Although the architecture illustrated in FIG. 13 permits a data exchange between the process elements 1301 one after the other. The disadvantage is that with simultaneous bus access requests of the process elements 1301 waiting times can arise. Such parallel structures are also very resource-consuming.

As shown in FIG. 11, the data exchange between process elements 1101 can also be realized by the use of a common multiport memory 1103 (shared cache), which is used by all process elements 1101 simultaneously. Typically, multiport memories have multiple address and data busses, called ports, that can be used to access memory at the same time. The realization of a multiport memory, however, is resource-consuming due to the necessary memory arbitering mechanism. Moreover, when using the multiport memories, the area requirement of a data word on the chip increases because the abovementioned arbitration mechanism must be implemented in each data word of the memory. Therefore, as the number of ports increases, the footprint of a data word is significantly determined by the arbitration mechanism, thereby creating an unfavorable ratio between the amount of memory and the available chip area.

The data exchange between the process elements is further possible using the architecture shown in FIG. In this case, local memories 1001 are used, which form the so-called distributed cache and are implemented in the individual process elements 1103 in conjunction with massively parallel buses. The data exchange between the process elements 1103 continues to be sequential. However, by distributing the data to the cache memories 1001 and the bus communication, a mechanism for ensuring cache coherency is necessary. Furthermore, due to the parallel bus structure, the realization of the architecture shown in FIG. 10 is resource-consuming.

Disclosure of the invention

The invention is based on the recognition that an efficient exchange of data between process elements can be achieved by separate memories, for example by separate cache memories. Memory, which can be connected via a configurable wiring matrix with each process element, can be realized. The process elements therefore access directly the memory which is relevant for them at the time of processing. Therefore, the permanent copying of the data between the process elements is eliminated, which ensures higher data availability with lower power loss. This results in a block-oriented common memory structure based on a distributed memory architecture, which can be implemented with a reduced amount of resources, because, for example, eliminates the need in the case of a shared cache due to the large number of ports arbitration.

The invention relates to a memory arrangement having a first memory, a second memory, a first memory access terminal, a second memory access terminal and a configurable connection matrix element which is provided, independent connections between the first memory and the first memory access terminal or the second memory access terminal and between the second memory and the first memory access port or the second memory access port. Due to the configurability of the connection matrix element, the memory arrangement can therefore be used within arbitrary multiprocessor surroundings, in particular for the parallel processing of, for example, complex signal processing algorithms.

According to one embodiment, the first memory and the second memory are cache memory, in particular dual-port memory cache memory or single-port memory cache memory. This makes possible a hardware design attributed to known structures.

According to one embodiment, the configurable connection matrix element is provided to provide the independent connections at the same time. This ensures that, for example, processor elements connected to different memory access connections can simultaneously access different memories.

According to one embodiment, the independent connections are preconfigured and fixed. Due to the fixed arrangement of the compounds, the Memory arrangement, for example, a predetermined signal processing sequence already be adapted in advance.

According to one embodiment, the configurable connection matrix element is a programmable element, in particular an FPGA (FPGA: Field Programmable Gate Array). By a simple configurability of the connection matrix element is possible.

According to one embodiment, the configurable connection matrix element comprises a first address multiplexer for addressably connecting the first memory to the first memory access port and / or to the memory access port in multiplex mode, and a second address multiplexer for addressably connecting the second memory to the first memory access port and / or to the memory access port in Multiplexing as well as an arbitration element for arbitrating the addressable connections. Based on the address multiplexer, efficient memory arbitration can be realized.

The invention further relates to a signal processing architecture comprising the memory arrangement according to the invention, a first signal processing element, in particular an image data processing element which is connected to the first memory access terminal for accessing the first memory or the second memory, and a second signal processing element, in particular an image data processing element, for accessing the first memory or the second memory is connected to the second memory access terminal.

According to one embodiment, the first signal processing element is configured to access the first memory for processing the data stored therein via the connection matrix element and to access the second memory via the connection matrix element in order to store therein a result of the processing of this data, wherein the second signal processing element is formed to access the second memory via the connection matrix element for further processing of the result stored in the processing of the data stored in the memory.

The memory arrangement according to the invention makes it possible to ensure efficient processing of signal processing steps by the signal processing elements. the. The memories can be used, for example, as a cache for providing processable data and for storing intermediate results.

The invention further relates to a method for providing connections between a first memory, a second memory, a first memory access port and a second memory access port of a memory device, providing configurable and independent connections by means of a configurable connection matrix element between the first memory and the first memory access port or the second Memory access port and between the second memory and the first memory access port or the second memory access port.

The invention further relates to a signal processing method using the inventive signal processing architecture and memory device accessing the first memory for accessing the data stored therein via the connection matrix element, accessing the second memory via the connection matrix element to store therein a result of the processing of that data and accessing the second memory via the connection matrix element to further process the stored result of processing the data stored in the memory.

drawings

Further embodiments will be explained with reference to the accompanying drawings. Show it:

Fig. 1 a memory arrangement;

Fig. 2 is a system architecture;

3 shows a system architecture;

4 shows a system architecture; 5 shows a memory structure;

Fig. 6 is a system architecture;

Fig. 7 shows a flow of a signal processing method;

8 is a data flow diagram;

Fig. 9 is a system architecture;

Fig. 10 is a system architecture;

Fig. 11 is a system architecture;

Fig. 12 is a system architecture; and

Fig. 13 is a system architecture.

Description of the embodiments

1 discloses a memory arrangement having a first memory 101, a second memory 103, a first memory access terminal 105, a second memory access terminal 107, and a configurable connection matrix element 109. Both the memories 101, 103 and the memory access terminals 105, 107 are electrically powered Connections to the configurable connection matrix element 109 connected.

The configurable connection matrix element 109 is provided, for example, to provide configurable electrical connections between the memory access terminals 105 and 107 on the one hand and the memories 101 and 103 on the other hand in the manner of a connection matrix. For example, both the first memory 101 and the second memory 103 can be accessed via the memory access port 105. On the other hand, the connection matrix can inhibit, for example, a connection between the memory access terminal 107 and the memory 101, so that only the second memory 103 can be accessed via the memory access port 107. The memories 101 and 103 are, for example, cache memories which are used for temporary data and result storage. To the memory access terminals 105 and 107 are signal processing elements, such as process elements, connected, which process, for example, a signal processing algorithm.

2 shows a system architecture with a plurality of memories 201, for example cache memories, as well as with a plurality of signal processing elements 203, for example process elements. The signal processing elements 203 are connected to the feeders 201 in the manner of a connection matrix by a connection matrix element 205. In each case memory access connections are provided, via which the signal processing elements 203 can be connected to the connection matrix element 205. The connection matrix element 205 is preferably configurable and may be designed, for example, as a crossbar switch or as a programmable processor or as a programmable FPGA (FPGA: Field Programmable Gate Array).

FIG. 3 shows the system architecture shown in FIG. 2, in which, in addition to the signal processing elements 203, for example process elements, connected to the connection matrix element 205, a further signal processing element 301 is provided. The further signal processing element 301 is preferably connected to each of the signal processing elements 203, for example via a communication bus. Preferably, the further signal processing element 301 is designed as a higher-level process unit, for example as a CPU (CPU: Central Processing Unit), in order to coordinate the signal processing elements 203. This higher-level process unit 301 has, for example, knowledge of when which process element 203 is allowed to process which data stored in the respective cache memory 201. Thus, simultaneous data access of multiple process elements 203 to a data word while satisfying the cache coherency requirement is avoided.

For resource and cost reasons, the size of a cache memory is limited. For example, if the process elements 303 are to process a data area which is larger than the available cache memory size, then the data or signal processing can take place in regions. The data areas can be For example, they may be loaded in the cache memories from an external memory sequentially. For this purpose, it is preferable to provide a further control mechanism and a further port in each cache. FIG. 4 shows such a system architecture using the example of the system architecture shown in FIG. 3.

In this case, for example, a communication bus 401 is provided, to which memory 403, for example cache memories, are connected. Each of the memories 403 is connected to the connection matrix element 205 in the manner described above. Furthermore, a further memory 405 is provided, which is also connected to the communication bus 401. The further signal processing element 301 is also connected to the communication bus 401, so that an efficient control of a data flow between the further memory element 405, which is embodied for example as an SDRAM memory (SDRAM: Synchronous Dynamic Random Access Memory), is ensured. The control mechanism can be realized, for example, by means of the further signal processing element 301, which ensures that the data areas desired by the respective process element 201 are always present in the respective cache memory 403 from the external memory 405, which is for example a mass memory. Such a control mechanism can also help to write changed data areas of the respective cache memory 403 back into the further memory 405. In this case, the connection between the further memory 405 and the individual cache memories 403 can take place via the communication bus 401, which is for example a standardized processor bus. For this purpose, it is advantageous to provide an interface between the cache memories 403 and the communication bus 401.

According to one embodiment, it is not necessary for each cache memory 403 to gain access to the communication bus 401. If, for example, one of the cache memories 403 is not connected to the communication bus 401, then this memory can be accessed exclusively via the connection matrix element 205.

FIG. 5 shows a structure of a cache memory which may be used as one of the cache memories 401 shown in FIG. 4, for example. The cache memory includes a bus interface 501, a dual-port memory area 503 (dual-port memory), a cache control 505 (cache-control), and communication links between the cache Bus interface 501, the dual-port memory area 503 and the cache controller 505. The bus interface 501, for example, can communicate bidirectionally with a bus not shown in FIG. The dual-port memory 503 also has a further port with which, for example, a bidirectional connection to a connection matrix element can be established. By way of example, a signal processing element or a control mechanism can act on the data flow between the cache memory and, for example, an external memory via the cache controller 505, which may also be connected to the connection matrix element.

6 shows a system architecture with a first memory 601, for example a cache memory, and a second memory 603, for example a further cache memory. Further, the system architecture includes a first signal processing element 605 and a second signal processing element 607. The signal processing elements 605 and 607 may be, for example, process elements.

The signal processing elements 605 and 607 access the memory elements 601 and 603 via a connection matrix element. Each of the memories 601 and 603 are each assigned an address multiplexer 609, 611, a write data multiplexer 613 and 615 and a read data multiplexer 617 and 619. For memory arbitration, an arbitration element 621 is optionally provided, which is connected to each memory element 601 and 603. The signal processing elements 605 and 607 have terminals connected to the arbitration element 621. The arbitration element 621 further has a first and a second output, the first output for controlling the elements 609, 613 and 617 associated with the first memory element 601 and the second output for controlling the elements 611, 615 and 619 associated with the second memory element 603 is provided. The arbitration element 621 also has an error output 623, via which an error signal can be output.

The arbitration element 621 is optional in particular when the coordination of the memory area accesses is controlled by a higher-order process element. However, if the coordination of the memory accesses to be performed in self-responsibility of the process elements 605 and 607, the provision of the Arbitrierungselementes 621 in the multiplexer circuit to prevent memory conflicts is advantageous. For example, the arbitration element 621 can deactivate the address multiplexer 609. in order to prevent the first process element 605 from accessing the first memory 601. By activating or deactivating the respective write data multiplexer 613 or 615 or the respective read data multiplexer 617 or 619, further memory accesses can be coordinated.

Each address multiplexer 609 and 611 is connected to each of the process elements 605 and 607. As a result, each process element 605, 607 can access each memory 601 or 603. In analogy, the write data multiplexers 613 and 615 are connected to each of the process elements 605 and 607, which can write data into each of the memories 601 and 603, respectively. The read data multiplexers 617 and 619 further connect each memory 601 and 603 to each of the process elements 605 and 607, respectively, so that each process element 605, 607 can read the data from the respective memory 601 and 603, respectively. The access control can be carried out by the Arbitrierungsele- element 621.

FIG. 7 illustrates a timing of a signal processing method in which the signal processing elements 701 and 703, for example, process elements, access memories 707, 709, 711, and 713 via a connection matrix element 705. The memories 707, 709, 711 and 713 are, for example, cache memories and access a mass memory 717, for example an SDRAM, via a communication bus 715.

The mass memory 717 is subdivided into data areas DO, D1,..., D5,..., In which data are stored which are processed by the process elements 701 or 703 in chronological order, which is determined, for example, by the execution of an image processing algorithm become. For example, first, the data DO may be loaded into the memory cache 701, whereby the memory cache 707 contains data CO. The signal processing element 701 processes the data CO according to a signal processing algorithm and stores a result C2 in the second memory memory cache 709. The result C2 can also be stored, for example, in the memory area D2 of the mass memory 717. In a further signal processing step, the data Cl are loaded into the first memory cache 707 from the memory area D1 of the mass memory 717 by the first signal processing element 701. The first signal processing element 701 processes this data in accordance with a further signal processing. processing step and stores a result of this processing in the form of data C3, for example, in the third memory cache 711. This result data C3 can also be stored in the memory area D3 of the mass memory 717.

The second signal processing element can in turn access the result data C2 stored in the memory 709, process it in accordance with a further signal processing step and store the resultant result data C4 in the memory cache 713. This data may, for example, also be stored in the memory area D4 of the mass memory 717. If the result data C3 is present in the memory cache 711, the second signal processing element can access it and process this data in order to obtain a processing result C5 which is available in the form of

Data can be stored in the memory cache 713. The result data C5 can in turn be stored in the memory area D5 of the mass memory 717. The data flow can be controlled, for example, by a higher-level process unit, such as a CPU (CPU: Central Processing Unit).

FIG. 7 shows by way of example two signal processing elements and four memory elements. However, the concept illustrated in FIG. 7 can be extended to any number of signal processing elements and any number of memory elements.

Fig. 8 illustrates a timing of the data CO, C1, C2, C3, C4 and C5. At this time, the data CO and Cl are read out in a processing section 801 by the first signal processing element 701, for example. In a processing section 803, the result data C2 and C3 are output by the first signal processing element 703. In another signal processing section 805, the data C2 and C3 are read in by the second signal processing element 703. The second

Signal processing element 703 processes this data and outputs in a processing section 807 the result data C4 and C5. As shown by the vertical dashed line 809, each memory cache 707, 709, 711, and 713 is preferably addressed only once to avoid access conflicts.

9 shows a further exemplary embodiment of a memory architecture comprising two signal processing elements 901 and 903 as well as two memories 905 and 907. The memories 905 and 907 can be, for example, cache memories, while the signal processing be processing elements 901 and 903, for example, process elements. The signal processing elements 901 and 903 access the memories 905 and 907 via a connection matrix element 909. The connection matrix element 909 may, for example, be a configurable crossbar switch which has, for example, a preconfigured connection matrix which connects the elements shown in FIG. 9 together.

An advantage of the invention is that all process elements can be connected directly to one or more arbitrary memories, for example cache memories. The memories can be, for example, resource-conserving dual-port memories, so that the memory architecture according to the invention can be implemented cost-effectively. The connection matrix element may, for example, be designed as a multiplexer, which determines which memory cache is to be connected to which signal processing element. In addition, preferably all signal processing elements can access the caches in parallel, which increases the processing speed. It is not necessary to copy the data from one signal processing element to another because the data exchange can be realized by simply switching between the memories. The power loss can also be significantly reduced by eliminating the data transfer between the signal processing elements, in particular via a communication bus, because the necessary functionality is eliminated. The memories may also have access to one or more common mass memories so that the data may be exchanged between the memories and the mass storage as needed. In this case, for example, a control mechanism in the memories generate a memory image of the mass storage in its own memory. The control mechanism in the memories may also rewrite changed data areas in the mass storage, which increases the performance of the structure according to the invention.

Thus, resource conserving storage ar- rangement is provided to ensure greater data availability in massively parallel signal processing systems. The connection matrix element may, for example, be realized as an interconnection matrix, for example as a multiplexer or a crossbar switch between the signal processing elements and the distributed memories. The memories may also be designed as a dual-port cache memory. According to another embodiment For example, the dual port caches may be replaced with single port caches associated with, for example, a time division multiple access method. By appropriate programming, a further reduction in resource requirements can be achieved. The connection matrix element can also be replaced by a tri-state bus, which enables a particularly resource-saving implementation in an ASIC.

Claims

claims

1. Memory arrangement, with:

a first memory (101);

a second memory (103);

a first memory access port (105);

a second memory access port (107); and

a configurable connection matrix element (109) which is provided, independent connections between the first memory (101) and the first memory access port (105) or the second memory access port (105) and between the second memory (101) and the first memory access port ( 105) or the second memory access port (105).

2. A memory device according to claim 1, wherein the first memory (101) and the second memory (103) are cache memory, in particular dual-port memory cache memories.

A memory device according to any one of the preceding claims, wherein the configurable connection matrix element (109) is arranged to provide the independent connections at the same time.

A memory device according to any one of the preceding claims, wherein the independent connections are preconfigured and fixed.

5. Memory device according to one of the preceding claims, wherein the configurable connection matrix element (109) is a programmable element, in particular an FPGA (FPGA: Field Programmable Gate Array).

6. The memory device of claim 1, wherein the configurable connection matrix element comprises a first address multiplexer for addressably connecting the first memory to the first memory access port and / or to the memory access port in multiplex mode , a second address multiplexer for addressably connecting the second memory (103) to the first memory access port (105) and / or to the memory access port (105) in multiplex mode, and an arbitration element for arbitrating the addressable connections.

7. Signal processing architecture, with:

the memory device according to one of claims 1 to 6;

a first signal processing element, in particular an image data processing element, connected to the first memory access port (105) for accessing the first memory (101) or the second memory (103); and

a second signal processing element, in particular an image data processing element, which is connected to the second memory access port (107) for accessing the first memory (101) or the second memory (103).

A signal processing architecture according to claim 7, wherein the first signal processing element is arranged to access the first memory (101) via the connection matrix element (109) for processing the data stored therein and to access the second memory (103) via the connection matrix element (109). for storing therein a result of the processing of this data, and wherein the second signal processing element is adapted to access, via the connection matrix element (109), the second memory (103) for further processing the result of processing therein the data stored in the memory (101).

A method for providing connections between a first memory, a second memory, a first memory access port, and a second memory access port (107) of a memory device, comprising:

Providing configurable and independent connections by means of a configurable connection matrix element between the first memory and the first memory access port or the second memory access port and between the second memory and the first memory access port or the second memory access port.

Signal processing method using the signal processing architecture according to claim 7 or 8 with the memory device according to one of claims 1 to 6, comprising:

Accessing, via the connection matrix element, the first memory for processing the data stored therein;

Accessing the second memory via the connection matrix element to store therein a result of the processing of that data, and

Accessing the second memory via the connection matrix element to further process the stored result of processing the data stored in the memory.