WO2010030474A1 - Interconnect structures for stacked dies, including penetrating structures for through-silicon vias - Google Patents
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias Download PDFInfo
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- WO2010030474A1 WO2010030474A1 PCT/US2009/054313 US2009054313W WO2010030474A1 WO 2010030474 A1 WO2010030474 A1 WO 2010030474A1 US 2009054313 W US2009054313 W US 2009054313W WO 2010030474 A1 WO2010030474 A1 WO 2010030474A1
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200980141580.3A CN102187458B (en) | 2008-09-11 | 2009-08-19 | Comprise the stacked die interconnection structure of the penetrant structure for wearing silicon through hole |
KR1020117008164A KR101260219B1 (en) | 2008-09-11 | 2009-08-19 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/209,029 | 2008-09-11 | ||
US12/209,029 US7872332B2 (en) | 2008-09-11 | 2008-09-11 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods |
Publications (1)
Publication Number | Publication Date |
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WO2010030474A1 true WO2010030474A1 (en) | 2010-03-18 |
Family
ID=41119470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2009/054313 WO2010030474A1 (en) | 2008-09-11 | 2009-08-19 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias |
Country Status (5)
Country | Link |
---|---|
US (4) | US7872332B2 (en) |
KR (1) | KR101260219B1 (en) |
CN (1) | CN102187458B (en) |
TW (1) | TWI445151B (en) |
WO (1) | WO2010030474A1 (en) |
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CN102187458B (en) | 2016-04-20 |
US9165888B2 (en) | 2015-10-20 |
US7872332B2 (en) | 2011-01-18 |
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KR101260219B1 (en) | 2013-05-06 |
US20110111561A1 (en) | 2011-05-12 |
TWI445151B (en) | 2014-07-11 |
TW201017852A (en) | 2010-05-01 |
US20130234296A1 (en) | 2013-09-12 |
US20100059897A1 (en) | 2010-03-11 |
US20140206145A1 (en) | 2014-07-24 |
CN102187458A (en) | 2011-09-14 |
US8435836B2 (en) | 2013-05-07 |
US8680654B2 (en) | 2014-03-25 |
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