WO2010045213A1

WO2010045213A1 - Programmable gain amplifier

Info

Publication number: WO2010045213A1
Application number: PCT/US2009/060478
Authority: WO
Inventors: Jonathan Ephraim David Hurwitz; Adria Bofill-Petit; Robert K. Henderson
Original assignee: Gigle Networks Inc.
Priority date: 2008-10-13
Filing date: 2009-10-13
Publication date: 2010-04-22
Also published as: US20100117734A1; US8188791B2; WO2010045215A1; US20110227651A1; US7956689B2

Abstract

A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Description

Programmable Gain Amplifier

CROSS-REFERENCE TO RELATED APPLICATIONS

(OOOlJ This application is related to U.S. Patent Application Serial No. 12/250,450 entitled "Programmable Gain Amplifier" filed October 13, 2008; U.S. Patent Application Serial No. 12/577,536 entitled "Programmable Gain Amplifier and Transconductance Compensation System" filed October 12. 2009; U.S. Patent Application Serial No. 11/467,141 entitled "Multi-Wideband Communications over Power Lines" filed September 28, 2006; U.S. Patent Application Serial No. 12/075,888 entitled "Coupling Signal Processing Circuitry with a Wireline Communication Medium" filed March 14, 2008; U.S. Patent Application Serial No. 1 1/752,887 entitled "Multi- Wideband Communications over Multiple Mediums" filed May 23, 2007; and U.S. Patent Application Serial No. Application No. 12/145,475 "entitled Resistor-Input Transconductor Including Common-Mode Compensation" filed June 24. 2008 and issued as U.S. Patent No. 7,602,220 on October 13, 2009. The disclosures of each of the above patent applications are incorporated herein by reference.

BACKGROUND

[0002] Field of the Invention

[0003] The invention is in the field of electronics and more specifically in the field of programmable amplification.

[0004\ Related Art

[0005] The receipt of signals in communication systems often includes amplification of analog signals and conversion of these signals to digital values using an analog to digital converter. The magnitude of the received signal may be dependent on the signal's strength at its source, the distance and path traveled, and the efficiency of detection of the signal. As a result, the magnitude of received communication signals may vary widely and unpredictably. [0006] A wide variability in signal magnitude raa> result in loss of information when lhc signal is conv erted Io digital values at the analog to digital converter. Analog to digital converters typically are configured to convert signals oxer a set magnitude range to a set number of digital bits. For example, an analog to digital converter ma}¹ be configured to convert signals between 0 and 5 Volts to an eight bit digital value. In this case the maximum digital value is generated when the signal is at 5 Volts and the minimum digital value (0) is generated when the signal is at 0 Volts. Problems arise when the received signal is between, for example. 0 and 2 Volts or 0 and 10 Volts. In these cases the signal is mismatched to the input range of the analog to digital converter. The best signal to noise is achieved when the signal is matched to the input range of the analog to digital converter. [0007] Because of these problems it is well known to pass the received signal through a programmable gain amplifier. The programmable gain amplifier may be configured to apply a gain larger than one or a gain smaller than one to the signal. For example, a gain greater than one may be used to increase a 0 to 2 Volt signal to 0 to 5 Volts, and a gain less than one may be used to decrease a 0 to 10 Volt signal to 0 to 5 Volts.

[0008] There are two general approaches to programmable gain amplifiers. In one approach the programmable gain amplifier includes a single gain stage whose gain can be changed by, for example, changing the value of a resistance or capacitance. In an alternative approach a series of fixed gain stages are used to produce a stepwise variable gain. In this approach switches are used to control which of the gain stages are included in a signal path. By adding or removing gain stages from the signal path different amounts of gain ma> be achieved. It is possible for a programmable gain amplifier to include both variable and fixed gain stages. |0009j One problem in using a series of gain stages is that any noise introduced bv/ the first gain stage is amplified by later stages. As a result it is preferable to include as much of the total gain of the series in the first gain stage. This first stage must also be able to receive and amplify a wide range of signal magnitudes. Another problem of using a series of gain stages is to maintain linearity of the system. It turns out that to optimize the linearity of the system it is preferable to include as much of the total gain of the series in the last of the gain stages. [0010} These two factors result in a trade-off between linearity and noise for the system. To minimize noise one would prefer to place most of the gain in the first stages but to optimize linearity one would prefer to place most of the gain in the later stages. There is, therefore, a need for improved programmable gain amplifiers.

SUMMARY

[0011] Various embodiments of the invention comprise a programmable gain amplifier comprising a front end including one or more transconductors and a back end including one or moie current-mode gain stages. Each of the front end and the back end are separately programmable so as to control gain and other operating characteristics of the programmable gain amplifier. For example, gain of the front end may be controlled by alternatively coupling the output of the one or more transconductors to the output of the front end. Gain of the back end may be controlled by including or not including individual members of the one or more current-mode gain stages in the current path.

[0012] Transconductors within the front end are optionally in a parallel array wherein the inputs of each can be coupled to a common point and the outputs of each can be coupled to another common point. For example, the outputs of each transcondiictor may be switchably coupled to the same conduction (output) point, e.g., coupled through one or more switches such that the coupling can be svv itched on and off. Each of the transconductors may be configured to receive signals within specific frequency and/or voltage ranges. As such, switches may be used to select which transconductor is within the single path responsive to the characteristics of the signal. [00131 The current-mode gain stages of the back end comprise current amplifiers in series. Members of the current-mode gain stages can be switched in and out of the signal path to select which stages are used to amplify the signal, and thus how much amplification the signal receives.

[00141 Bv using separately variable front and back ends, one of which is configured to convert voltage to current and the other current-to-eurrent or current-to- voltage, tradeoffs between optimizing signal amplification and minimizing noise maj be reduced relative to the prior art. The elements of each stage may be single-ended or differential, and the amplification may result in an increase or a decrease in the magnitude of the signal. [0015] Various embodiments of the invention include a system comprising: a front end comprising a first transconductor configured to receive a voltage and generate a current proportional to the voltage received by the first transconductor, a second transconductor in parallel with the first transconductor and configured to receive a voltage and generate a current proportional to the voltage received by the second transconductor, and a switch configured to create a signal path from an input of the front end to an output of the front end through alternatively the first transconductor or the second transconductor; and a back end comprising a first current-mode gain stage configured to receive current from the front end and to generate a current proportional to the current received from the front end, a second current-mode gain stage in series with the first current-mode gain stage, configured to receive current via the first current-mode gain stage, and configured to generate current proportional to the current received by the second current-mode gain stage, and a switch configured to select whether or not the second current-mode gain stage is included in a signal path from an input of the back end to an output of the back end.

[0016J Various embodiments of the invention include a method comprising: receiving a signal; setting a first switch to alternatively create a first signal path through a first but not a second of a plurality of parallel transeonduetors, or create the first signal path through the second but not the first of the plurality of parallel transconductors: generating a first current proportional to a voltage of the signal by passing lite signal through the first signal path; setting a second switch to alternatively create a second signal path through a first and a second of a plurality of serial current-mode gain stages, or create the signal path through the second but not the first of the serial current -mode gain stages; and generating a second current proportional to the first current by passing the signal through the second signal path. [0017] Various embodiments of the invention include a system comprising: a front end comprising alternatively selectable parallel means for receiving a voltage and converting the received voltage to a current; a back end comprising serial means for variably amplifying the current; and control logic configured to control a ratio between the received voltage and the current, and a ratio between the current and the amplified current. [0018] Various embodiments of the invention include a method comprising: receiving a signal; setting a first switch to create a first signal path through one of a plurality of parallel transconductors; generating a first current proportional to a voltage of the signal by passing the signal through the first signal path; setting a second switch to create a second signal paih through a first and a second of a plurality of serial current-mode gain stages; and generating a second current proportional to the first current by passing the signal through the second signal path.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 illustrates a signal processing system, according to various embodiments of the invention.

[00201 FIG. 2 illustrates a programmable gain amplifier comprising a front end and a back end, according to various embodiments of the invention. [00211 FIG. 3 illustrates a programmable gain amplifier comprising a differential mode front end and a differential mode back end. according to ^■various embodiments of (he invention.

10022 J FIGs. 4A and 4B illustrate alternative embodiments of a back end. according to various embodiments of the invention.

[0023] FIGs. 5 A and 5B illustrate a matrix of programmable gains possible using the front end and the back end, according to various embodiments of the invention.

[0024] FIG. 6 illustrates various programmable gains within the back end, according to various embodiments of the invention.

[0025] FIG. 7 illustrates a transconductor with resistor-dependent transconductance, according to various embodiments of the invention.

[0026] FIG. 8 illustrates a transconductor based on the transconductance of a transistor, according to various embodiments of the invention.

[0027] FIG. 9 illustrates a current-mode gain stage, according to various embodiments of the invention.

[0028] FIGs. 1OA and 1OB illustrate two exemplary variable resistance resistors, according to various embodiments of the invention.

[0029] FIG. 1 1 illustrates a method of processing a signal, according to various embodiments of the invention.

DETAILED DESCRIPTION

[0030] An improved programmable gain amplifier includes different types of circuits in a front end and a back end. The front end comprises a plurality of transconductors in parallel. Switches are configured to create a signal path selectively through one or more of these transconductors. responsive to the magnitude of a received signal. Each of the lransconductors is configured to generate a current proportional to a received signal voltage. The ratio of received voltage to generated current is typically different for each transconductor. Each transcondiictor may further be configured to receive signals in a different voltage range. For example, one transconductor may be configured to receive signals between 0 and 1 Volts while another of the transeonduetors is configured to receive signals between 0 and 2 Volts. The plurality of transeonduetors in the front end allows for the selection and use of a transconductor best configured to receive a particular signal. In various embodiments this allows for amplification of the signal while maximizing the signal to noise ratio at the output of the front end. The front end raa\ be operated in a differential or single-end mode.

[0031] The back end comprises a plurality of amplifiers in series. These serial amplifiers are typically configured to operate in current mode (e.g., to amplify a current). Switches are configured to select which members of the plurality of amplifiers are included in a signal path between an input and an output of the back end. The total amplification that occurs in the back end is a function of the number and/or identity of the members of the plurality of amplifiers that are included in the signal path for any particular state of the switches. The total amplification of the programmable gain amplifier is the combination of the amplification of the front end and the back end. Either of these segments may have an amplification that is less than or greater than one.

[0032] The programmable gain amplifier is optionally configured to provide an amplified signal to an analog to digital converter. For example, some embodiments include control logic configured Lo program (e.g.. by setting switches of the front end and/or back end) the programmable gain amplifier to amplify the signal such that it is matched to the dynamic range of the analog to digital converter.

[0033] FIG. 1 illustrates a Signal Processing System 100, according to various embodiments of the invention. Signal Processing System 100 includes a Signal Source 1 10, a Programmable Gain Amplifier 120, an Analog to Digital Converter 130. and a Control Logic 140, Signal Source 1 10 maj include, for example, an antenna, a communication cable connector, a sensor, an optical coupler, a transducer, a coaxial cable connector, a telephone cable connector, or the like. For example, in some embodiments Signal Source 1 10 comprises an interface configured to receive a digitally encoded signal from a power line communication system in which data and electrical power are transmitted over the same conductors. An example of such an interface is provided in the U.S. patent applications cited elscw here herein. Signal Source 1 10 is configured to pro\ ide a signal in the form of a current or a voltage to Programmable Gain Amplifier 120. This current or voltage may be differential or single-ended. The signal optionally includes digitally encoded data. [0034] Programmable Gain Amplifier 120 is optionally configured to receive the signal from Signal Source 110 and to amplify the signal. This amplification may include raising or lowering the magnitude of the signal. For example, if the amplification ratio is greater than one, the magnitude will be increased. Likewise if the amplification ratio is less than one. the magnitude of the signal will be decreased. Programmable Gain Amplifier 120 is optionally further configured to provide the amplified signal to Analog to Digital Converter 130. [0035] Analog to Digital Converter 130 is configured to generate a digital value representative of the amplified signal. For example. Analog to Digital Converter 130 may include an 8-bit analog to digital converter configured to generate an 8-bit representation of the amplified signal. Analog to Digital Converter 130 is typically characterized by an input voltage range, a data size (e.g., 8-bit, 16-bit, 24-bit, 32-bit, etc.), a bandwidth, and/or the like. The input voltage range is the range of voltages that correspond to the range in digital output values. For example, if Analog to Digital Converter 130 is characterized by an input voltage range of 0 to 1 Volt, then (in an 8-bit data size) 0 bits on will represent approximately 0 Volts and all 8 bits on will represent approximately 1 Volt. In various embodiments, a wide range of input voltage ranges, including positive and/or negative voltages, is possible. [0036] Programmable Gain Amplifier 120 is optionally programmed to generate a signal within the input voltage range of Analog to Digital Comerter 130. This programming is performed using Control Logic 140 and includes setting su itches within Programmable Gain Amplifier 120. Control Logic 140 includes, for example, hardware, software or firmware configured to set these sw itches. Control Logic 140 is typically responsive to a magnitude of the signal as detected within Programmable Gain Amplifier 120. Analog to Digital Comerter 130. or in other circuits. For example, the digital representation generated by Analog to Digital Converter 130 may be provided to Control Logic 140 wherein the digital representation is processed to determine if switches should be changed. [0037] Control Logic 140 is optionally configured to separately control switches in a Front End 150 and a Back End 160 of Programmable Gain Amplifier 120. For example, Control Logic 140 may be configured to determine an amount of amplification that occurs in each of the Front End 150 and the Back End 160 so as to optimize both signal to noise and linearity of the amplification process. In some embodiments, Control Logic 140 is configured to set switches to achieve the best linearity possible while still maintaining a signal to noise requirement. In some embodiments. Control Logic 140 is configured to set switches to achieve the best signal to noise while maintaining a linearity requirement. In some embodiments, Control Logic 140 is configured to receive information regarding the signal to noise of the signal and change switches accordingly. For example, the output of Analog to Digital Converter 130 may be processed to identify messages encoded there in. When this processing results in uninterprctable data, information indicating that an improved signal to noise may be needed is sent to Control Logic 140. Control Logic 140 may then change switches accordingly.

|0038| Front End 150 comprises a plurality of circuits in parallel. These circuits arc alternatively selectable to be within a signal path from an input of the Front End 150 to an output of the Front End 150. One or more of these circuits will be in the signal path at a time. These circuits may include amplifiers, followers, or the like. For example, in

embodiments these circuits include a plurality of transconductors. Transconductors are circuits configured to receive a voltage and generate a current proportional to lire received voltage. Transconductors are characterized by a transconductance (g) which is a ratio of a current I at an output to a voltage V at an input. Transconductance can be represented by the formula g - IΛ\ or in a differential mode g = J//J V. Topically, each transconductor within Front End 150 is characterized by a different transconductance. The transconductors may also be characterized by different input ranges. For example, one transconductor may be configured to receive signals between 0 and 1 Volt while another of the transconductors is configured to receive signals between 0 and 4 Volts. Optionally the transconductance of these circuits is approximately proportional to the size of the input ranges for which they are optimized. For example, the transconductance of the transconductor having a 0-4 Volt range may be ¹A the transconductance of the transconductor having a 0-1 Volt range. As a result, the currents they generate over their input ranges will be approximately the same. Front End 150 may be configured in a differential mode or a single-ended mode. [00391 The output of Front End 150 is received by Back End 160. For example, where Front End 150 comprises a set of transconductors in parallel, Back End 160 is configured to receive the current generated by the selected member or members of the transconductors . Back End 160 comprises a plurality of selectable current-mode gain stages. These current mode gain stages are each configured to receive a current and generate a proportional output current. The ratio of the input current to the output current is referred to herein as the gain. When the output current is greater than the input current the gain is greater than one. [0040J The gain of the Back End 160 is the product of the gain of each of the current-mode gain stages. The gain of the Back End 160 is programmable by selecting which of the current mode gain stages are included in a signal path between an input of the Back End 160 and an output of the Back End 160. This selection is typically made by setting switches included in Back End 160. The current gain stages may have gains less than, equal to, or greater than one.

[0041] The Back End 160 may be configured in a differential and/or single-end configuration. For example, each of the current mode gain stages may be differential or single-ended. If Front End 150 is configured in a differential mode, Back End 160 may comprise a series differential mode current gain stages, or two parallel series of single-end current gain stages. In some embodiments Back End 160 comprises a mixture of differential and single-end current gain stages.

[0042] Back End 160 optionally further comprises a current to voltage converter configured to convert a current output of a final current gain stage from a current to a voltage. This current to voltage converter optionally includes resistors from each of the outputs to a low- impedance node such as ground, or a resistor between differential outputs. [0043] As discussed elsewhere herein, Programmable Gain Amplifier 120 is programmable to generate an output that matches the input range of Analog to Digital Converter 130. In selecting a total gain of Programmable Gain Amplifier 120, gross steps in gain (and, thus, amplification) are typically made using Front End 150 and fine steps in gain are made using Back End 160. For example, in some embodiments the differences in transconductance of transconductors within Front End 150 are on the order of 18 dB while the difference in gain of Back End 160 that can be achieved by setting switches to include various members of the current gain stages in the signal path are on the order of 6 dB or less. A gross step is defined as a step that ϊs larger than a fine step. The fine steps may be less than 1/2, 1/3, 1/4, 1/5, 1/7 or 1/8 of the gross steps. [0044] FIG. 2 illustrates further details of Programmable Gain Amplifier 120 comprising a Front End 150 and a Back End 160. according to various embodiments of the invention. In these embodiments. Front End 150 comprises a plurality of Transconductors 210, individually labeled 210A, 210B ... 2 ION. One or more Transconductors 210 may be placed in a signal path between an Input 215 and an Output 220 of Front End 150. This placement is controlled b> Switches 225, individually labeled 225A, 225B ... 225N. Front End 150 may comprise 2, 3, 4 or more pairs of Transconductors 210 and Switches 225. In some embodiments only one of Switches 225 is closed at once. For example, to include Transconductor 210B in the signal path Switch 225B is closed and the other Switches 225 are opened. In alternative embodiments, Switches 225 are disposed between Input 215 and Transconductors 210 rather than between Output 220 and Transconductors 210 as shown. In still other embodiments, more than one of the Switches 225 are closed at once. In these embodiments the transconductance of the Front End 150 is the sum of the transconductances of the Transconductors 210 placed in parallel in the circuit. [0045] For example, in various embodiments the transconductances of successive Transconduclors 210 differ by a same amount, for example, 6dB. Other suitable differences between successive Transconductors 210 in the Front End 150 include 12dB, 18dB, 24dB, or 3OdB. The term "step" is used herein to refer to the transconductance difference between successive transconductors. The transconductances may include values less than, equal to, and greater than one. Typically, each of Transconductors 210 is optimized to receive signals of a specific voltage range and to introduce a minimal amount of noise and/or distortion into the signal at this voltage range. Transconductors 210 optionally also differ in their frequency response or include a tunable frequencj response. In some embodiments, the gain contribution steps within Front End 150 are different. For example, Transconductor 210A mav contribute -10 dB. Transconductor 2K)B may contribute 2 dB and Transconductor 210N may contribute 10 ciB. Here, the first gain contribution step is 12 clB while the second gain contribution step is 8 clB.

[0046] In the embodiments illustrated in FIG. 2 Back End 160 comprises a plurality of Current Gain Stages 230, individual I) labeled 230A. 23OB ... 230N. Switches 235 are used to control which of Current Gain Stages 230 are included in a signal path between an Input 240 and an Output 245 of Back End 160. Back End 160 may comprise 1, 2. 3, 4 or more (N) Current Gain Stages. One, two or more of Current Gain Stages 230 may be included in the signal path at the same time. For example, if Switches 235B, and 235E are closed while Switches 235A, 235C, 235D ... and 235N are open, then Current Gain Stages 230B ... 230N. but not 230A will be included in the signal path.

[0047] Each of the Current Gain Stages 230 in the Back End 160 may have the same or different gain than the others. For example, in some embodiments, each of Current Gain Stages 230 has a gain of 6 dB. In some embodiments, some members of Current Gain Stages 230 have a gain of 6 dB while other members have a gain of 3 dB. Other gains are included in alternative embodiments, however, in most embodiments the gains of the Current Gain Stages 230 are smaller than the differences in transconductance between Transconductors 210. For example, if the difference in transconductances between successive Transconductors 210 is 18 dB, the gain of Current Gain Stages 230 may be 1 , 2, 3, 6, and/or 9 dB. In some embodiments, a last of the Current Gain Stages 230, e.g., Current Gain Stage 23ON is configured such that it is always included in the signal path. See FIG. 2. In these embodiments, this last Current Gain Stage 230N is configured to provide the output of Back End 160. For example. Current Gain Stage 23ON may be configured to provide a current suitable for conversion to a voltage within the \oltage input range of Analog to Digital Converter 130. By always including Current Gain Stage 230N in the signal path, output characteristics such as capacitive load, output impedance, and inductance may be held constant as the gain of Back End 160 is varied.

[0048] Optionally, one or more Current Gain Stages 230 within Back End 160 can have a variable gain as described in greater detail below with respect to FIG. 9, For example. Current Gain Stage 23OA contributes 6dB. Current Gain Stage 230B contributes 3dB and Current Gain Stage 23ON selectively contributes 0. 1 or 2dB. Thus, Back End 160 prov ides gains between 0 and 1 1 dB in steps of 1 dB.

[0049] Back End 160 optionally further comprises a Conversion Circuit 250 configured to convert the current output of Current Gain Stage 230N to a voltage. Conversion Circuit 250 may include a resistor (with resistance R_oul) as illustrated in FIG. 2. Other current to voltage circuits may be found in alternative embodiments.

[0050] The embodiments of Transconductors 210 and Current Gain Stages 230 illustrated in FIG. 2 are single-ended. However, in alternative embodiments. Transconductors 210 and/or Current Gain Stages 230 may be differential. FIG. 3 illustrates Programmable Gain Amplifier 120 comprising a differential mode Front End 150 and a differential mode Back End 160, according to various embodiments of the invention. In the differential mode Transconductors 210 generate two currents as output. The difference between these currents is proportional to the difference between two voltage inputs. Switches 225 are replaced by pairs of switches, labeled 225 and 225'. Likewise Switches 235 are replaced by pairs of switches, labeled 235 and 235'. In the differential mode Current Gain Stages 230 generate two output currents whose difference is proportional to a difference between two input currents. Conversion Circuit 250 optionally comprises a resistor disposed between the outputs of the final Current Gain Stage 23ON.

[0051] In v arious alternative embodiments Front End 150 is differential while Back End 160 is single-ended, or Front End 150 is single-ended while Back End 160 is differential. [0052J FlGs. 4A and 4B illustrate alternative embodiments of Back End 160, according to various embodiments of the invention. In FlG. 4A additional Switches 410 are configured to allow for further control of which members of Current Gain Stages 230 are included in the signal path. The embodiments of Back End 160 illustrated in FIG. 4Aallow for exclusion of Current Gain Stages 230 starting at 23OA by opening Sw itch 235A. closing Switch 235B. closing Switch 235C, closing Switch 410A and opening switch 410B, and next excluding Current Gains Stages 230A and 230B by opening Switch 235B, closing Sw itch 235D and Switch 410B. This exclusion from the left to right (as illustrated) can be stepped through Back End 160 by closing successive switches until only Current Gain Stage 230N is included in the signal path. The embodiments illustrated in FIG. 4A further allow for exclusion of Current Gain Stages 230 without necessarily starting at one end of Back End 160. For example, opening Switch 410A, 235C and closing of 235A, 235B, and 410B result in the inclusion of Current Gain Stage 230A and exclusion of Current Gain Stage 230B. Switches 410A, 410C ... 410N may likewise be used to exclude individual Current Gain Stages 230. Addition of further switches to the embodiments illustrated in FIG. 2 would allow stepwise exclusion of Current Gain Stages 230 from either the left to the right or the right to the left. [0053] FIG. 4B illustrates embodiments of Back End 160 in which some of Current Gain Stages 230 are single-ended while others of Current Gain Stages 230 are differential. Specifically, Current Gain Stages 230A, 23OB, etc. and 23OA', 230B', etc. are single-ended while Current Gain Stage 230N is differential. While the example illustrated shows the last Current Gain Stage 230N as being differential, other combinations of differential and single- ended Current Gain Stages 230 may be included in alternative embodiments. [0054] FlGs. 5A and 5B each illustrate a matrix of programmable gains possible using the front end and the back end, according to various embodiments of the invention. These matrixes illustrate how various combinations of front end gain and back end gain can be used together to produce a total gain of Programmable Gain Amplifier 120. For example. FlG. 5 A shows three possible total gain contributions (OdB, 6dB and OdB) for Back End 160. In v arious embodiments, these values ma) be achieved b} opening and closing Switches 235 to include and exclude Current Gain Stages 230 from the signal path. Specifically these values could be obtained if Current Gain Stage 230N had a current gain of 0 dB, Current Gain Stage 230B had a current gain of 6dB and Current Gain Stage 230A had a current gain of 6 dB. FIG. 5A also shows four possible gain contributions (0 dB. 18 dB, 36 dB, 54 dB) contributed by Front End 150. These values can be obtained if Transconductor 210A contributes 0 dB to the total gain of Programmable Gain Amplifier 120, Transconductor 210B contributes 18 dB to the total gain, Transconductor 210C (not shown) contributes 36 dB to the total gain, and Transconductor 210N contributes 54 dB to the total gain.

[0055] The total gain of Programmable Gain Amplifier 120 may be stepped between different Gain States 510 as illustrated by the Arrows 520 shown in FIG 5A. For example, gain may be changed in steps of 6 dB by follow ing the path of Arrows 520. If required, transitions between gain states may take other paths. For example Programmable Gain Amplifier 120 may be changed from a Gain State 51OA that includes 12 dB back end gain and 18dB front end gain to a Gain State 510B that includes 6 dB back end gain and 54dB front end gain.

[0056] FIG. 5B illustrates embodiments in which the programmable gains that can be achieved by changing the gain contributed by Back End 160 overlap with the gains that can be achieved by changing the gain of Front End 150. For example, a Gain State 510C and a Gain State 510D both provide approximately a total of 36 dB gain. Such ov erlapping gains may be advantageous when changing gain contribution in one of Front End 150 or Back End 160 is easier or creates less noise that changing the other. [0057] FlG. 6 illustrates various programmable gain contributions within Back End 160. according to various embodiments of the invention. The x-axis represents the gains (8. 4, 2, and 0 dB) of four different Current Gain Stages 230. By including the appropriate Current Gain Stages 230 within the signal path, total gain contributions of Back End 160

be selected from 0, 2. 4, .... 12, and 14 dB. The optional gain stage having 0 dB may or may not be included in each of the selections. The programmable gains illustrated in FlG. 6 may be achieved using a configuration such as that illustrated in FIG. 4A, where each of Current Gain Stages 230 can be independently selected for inclusion or exclusion in the signal path. In FIG. 6 open circles represent a Current Gain Stage 230 that is excluded from the signal path and black circles represent a Current Gain Stage 230 that is included in the signal path. [0058] FIG. 7 illustrates an example of Transconductor 210. according to various embodiments of the invention. This example includes a differential transconductor comprising two Voltage Inputs 710p and 71On configured to receive voltages V_mp and V_111n, respectively, and two Current Outputs 715p and 715n through which currents I_outn and I_outp are provided, respectively. The difference between the Current Outputs 715p and 715n is proportional to the difference between the Voltage Inputs 71Op and 710n. Briefly, this embodiment of Transconductor 210 operates by copying the voltage difference between V_inp and V₁₁₁₁₁ across a Resistor 720 having resistance R₇₂o- As a result of this voltage difference, a current I_R72O = (V_mp - V_mn)/R₇₂o flows across Resistor 720. This current results in a difference between the output currents I_outn and l_oυtp. The transconductance of Transconductor 210 is determined by, for example, a value of the resistance R₇₂o and the ratio of current sources discussed elsewhere herein. Transconductors 210 of the type illustrated by FIG. 7 characterued by a transconductance that is inversely proportional to the resistance of a Resistor 720 arc also referred to herein as Type- 1 Transconductors 210. [0059] More specifically, the embodiments of Transconductor 210 illustrated in FIG. 7 are optionally operated as follows. Transconductor 210 is biased by setting Current Sources 725p. 725n, 73Op and 730n such that the currents

ided by 725p and 725n are equal, and the currents provided by 730ρ and 73On are equal. In addition the following relation is held I~_25p/Ho_p

i(t_p) = M, where I₇I_Sp is the current provided by Current Source 725p,

and L-π₅₍₁ are the width and length of a Transistor 735p, W~4o_p and L-4o_p are the width and length of a Transistor 74Op and M is a positive fractional number. The Transconductor 210 is symmetric in the sizes of transistors on either side of Resistor 720. As such, Transistors 735n and 74On are governed by the same relationship.

[0060] Transistors 745p and 745n are configured to operate as source followers and as such copy the voltages V,_np and V_mn minus a constant voltage to their sources, which are disposed on either side of Resistor 720. Because the gate-source voltage is the same for Transistors 745p and 745n, the difference in voltages at the sources of these transistors is the same as the difference in voltages at their gates. As a result, an excess current (V_mp - Vj_0n)ZR₇Io flows across Resistor 720. This excess current must flow through Transistor 74Op, and a current of the same magnitude but opposite sign (polarity) flows through Transistor 74On. These currents are generated by two local gain loops. The first of these loops comprises a Transistor 75Op, a Transistor 755p, Transistor 74Op and Transistor 745p. The second of these loops comprises a Transistor 750n, a Transistor 755n, Transistor 74On and Transistor 745n. Nodes 760p and 76On are high-impedance nodes which amplify any variation of voltage on the sources of Transistors 745p and 745n. respectively. The voltages at Nodes 76Op and 760n are converted to currents by Transistors 75Op and 750n. These currents are fed back by a current mirror comprising Transistors 755p and 740p. and a current mirror comprising Transistors 755n and 740n. As a result of this negative feedback the input voltage difference V_mp - V₁₁₁₁₁ is copied across Resistor 720.

[(WMIj Because Transistors 735p and 74Op have the same gate-source \ oltage, and because as is described elsewhere herein

the ratio of their drain currents is I_<i_ram735p I IdramT-tftp = Hsp / I:>o_{>- Using Kirchhoffs Current Law the current I?25p

+ Solving these equations yields that the cuiτcnt [I_vHi_m| must equal the current I_R7JH through Resistor 720. A similar set of relations hold for the other side of Transconductor 210. Note, however, that I_outp = - I_outn- The transfer function of Transconductor 210 illustrated in FIG. 7 is Io_Utp - I_0111n = 2 M (V_111n - V_inp)/R₇2o. Thus, its differential transconductance is defined as

[0062J In most IC fabrication processes, the resistance of resistors is not well controlled and can vary by as much as 45% or more between different fabrication lots. Thus, the transconductance of a Type-1 Transconductor 210 may also vary. However, the total gain of the Programmable Gain Amplifier 120 may be well controlled if the Back End 160 has a voltage-to-current Conversion Circuit 250 at the output, as illustrated in FIGs. 2, 3, 4 A. and 4B, based on a resistor which is built using one or more copies of the same unit resistors which make up Resistor 720, or is fabricated of the same material as Resistor 720. In that case, the total gain of the Programmable Gain Amplifier 120 is proportional to g_miR_0Ut, ^or equivalently. proportional to R_t)Ul/R72o- Since Conversion Circuit 250 and Resistor 720 are built with copies of the same unit resistor, or with resistors of the same material, the resistance change due to a variation of the fabrication process does not alter the ratio of their resistance. In other words, a total gain of the Programmable Gain Amplifier is independent of fabrication process variations which may affect the resistance of Resistor 720. FIGs. 1OA and 1OB, discussed below, illustrate two different embodiments of variable resistance Resistors 720. [0063 J FIG. 8 illustrates another possible embodiment of a Transconductor 210. In this case, the transconduetance of Transconductor 210 is proportional to the transconductance (g_m) of Input Transistor 855n or Input Transistor 855p, which arc commonly sized equal. Transistors 84Op, 840n. 845p, 845n and 850 are used to bias input Transistors 855ρ and 855n. Transconductofs 210 of the type illustrated by FIG. 8 characterized by a transconductance that is proportional to the transconductance of a transistor are also referred to herein as Type- 2 Transconductors 210.

[0064] More specifically, a voltage input difference (V_mp-V_mn) creates a current difference l_omp-I_oum = g_m2 (V_mp-V,_nn), with g_m2 equal to the transconductance g_m of Input Transistors 855n and 855p. By definition, g_m2 is the transconductance of this embodiment of Transconductor 210. The transconductance of Input Transistors 855n and 855p depends on the current flowing through them. The total current flowing through the Input Transistors 855n and 855p is generated by Transistor 850 in response to a voltage V_clrl at its gate. The higher the current through Transistor 850, the higher the transconductance g_m of Input Transistors 855p and 855n. and thus the higher the transconductance g_mi of the Transconductor of FIG. 8.

[0065] Transistors 84Op and 845p form a Current Source which supplies a current approximately equal to half the current flowing through Transistor 850. Transistors 84On and 845n are commonly sized equal to 84Op and 845p, respectively. The input-dependent current from Transistor 855p and Transistor 855n are subtracted from the bias currents from 845p and 845n, respectively, at nodes 830p and 83On. When a low input-impedance circuit such as Current Gain Stages 230 follows the circuit of FIG. 8, the excess differential current on nodes 83Op and 83On will flow into Current Gain Stage 230.

[0066] A Transconductor 210 such as that of FIG. 8, or other possible embodiments of Transconductor 210 having a transconductance that is directly based on the transconductance of one or more transistors, is typically better suited to high-gain and low-noise gain configuration, whereas resistor-based Transconductυrs 210 , such as that of FIG. 7, may be better suited to low-gain and high-linearity configurations.

[0067J FIG. 9 illustrates an example of a Current Gain Stage 230, according to various embodiments of the invention. This example is single sided and comprises one Current Input 910 and one Current Output 915. This circuit operates on the same local gain loop principle as the circuit illustrated in FIG. 7.

[0068] More specifically, a Current Source 920 and a Current Source 925 are biased such that their respective currents føo and I92₅ are related by I920/I925 = (W930/L930) / ( W₉₃₅ZL)₃₅ )=N, where W₉₃₀ and L₉₃₀ are the width and length of a Transistor 930,

and L₉₃₅ are the width and length of a Transistor 935 and N a positive fractional number. A Transistor 940 is a common-gate input with a fixed gate bias V_b,_as. A Node 945 is a high-impedance node configured to amplify any variation of voltage on the source of Transistor 940. The voltage at Node 945 is converted into a current by a Transistor 950 and fed back to the Current Input 910 using a current mirror comprising a Transistor 955 and a Transistor 935. As a result of this negative feedback loop, the voltage on the source of Transistor 940 is kept essentially constant for the range of possible currents provided through Current Input 910. A fixed bias current I₉₂₅ therefore flows through Transistor 940. The drain current through Transistor 935 is therefore the sum of the current I₉₂₅ and the input current provided through Current Input 910. As Transistors 935 and 930 have the same gate-source \oltage, their drain currents (Lns and I₉ ^o respectively) have the relationship LM_O = i{WιnoZLc)₃o) I (Wi)₃₅ZLt)₃₅)J L^₅, or equivalentlyIdiaιn9H) = Nljramw- Again, applying Kirchhoff's Current Law one derives that Im₅ = Nk>ιo. which is the transfer function for the illustrated circuit. Thus, N is also equal to the current gain of the circuit. [0069] By selectively changing the fractional number N it is possible to change the current gain of Current Gain Stages 230. Commonly. Transistor 935 and Transistor 930 are made up of multiple parallel copies of a smaller unit transistor. Accordingly, Transistor 935 can consist of K parallel copies of the unit transistor and Transistor 930 of J parallel copies of the unit transistor, where J and K are integer numbers. Thus, Transistors 930 and 935 have the same length but the ratio of their widths is J/K. The drain current ratio of two transistors of the same length but different widths driven by the same gate-to-source voltage equals the ratio of their widths. Thus,

Therefore, as explained elsewhere herein J/K = N = It) ₁₅/lQ _K). The value of J and K can be varied by switching in and out of the signal path copies of the unit transistor. Thus, the gain of a Current Gain Stage 230 can be varied by selectively switching in and out some unit transistors from the plurality of unit transistors of compound Transistors 930 and 935. If the widths of Transistor 930 and 935 are changed currents I₉₁₅ and I910 should be changed accordingly so that the equality N = I9₁₅/I9K) is maintained.

[0070] Transconductors 210 are also subject to other control schemes. In some embodiments, Type-1 Transconductors 210 may include circuits such as those provided by FIGs. 1OA and 1OB which illustrate different embodiments of variable resistance Resistors 720. Switches 1020 (FIG. 10A) and 1040 (FIG. 10B) are controlled by control circuitry (not shown). The effective resistance of either Resistor 720 is achieved by choosing to switch in or out of the signal path some Resistors 1035 in a series (FIG. 10B) or some Resistors 1015 in a parallel arrangement (FIG. 10A). FIGs. 1OA and 1OB illustrate just two of the possible ways to implement a variable Resistor 720. Optionally, a combination of series and parallel paths may be used, for example. Other possible embodiments of variable Resistor 720 can include active resistances implemented with transistors biased in the ohrnic region. [00711 FIG. 11 illustrates a method I KX) of processing a signal, according to various embodiments of the invention. In method 1 100 a signal is received and measured, a Programmable Gain Amplifier 120 is configured based on the measurement, and then the signal is amplified by the Programmable Gain Amplifier 120. Configuring the Programmable Gain Amplifier 120 can include selecting a suitable gain to be applied to the received signal such that the amplified signal is matched to an input characteristic of a subsequent circuit, such as Analog to Digital Converter 130. The method 1 100 can also include processing the signal with the subsequent circuit.

[0072] In a Receive Signal Step 11 10, a signal is received, for example from a Signal Source 110. The received signal may comprise a magnitude in a known (predictable) or unknown (unpredictable) range. For example, if the signal is received via an antenna, variable length conductor, or the like, the magnitude of the signal may be attenuated by an unpredictable amount before it is received. The received signal optionally comprises digitally encoded data. The received signal optionally comprises a modulated voltage or current. [0073] In an optional Determine Magnitude Step 1 120, information about the magnitude of the received signal is determined. This information may comprise an absolute value of the magnitude of the signal, while in other embodiments the information comprises a comparative value such as that the magnitude of the signal is below, within, or above a set voltage or current magnitude range. Determine Magnitude Step 1 120 may include applying the signal to a comparator, digitizing the signal, or making some other measurement of the signal. The voltage or current magnitude range against which the signal magnitude may be compared can be. in some embodiments, an input range for a subsequent circuit like Analog to Digital Converter 130.

10074) In some embodiments Determine Magnitude Step 1 120 is performed by Control Logic 140 (FIG. 1 ). Optionally, Control Logic 140 may contain an automatic gain control circuit that Ls configured to determine the magnitude of the signal, or a training signal, through the use of an algorithm that characterizes the signal according to a parameter such as peak. RMS, histogram, threshold, amount of clipping, frequency analysis, combinations thereof, etc. Control Logic 140 and the automatic gain control may be responsive to a signal at the input, the output or one or more points inside of PGA 120.

[0075] In a Set First Switch Step 1 130, one or more Switches 225 w ithin Front End 150 are set to select one or more of Transcondiictors 210 to be included in the signal path of Front End 150. The set Switches 225 may be set to a default setting or to a setting in response to the information determined in Determine Magnitude Step 1 120. For example, if the information includes that the signal has a voltage magnitude greater than an optimal input voltage range of Transconductor 210A, then Switches 225 may be set for Transconductor 210B (or some other appropriate member or combination of Transconductors 210) to be included within the signal path of Front End 150. The setting of Switches 225 will result in a current path through Front End 150 that includes one or more Transconductors 210. Set First Switch Step 1130 is optionally performed using Control Logic 140. [0076] In a Generate First Current Step 1140, a first current is generated using the Transconductors selected from the plurality of Transconductors 210 selected in Set First Switch Step 1130. This current is typically related to the magnitude of the received signal. For example, the generated current may vary proportionally with the received voltage, the proportionality constant being the sum of the one or more selected transconductances from the plurality of Transconductors 210. The magnitude of the generated current is dependent on which of the Transconductors 210 was selected using Switches 225. The generated current is provided to the Output 220 of Front End 150.

[0077] In a Set Second Switch Step 1 150, one or more Switches 235 within Back End 160 are set to select which of Current Gain Stages 230 are included in the signal path Vvithin Back End 160 and. thus, select a gain of Back End 160. The set Switches 235 and set Switches 410 ma) be set to a default setting or a setting in response to the information determined in Determine Magnitude Step 1 120, HGs. 5A, 5B, and 6 illustrate some possible gain states of Front End 150 and Back End 360. Optionally, the gain of Back End 160 is selected to modify the output of Front End 150 to better match input characteristics of subsequent circuits. For example, the gam of Back End 160 may be selected to match an input range of Analog to Digital Converter 130. The setting of Switches 235 and Switches 410 may result in a signal path that includes all of the Current Gain Stages 230, in a signal path that includes one or more of Current Gain Stages 230 but not others of Current Gain Stages 230, or a current path that includes none of Current Gain Stages 230. Set Second Switch Step 1150 is optionally performed using Control Logic 140.

[0078] In a Generate Second Current Step 1 160, Back End 160 is used to generate a second current proportional to the current generated using Front End 150 in Generate First Current Step 1140. This current may be generated by passing the output of Front End 150 through some but not others of Current Gain Stages 230.

[0079] In an optional Convert Second Current Step 1 170, the current generated in Generate Second Current Step 1160 is converted to a voltage using Conversion Circuit 250. This optionally includes passing the current through a resistor.

[0080] In an optional Generate Digital Value Step 1180, the signal received via Front End 150 and Back End 160 is converted to a digital value, for example using Analog to Digital Converter 130. This digital value may be 8-bit, 16-bit, 24-bit, 32-bit or some other data size. The digital value is optionally provided to Control Logic 140. Control Logic 140 may use this value as feedback to set Switches 225 and/or Switches 235.

[0081] The order of steps illustrated in FIG. 1 1 may be different in other embodiments. For example, in some embodiments Set First Switch Step 1 130 and Set Second Switch Step I J 50 are performed in parallel or subsequent to each other. Likewise, if Switches 225. 235 and 410 are initially set to default values, then these steps may occur for the first time before a signal is recehed. The method illustrated m FIG. 1 1 may be repeated. For example, during reception of a signal, if the intensity range of the signal varies, then Programmable Gain Amplifier 120 may be reprogrammed dynamically. Further, the method may be performed repeatedly in an iterative process until switch settings appropriate to the received signal are found. Viewed as a dynamic process, method 1100 can alternatively be viewed as comprising at least a step of measuring a change in the magnitude of a signal, and a step of changing a configuration of a Programmable Gain Amplifier 120 in response to the change in the signal magnitude.

[0082] In some embodiments, by separately selecting those elements of Front End 150 and Back End 160 through which the signal passes, each total gain state of Programmable Gain Amplifier 120 can be set to an optimal point for the trade-off between linearity and signal-to- noise ratio. For example, for a large input signal linearity is typically more critical than low noise. For these signals a relatively low transconductance, e.g., Transconductor 210A, is selected in Front End 150. For smaller input signals, a larger input transconductance, e.g., Transconductor 210N, is used in Front End 150 and more of the total gain is applied in Front End 150. This tends to minimize noise.

[0083] Several embodiments are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations are co\ered by the above teachings and within the scope of the appended claims without departing from the spirit and intended scope thereof. For example, while the embodiments discussed herein comprise a back end in which amplification occurs in a current mode, in alternative embodiments the front end is configured to output a voltage and the back end is configured to amplify in a \oltage mode. While the Programmable Gain Amplifier 120 is described herein as being used to amplify a signal prior to being received by Analog to Digital Converter 130, the Programmable Gain Amplifier 121) may be used in other applications wherein programmable amplifiers are used, lα some embodiments, a variable amplifier is included in the front end and/or back end. The terms first and second, etc. as used as adjectives in the claims are not meant to particular physical ordering, rather they are meant merely to distinguish elements. In embodiments wherein the signal received by Programmable Gain Amplifier 120 is in a current mode, the parallel Transcouductors 210 of Front End 150 may be replaced by parallel current gain stages similar to Current Gain Stages 230.

[0084] The embodiments discussed herein are illustrative of the present invention. As these embodiments of the present invention are described with reference to illustrations, various modifications or adaptations of the methods and or specific structures described may become apparent to those skilled in the ait. All such modifications, adaptations, or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the spirit and scope of the present invention. Hence, these descriptions and drawings should not be considered in a limiting sense, as it is understood that the present invention is in no way limited to only the embodiments illustrated.

Claims

What is claimed is: J . A svstem comprising: a programmable gain amplifier including a front end having a plurality of selectable transconductors arranged in parallel; a back end configured to receive an output of the front end and having a plurality of selectable current gain stages arranged in series; and a control circuit configured to change a gain of the programmable gain amplifier by selecting a transconductor in the front end or by selecting a current gain stage in the back end.

2. The system of claim 1, wherein the front end is configured to operate in a differential mode.

3. The system of claim 1 or 2, wherein the back end is configured to operate in a differential mode.

4. The .system of claim 1, 2. or 3 wherein the output of the front end is a current output and the back end K further configured to produce a voltage output.

5. The s\stcm of claim 1-3 or 4. wherein a trunsconductor of the plural it v of selectable transconductors includes a transistor and wherein a transconductance of the lransconductor is proportional to a transconductance of the transistor. (^■>. The system of claim 1 -4 or 5. wherein a iransconductor of the plurality of selectable traiisconductors includes a resistor and wherein a transconductanee of the transcondυctor is dependent on a resistance of the resistor.

7. The system of claim 1-5 or 6. wherein a transconduetor of the plurality of selectable transconductors includes a variable resistance resistor and wherein a transconductanee of the transconduetor is dependent on a resistance of the \anable resistance resistor.

8. The system of claim 7. wherein the variable resistance resistor includes a plurality of selectable resistors in parallel.

9. The system of claim 7, wherein the \ ariable resistance resistor includes a plurality of selectable resistors in series.

10. The system of claim 1 -8 or 9 wherein a current gain stage of the plurality of selectable current gain stages has a variable gain.

1 1. The system of claim 10 wherein the current gain stage includes a transistor comprising parallel selectable copies of a smaller unit transistor, wherein a gain of the current gain stage is a function of the number of selected unit transistors.

12. The system of claim 1-lO or I l wherciα the plurality of selectable transconductors in the front end comprises a first transconductor configured to receive a voltage and generate a current proportional to the voltage received by the first iransconducior, a second transconductor in parallel with the first transconductor and configured to receive a voltage and generate a current proportional to the voltage received by the second transconductor, and a switch configured to create a signal path from an input of the front end to an output of the front end through alternatively the first transconductor or the second transconductor.

13. The system of claim 1-11 or 12 wherein the plurality of selectable current gain stages in the back end comprises a first current gain stage configured to receive current from the front end and to generate a current proportional to a current received from the front end, a second current gain stage in series with the first current gain stage, configured to receive current via the first current gain stage, and configured to generate current proportional to the current received by the second current gain stage. and a switch configured to select whether or not the second current gain stage is included in a signal path from an input of the back end to an output of the back end.

14. The system of claim 1- 12 or 13, wherein the gain of the second transconductor is at least

10 dB greater than the gain of the first transconductor.

15. The system of claim 1-13 or 14, wherein the first current gain stage is configured to amplify current by a different amount than the second current gain stage.

16. The s) stem of claim 1 -14 or 15, v\ herein the back end further comprises a circuit configured to convert a current output of a final current gam stage to a voltage.

17. The s) stem of claim 1-15 or 16, wherein the control circuit is configured to change the gain of the programmable gain amplifier by selecting the transconductor in the front end or by selecting the current gain stage in the back end responsive to a magnitude of a signal received at an input of the front end.

18. The system of claim 1-16 or 17, further comprising an analog to digital converter configured to receiv e an output of the back end.

19. The system of claim 1-17 or 18, further comprising a signal source configured to provide a signal to the front end.

20. A method comprising: creating a first signal path through a front end of a programmable gain amplifier by setting switches to select a transconductor of a plurality of selectable transconductors: and creating a second signal path through a back end of the programmable gain amplifier by setting switches to select a current gain stage of a plurality of selectable current gain stages.

21 . The method of claim 20. further comprising receiving a signal and amplify ing the signal passing the signal through the first and second signal paths.

22. The method of claim 21 , further comprising determining a magnitude of the signal, wherein creating the first and second signal paths is responsive to the magnitude.

23. The method of claim 21, further comprising passing the amplified signal through an analog to digital converter.