WO2010084083A1

WO2010084083A1 - A time-digital converter and an electronic system implementing the converter

Info

Publication number: WO2010084083A1
Application number: PCT/EP2010/050440
Authority: WO
Inventors: Salvatore Levantino; Carlo Samori; Marco Zanuso
Original assignee: Politecnico Di Milano
Priority date: 2009-01-23
Filing date: 2010-01-15
Publication date: 2010-07-29
Also published as: ITMI20090077A1

Abstract

A time-digital converter (100) comprising: an adjustable delay device (D1; DN) for generating a delayed signal (S₁) provided with a delay adjusting input (5), and an arbiter device (FF1) for receiving the delayed signal and a reference signal (S_o) on corresponding inputs and for supplying an output signal (S_D1) to an output (O1) indicative of a relative timing of the signals at its inputs. The converter further comprises: a calibration delay device (D_bm) for supplying the reference signal to the arbiter device, and a calibration filter (F1) connectable to said output (O1) for providing input (5) of the adjustable delay device with a delay adjusting signal (S₂₁) depending on the output signal of the arbiter device.

Description

"A time-digital converter and an electronic system implementing the converter"

Technical field of the invention

The present invention relates to the time- digital converters field, and in particular, it relates to linearization techniques for these converters .

Prior art

Document US-A-2007/0273569 discloses two types of time-digital converters comprising a plurality of delay cells (i.e. phase shifters) and a plurality of D- type flip-flops, which, driven by a suitable signal, act like a time regulator, i.e. making a decision about which of the signals at the input has switched first. According to the decision signals, an output coder returns a digital code, representative of the signal duration which has converted. In this prior art document in the opening part a series type cell- linking mode is disclosed and a converter in a parallel cell-linking mode is proposed.

The converters, such as those above mentioned, have performances critically dependent on mismatch, either structural or due to degrading over the time, which can make delays and/or delay differences, introduced by the cells, not correspond to those chosen when designing. Such phenomena lead to a linearity of the conversion characteristic, to which an unsatisfactory quality of the time-digital conversion can correspond.

Calibration techniques are known, aimed to correct the non-linearities by reducing the mismatch introduced by the delay cells. As regards this, the article by T. Hashimoto et al . "Time-to-Digital Converter with Vernier Delay Mismatch Compensation for High Resolution On-Die lock Jitter Measurement", Digest of Tech. Papers of IEEE Symp. on VLSI Circuits, 2008, pp.166-167 discloses a vernier delay line-based converter. According to the article, every delay cell is alternatively closed in a ring oscillator, whose oscillation frequency is measured and then the oscillation frequencies of the oscillator are required to be the same when the delay cell included in the ring changes .

The article by Weltin-Wu et al . "A 3GHz Frac- tional-N All-digital PLL with precise Time-to-Digital Converter Calibration and Mismatch Correction", Digest of Solid-State Circuits Conference, 2008, ISSCC 2008, February 2008, pp.344-618 discloses a technique, that provides a "code density test" statistical measure, of the converter behaviour. By means of this test, the non linearity of the conversion characteristic is assessed and subsequently a correction is carried out based on the estimated characteristic.

The article by K. Nose et al. "A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling", IEEE J. of Solid-State Circuits, Vol. 41, No. 12, December 2006, pp. 2911-2920 discloses a feed-forward calibration technique, which tries to equalize the delays on a vernier delay-line.

Brief summary of the invention

The applicant has observed that the apparatuses and the calibration techniques of the known time- digital converters are not satisfactory in terms of manufacturing and implementation complexity, and in terms of speed and effectiveness either. It is the object of the present invention to propose a calibration technique, which has a satisfactory effectiveness and an acceptable complexity. The present invention relates to a time-digital converter as defined in the annexed claim 1 and by preferred embodiments thereof disclosed in the dependant claims 2 to 13.

It is a further object of the present invention an electronic system defined in the annexed claim 14 and by its preferred embodiment disclosed in the dependant claim 15.

Brief description of the drawings

Further features and the advantages of the invention will be evident from the following description of a preferred embodiment and variants thereof provided as a way of example, with reference to the appended drawings, wherein:

- Figure 1 schematically shows an example of an electronic system comprising a time-digital converter, according to the present invention;

- Figure 2 shows, by means of functional blocks, a first preferred embodiment of the time-digital converter;

- Figures 3A, 3B and 3C show diagrams of the parameters INL and DNL under three different simulation conditions;

- Figure 4 shows, by means of functional blocks, a second preferred embodiment of the time-digital converter .

Detailed description of the invention

Structural description

In referring to Figure 1, an example of an electronic system 400 is shown, such a Phase Locked Loop PLL, comprising a time-digital converter 100 and usable, for example, for the frequency synthesis in radio systems. In particular, the electronic system 400 represented in Figure 1 further comprises a digital filter 200, for generating a frequency control signal, connected to the output of the time-digital converter 100, and a digitally controlled oscillator 300 (DCO) . The time-digital converter 100 is provided with a first input 1 for signal to be phase locked and a second input 2, that, in this specifically described case, is adapt to receive a feedback signal provided by the current controlled oscillator 300 and such to equalize the signal phase at the first input

1. The time-digital converter 100 provides an output digital code representative of the signal time delay at the first input 1 in respect to the second input

2. The digital filter 200 according to the received signal returns the frequency control signal which suitably drives the digitally controlled oscillator 300.

The time-digital converter 100 is usable, besides the frequency synthesis, also in other electronic systems, such as, for example, analogue-to-digital conversion systems, in particular, but not limited to, for carrying out a digitalization of any voltage signal from a sensor, which has been previously time converted.

Figure 2 shows, by means of functional blocks, a first embodiment of the time-digital converter 100 usable in the electronic system 400 and implemented in a "parallel" mode. The time-digital converter 100 depicted in Figure 2 comprises an input multiplexer

3. a reference delay device D_bm, a plurality of conversion lines Ll-LN and an output encoder 4 provided with a respective output OU.

The time-digital converter 10 has two alternatively assumable operating configurations: a calibration configuration and an operating configuration. According to the example shown, the input multiplexer 3 is provided with the first output 1 for a signal "start" and the second input 2 for a reference signal "stop" and a switching input 13 for a switching signal "cal". The switching signal cal is suitable, for example, for switching between two levels and correspondingly to cause the time-digital converter 100 to switch from the calibration configuration to the operating configuration and vice versa.

Referring now to the first conversion line Ll of the plurality of lines Ll-LN; the same considerations are valid for the other conversion lines L2-LN. The first conversion line Ll comprises a first adjustable delay device or cell Dl, provided with an adjusting input 5, a first arbiter device FFl, a first calibration filter Fl having an output connected to the adjusting input 5, by means of a related adder node

Further, the first conversion line Ll comprises a switch 6 interposed between the first arbiter device FFl and a first filter Fl input and a multiplexer 7 switchable by the switching signal cal.

The adjustable delay device Di is capable of introducing an offset on the input signal, corresponding to a time delay Xi, which has a first term τ₀, ideally the same for all the delay devices D_I-D_N, and a second term kit, which marks it from the delays introduced by the other devices D₂~D_N. The adjustable delay devices D_I-D_N, introduce distinct delays and, for example, increasing when index i increases, which identifies each device. In general, the delay Ti introduced by each delay device D₁ can be expressed as X₁= Xo+kj_x with kj. = 1 , 2, 3 ...; wherein the coefficient ki is distinct according to the particular delay de- vice. The minimum delay difference can be, for example, made equal to about 1 ps .

Each adjustable delay device Dχ-D_N, is made such to enable the adjustment of the respective delay, by modifying the first term to, and, preferably, also the second term kit, by modifying the coefficient k_x . This adjustment of delay can be carried out by a digital signal sent to the adjustment input 5. It is to be observed that, typically, the first term τ₀ is higher than the second term kit. For example the ratio between the first delay term τ₀ and the second delay term kit can be within 10 and 100. According to a particular non-limitative example, the first term τ₀ can assume values within the range 10 ps - 10 ns and the second term can assume values within the range 1 - 100 ps.

The adjustable delay devices D_I-D_N have their own input terminals connected to an output terminal 8 of the input multiplexer 3. Each delay device D_I-D_N can be implemented, for example, in a way known per se, and can include a buffer stage, which drives a plurality of capacitors (or other suitable electric components), which can be connected to or disconnected from the circuit, by relative switches, in order to obtain the desired adjustment of the delay. This kind of delay devices can be implemented, for example, in the CMOS (Complementary Metal Oxide Semiconductor) technology.

The reference delay device D_bm introduces a delay equal to the value, which is desired to be the same for all the first terms to of the delay devices D_I-D_N. The reference delay device D_bm can be, for example, of the fixed type (i.e. not adjustable) and can be im- plemented analogously (unless the delay variability) to the adjustable delay devices D_I-D_N. The reference delay device D_bm has an input connected to the second input 2 of the input multiplexer 3.

The first arbiter device FFl of the first conversion line Ll is provided with a first input 9, connected to the output of the first delay device Di, and a second input 10 connected to an output 11 of the reference delay device D_bm- The signals provided to the first input 9 and to the second input 10 have, for example, the shape of rectangular wave signals, which changes between two levels (0 and 1) .

Moreover, the first arbiter device FFl has a respective output 01, which can be connected and disconnected through the switch 6 to and from the input of the calibration filter Fl. The output Ol of the arbiter device FFl is also connected to an input of encoder 4.

The first arbiter device FFl is made such to provide on its first output 01 a decision signal indicative of a relative timing of the signals to its inputs 9 and 10. In other words, the arbiter device FFl, by operating as a time arbiter, provides a decision signal, which indicates which of the two signals present at the inputs 9 and 10 has switched first from a level to the other.

In particular, the first arbiter device FFl can be implemented through a sampler, which samples the received signal at the first input 9 at the time instants when the signal at the second input 10 switches, for example, from a low value to a high one. As shown in Figure 2, such a sampler can be implemented, in particular, through a flip flop, for example, a D-type flip-flop. The same can be said for the other arbiter devices FF2-FFN, each having a first input 9 connected to the output of the respective adjustable delay device of the plurality D₂-D_N and a second input 10 connected to the output 11 of the reference delay device D_bm- The other outputs 02-ON of the arbiter devices FF2-FFN are connected to the respective inputs of encoder 4, besides (by the corresponding switches 6) the inputs of the respective calibration filters F2- FN.

Each multiplexer 7, which each conversion line Ll-LN is provided with, is such to impose the respective value of coefficient Ic₁ to the corresponding adjustable delay device D₁, in the operating configuration (for example, switching signal cal equal to 0) . According to the particular embodiment considered, in the calibration configuration (switching signal cal equal to 1), the multiplexer 7 makes the delay associated to the second term kit null for each delay device D_I-D_N.

The first calibration filter Fl is configured to generate, starting from the signal provided by the first arbiter device FFl a corresponding feedback signal, which, in the calibrating step, is used for adjusting the time delay introduced by the first delay device Di. In particular, the feedback signal provided by the arbiter device in the calibrating step FFl is such to reduce or minimize the difference between the time delays (or, equivalently, the relative offset) between the signals applied to the inputs 9 and 10 of the arbiter device FFl.

According to the exemplary embodiment described, the delay adjustment carried out by calibration by the first filter Fl acts only on the first term XQ, making such a term equal or proximate to the delay value introduced by the reference delay device D_bm-

As an example, the calibration filter Fl can be (as indicated in Figure 2) a digital integrator- filter or a non-linear digital logic network, which implements a binary search algorithm. In case the adjustable delay devices D_I-D_N allow a continuous adjustment of the delay value, an analogue filter can be employed as the calibration filter Fl. In this case, the delay coefficients Ic₁ are real values (i.e. not necessarily integers) given by the sum of an integer value provided by the respective multiplexer 7 and a real value provided by the corresponding calibration filter Fl-FN. The same applies to the other calibration filters F2-FN.

The encoder 4 is such to receive at its first inputs the decision signals (in the form of rectangular wave signals) provided by the arbiter devices FFl-FFN and, in the operating configuration, encode them, providing a typically binary digital code, representative of the time, i.e. the time duration of the signal start, for example at a high level. According to a particular example, the encoder 4 carries out a "thermometric scale"-type encoding and then expresses, at least ideally, in a binary representation, the sum of the values 0 and 1, represented by the output decision signals at the arbiter devices FFl-FFN.

An alternative example in respect to the previous one, the encoder 4 can be "priority encoder", which is such to represent, in a binary encoding, the position of the first transition from 0 to 1 in the input sequence. A different type of encoder 4 can also be employed, for example more elaborate than the previ- ous ones and which carries out an error correction of the sequence according to a determined criterion.

As it is evident from the previous description, the time-digital converter 100 is of the type that can be integrated in a semi-conductor chip and it can be implemented, for example, in the CMOS or BJT (Bipolar Junction Transistor) technologies.

Operation

In referring to the operation of the time-digital converter 100 in Figure 2, first the step, wherein the calibration configuration is assumed, needs to be considered; in such a situation the switching signal cal assumes, for example, the value 1. In the calibration configuration, the input multiplexer 3 is switched so that at its first output 8 the signal stop is transferred, which is also applied to the input of the reference delay device D_bm- Moreover, the multiplexers 7 of each conversion line Ll-LN are brought in a configuration, wherein the second delay term kiτ is made null for each adjustable delay device Dχ-D_N. Moreover, the switches 6 are closed, in order to connect the outputs 01-ON of the arbiter devices FFl-FFN with the respective inputs of the calibration filters Fl-FN.

The signal stop is delayed by the reference delay device Dbm by a value To and the so delayed signal So is applied to the second input 10 of each arbiter device FFl-FFN.

Moreover, the signal stop is delayed by each adjustable delay device D_I-D_N and therefore a plurality of delayed signals Sl-SN is provided to each first input 9 of each arbiter device FFl-FFN.

It is to be observed that because of structural mismatching or mismatching which arise during the product life, it occurs that the values of the first delay terms introduced by the delay devices D_I-D_N are not, as they should be, in ideal conditions, equal to each other and equal to the value to. In particular, the delay values actually introduced could depart from the ideal one, so relevantly to compromise the exactness of the decision made by the corresponding arbiter devices and therefore to compromise the linearity of the time-digital conversion. The calibration procedure disclosed herein is, advantageously, aimed to reduce or substantially eliminate these problems.

Each arbiter device FFl-FFN provides, on the respective output 01-ON, a decision signal, which, in the ideal case, should indicate the simultaneousness of the signal switching at the respective inputs and therefore should range between the values of 0 and 1.

When the output, for example, of the first arbiter device FFl is of the same level as the high level 1, the first integrator-type calibration filter Fl provides, on the first output thereof, a feedback signal S_rl, which adjusts the delay device Di, increasing the delay value associated to the first term, until switching the output Ol of the first arbiter device FFl .

When the output of the first arbiter device FFl is of the same level as the low level 0, the first calibration filter Fl provides, at the first output thereof, a feedback signal S_ri, which reduces the delay value associated to the first term, until switching the output 01 of the first arbiter device FFl.

According to the trend of the feedback signal S_ri some capacitors included in the first delay device Di will activate or deactivate. For example, when due to the action by the closed loop control, a null average value of the delay between the input signals at the first arbiter device FFl is reached, it will occur, advantageously, that a single capacitor is turned on and off by the feedback signal S_ri . In this case, it can be recognized to have carried out a calibration and the configuration reached of the activated and deactivated capacitors, which implies a first term of delay substantially equal to τ₀, is kept fixed for the subsequent operating step. In case the filter Fl is a simple integrator, the feedback signal S_rχ is of the ramp-type and the number of comparisons the arbiter device FFl carries out to find the number of capacitors, that implements the condition previously described is, at most, equal to the number of total capacitors .

The other calibration filters F2-FN work analogously, which produce relative feedback signals S_r2-

It is to be observed that the calibration filter Fl, feedback disposed, is inserted as to form a control loop, which includes also the arbiter device FFl and therefore the adjustment implemented leads to the reduction of the mismatching due to physical parameters of the arbiter device FFl itself and not only to the adjustable delay device Di.

As regards the alternative solution, which provides the use of a filter implementing a binary or dichotomous search algorithm (algorithm known per se) , initially all the capacitors activate, which concur to the first delay term for the first device Di. Then, the first filter Fl searches for the value of the number of capacitors to be activated according to the output signal from the first arbiter device FFl, redefining iteratively a maximum value and a minimum value of such a number of capacitors, by subsequent halving of that number. In more detail, the binary search provides, at the first step, the selection of the middle value of the range of possible values of the number of capacitors and, according to the output of the first arbiter device FFl, halving the selected search range implemented or the range above the previously selected value or below. At the following step, the middle value of the new range is selected, which amplitude is halved in respect to the previous step. And so on. The number of comparisons that the first arbiter device FFl carries out is, in this case, at most the same as the base-2 logarithm of the total number of capacitors.

In the step concerning the operating configuration, the switching signal cal assumes the value 0 and at the output 8 of the input multiplexer 3 the signal start is transferred, i.e. the signal representative of a time, which is desired to be converted into digital. The signal stop is fed to the input of the reference delay device D_bm. The switches 6 connected to each calibration filter Fl-FN are open, so that the corresponding conversion line Ll-LN is an open loop. The multiplexers 7 of each conversion lines Ll-LN are carried by the switching signal cal in a configuration wherein the relative adjustable delay device D_I-D_N, is fed with a constant regulation signal, in order for the delay of the general device to be, as already described, equal to T₁= τo+χx; wherein τ₀ was obtained by the calibration step.

The signal to be converted start is distinctively delayed from each delay device D_I-D_N and the corresponding delayed signals S_X-S_N (offset replicas of the signal start) are fed to the respective inputs 9 of the arbiter devices FFl-FFN, which return, at the relative outputs 01-ON, the decision signals S_Dχ-S_DN. The signal stop is delayed by the reference delay device D_bm by an amount τ₀ in order obtain the reference signal So which is fed to the second input 10 of each arbiter device FFl-FFN.

Each decision signal S_Di~S_DN will be, for example, of a high level or a low level if, upon switching the reference signal So from 0 to 1, the corresponding delayed signal S_I-S_N is of a high or low level, respectively. The decision signals S_DI-S_DN are then fed to the encoder 4, which converts them into a digital code .

Simulations

In referring to the performance of the time- digital converter 100, refer to Figures 3A, 3B and 3C, wherein parameters of Differential Non Linearity (DNL) and Integral Non Linearity (INL) are represented by a diagram, under three different simulated conditions and expressed in τ units, i.e. Least Significant Bit (LSB) of the time-digital converter. As it is clear to those skilled in the art, the parameters DNL and INL are both significant for the performance of the conversion carried out by the amplitude "time" in the respective output binary code OU.

Diagrams in Figure 3A refer to a time-digital converter analogous to that in Figure 2, wherein the calibration procedure was not carried out. The diagrams in Figure 3B refer to a situation wherein the time-digital conversion has been carried out in a calibrated converter, such as 100 in Figure 2 and in presence of a digital calibration filter. Diagrams in Figure 3C refer to a situation wherein the time- digital conversion is carried out in a calibrated converter, such as 100 in Figure 2 and in presence of delay devices which allow a continuous change in the delay itself and analogue calibration filters.

By comparing the diagrams DNL and INL in Figure 3B with those in Figure 3A, it is noted that, for Figure 3B, the values INL and DNL are within the range (-It₁, +lτ) while for the diagrams in Figure 3A, these parameters are also higher in the absolute value than 2τ. The best performance in terms of linearity of the time-digital converter in Figure 3B is particularly evident in respect to the parameter INL.

In respect to the diagrams in Figure 3C, it is to be observed that the non linearity in terms of both DNL and INL is extremely reduced in respect to that present in the relative converter in Figure 3A, resulting nearly unimportant and due to inaccuracy of the delay τ.

The time-digital converter 100 to which the above described calibration procedure is applied, results in a non complex implementation and has satisfactory performance, as shown by the values of the parameters DNL and INL obtained by the simulations carried out. The calibration of the first delay term τ₀ provides a beneficial effect on the quality of the conversion, since the first term of delay represents the most important component introduced by each adjustable delay device D_I-D_N. The possibility to feedback during the calibration also the same arbiter devices FFl-FFN employed in the operating step allows to compensate, in the calibration step, also for inaccuracies of the physical parameters associated to such arbiter devices. Moreover, considering that the input multiplexer 3 is common to all the adjustable delay de- vices Dχ-D_N, a possible difference in the delays introduced by the multiplexer 3 itself in the calibration configuration (second input 2 connected to the output 8) and in the operating configuration (first input 1 connected to the output 8) seems not to alter the accuracy of the correction done in the calibration step, since it is uniform for each conversion line Ll-LN.

Alternative embodiment

According to another embodiment of the invention, the time-digital converter 100 can be implemented in "series". In the Figure 4, which refers just to the series mode, equal or analogous devices and components to those already defined are represented with the same number references.

According to this embodiment, the adjustable delay devices Di-D_N have ideally the same delays. In practice, before calibration, such delays can be distinct to each other because of structural inaccuracies and the general delay of an i^th device can be represented with the expression kiτ.

The output of each delay device D₁-D_N, is connected to the first input 9 of the relative arbiter device FFl-FFN and it can be connected, except the N^th delay device D_N, also to the input of the subsequent delay device by the relative multiplexer 7, implementing the series-mode connection.

In the calibration step, each multiplexer 7 transfers to its own output the signal stop, which is then applied to the inputs of the adjustable delay device D_I-D_N and to the input of the reference delay device Db_1n- Each calibration filter Fl-FN, analogous to that described with reference to Figure 2, will act as a feedback loop, in order to adjust the coef- ficient k_x of each adjustable delay device for obtaining whole delays k_±τ equal to each other and the same as the delay introduced by the reference delay device Dbm- It is to be observed that, advantageously, the calibration step also takes into account, by compensation thereof, the delay introduced by each multiplexer 7, present at the input in each adjustable delay device.

In the operating step, the multiplexer 7, connected to the first adjustable delay device D_x, will transfer on its own output the signal to be converted start. The other multiplexers 7 transfer on their own outputs the output signal from the previous delay device. At the input of the reference delay device D_bm, the signal stop is provided. Each arbiter device FFl- FFN provides a decision signal S_Di-S_DN, indicative of which signal at its input has switched first, which is provided to the encoder 4, which generates the corresponding binary code.

It is evident that the inventive concepts expressed herein are not limited to the exemplary embodiments illustrated herein, because the present invention is susceptible of various modifications and variants, all of which fall within the inventive principle, expressed in the annexed claims, and the technical details can vary according to the particular needs and the continuously evolving state of the art.

Claims

1. A time-digital converter (100) comprising: an adjustable delay device (Dl; DN) for generating a delayed signal (Si) provided with a delay adjusting input (5); an arbiter device (FFl) for receiving the delayed signal and a reference signal (So) on corresponding inputs and for supplying an output signal (S_Di) to an output (01) indicative of a relative timing of the signals at its inputs; characterized in that it further comprises: a calibration delay device (D_bm) for supplying the reference signal to the arbiter device; a calibration filter (Fl) connectable to said output (01) for providing input (5) of the adjustable delay device with a delay adjusting signal (S₂i) depending on the output signal of the arbiter device.

2. Converter (100) according to claim 1, wherein said calibration filter (Fl) is designed to generate the adjusting signal so as to reduce a difference between a first delay introduced by the adjustable delay device and a second delay introduced by the calibration delay device.

3. Converter (100) according to at least one of the preceding claims, wherein the converter is such to alternatively take: an operative arrangement wherein the adjustable delay device (Dl) is supplied with a to-be-delayed signal (start) and the calibration filter is disconnected from said output; a calibration arrangement wherein the reference signal is supplied to said adjustable delay device and the calibration filter (Fl) is connected to said arbiter device output.

4. Converter (100) according to at least one of the preceding claims, wherein said calibration filter is a feedback of a closed loop further comprising the adjustable delay device and the arbiter device.

5. Converter (100) according to at least one of the preceding claims, wherein said filter is one of the filters belonging to the group consisting of: an integrator, a non linear digital logic network, a binary search logic network, an analog filter.

6. Converter (100) according to at least one of the preceding claims, wherein said arbiter device is a sampler of the signal delayed according to said reference signal.

7. Converter (100) according to claim 6, wherein the arbiter device belongs to the group consisting of: a sampler, a flip-flop, a D-type flip flop.

8. The converter according to at least one of the preceding claims, further comprising: at least one further adjustable delay device (D₂) for generating at least one further delayed signal

(S₂) and provided with a further respective delay adjusting input; at least one further arbiter device (FF2) for receiving said at least one further delayed signal (S₂) and said reference signal (S₀) on respective inputs and for supplying at least one further output signal

(S₀₂) to a respective output indicative of a relative signal timing at its inputs; at least one further calibration filter (F2) con- nectable to said respective output to provide the input of the further adjustable delay device with a further delay adjusting signal (S₂₂) depending on said at least one further output signal.

9. Converter (100) according to claim 8, imple- mented according to a parallel mode wherein the adjustable delay device (Di) and the at least one further adjustable delay device (D₂) have a common input for a common signal to be delayed (8) .

10. Converter (100) according to claims 2 and 9, wherein the adjustable delay device and the at least one further adjustable delay device have distinct delays when in an operative arrangement; each of said delays comprising a respective first component substantially equal to said first delay and respective second components each one different from the other.

11. Converter (100) according to claim 8, implemented according to a series mode wherein the adjustable delay device (Di) is provided with an output terminal connectable to a relative input of the at least one further adjustable delay device (Do) ; when in operative mode, the adjustable delay device and the further adjustable delay device having delays substantially equal to a respective delay associated to said calibration delay device.

12. Converter (100) according to at least one of the claims from 8 to 11, wherein said output of the arbiter device and said respective output of the at least one further arbiter device are connected to an encoder (4) for conversion into a time representative binary code.

13. Converter (100) according to claim 12, wherein said encoder is arranged so as to operate according to one of the following modes: a mode wherein it sums up the levels of the output signal and of said further output signal; another mode wherein it operates as a priority encoder.

14. Electronic system (400) comprising: a time-digital converter (100) provided with an output for a digital signal;

- a digital filter (200) connected to said output for processing the digital signal; characterized in that said time-digital converter is implemented according to at least one of the preceding claims .