WO2010092399A2

WO2010092399A2 - Integrated mems transducer and circuitry

Info

Publication number: WO2010092399A2
Application number: PCT/GB2010/050233
Authority: WO
Inventors: Anthony Traynor; Neil Sinclair Rankin; Colin Roberts Jenkins; Tsjerk Hoekstra; Richard Laming
Original assignee: Wolfson Microelectronics Plc
Priority date: 2009-02-13
Filing date: 2010-02-12
Publication date: 2010-08-19
Also published as: GB2467776A; GB2467776A8; GB0902479D0; WO2010092399A3

Abstract

The invention relates to the integration of MEMS transducers with electronic circuitry on the same substrate. A method of fabricating and integrated MEMS transducer and circuitry is disclosed which is fully compatible with standard CMOS processing and requires no post processing. The transducer is formed by forming at least one membrane layer, a plurality of back-plate layer sand at least one sacrificial structure such that removal of the sacrificial structure leaves the membrane free to move relative to the fixed back-plate. The method also forms circuit layers on the substrate to form the circuit components and involves sharing layers of material such that at least some of the layers which form the back-plate of the transducer also forms one of the circuit layer sand such layer include at least one metal layer and at least one dielectric layer. The method thus reduces the number of processing steps required compared with sequential fabrication of the circuitry and the transducer. Integrated transducer and electronics devices are also taught.

Description

INTEGRATED MEMS TRANSDUCER AND CIRCUITRY

This invention relates to a device having a capacitive MEMS transducer and associated circuitry integrated on a single chip and to methods of making such a device.

Consumer electronics devices are continually getting smaller and, with advances in technology, are gaining ever increasing performance and functionality. This is clearly evident in the technology used in consumer electronic products such as mobile phones, laptop computers, MP3 players and personal digital assistants (PDAs). Requirements of the mobile phone industry for example, are driving the components to become smaller with higher functionality and reduced cost. It is therefore desirable to integrate functions of electronic circuits together and combine them with transducer devices such as microphones and speakers.

The result of this is the emergence of micro-electrical-mechanical-systems (MEMS) based transducer devices. These may be for example, capacitive transducers for detecting and/or generating pressure/sound waves or transducers for detecting acceleration. There is a continual drive to reduce the size and cost of these devices through integration with the electronic circuitry necessary to operate and process the information from the MEMS through the removal of the transducer-electronic interfaces. One of the challenges in reaching these goals is the difficultly of achieving compatibility with standard processes used to fabricate complementary-metal-oxide-semiconductor (CMOS) electronic devices during manufacture of MEMS devices. This is required to allow integration of MEMS devices directly with conventional electronics using the same materials and processing machinery. This invention seeks to address this area.

Microphone devices formed using MEMS fabrication processes typically comprise one or more membranes with electrodes for read-out deposited on the membranes and/or a substrate. In the case of MEMS pressure sensors and microphones, read out is usually accomplished by measuring the capacitance between the electrodes.

Figure 1 shows a capacitive transducer as described in International Patent Application publication WO2007/107736. The transducer 101 is formed on a substrate 102 having an insulation layer 103. The transducer comprises a membrane layer 106 having an electrode 104 disposed thereon. A structurally rigid back-plate 114 has a second electrode 108 embedded therein. During the manufacture of the MEMS device described above, the membrane 106 is formed using a first sacrificial layer located between the membrane 106 and a layer of material disposed on the substrate 102. Metal for the membrane electrode is then deposited on the membrane material prior to deposition of a second sacrificial layer. The back plate material is deposited in two steps, with the back-plate electrode being deposited between the two steps so that it is embedded within the resultant back-plate. A back-volume 112 is formed using an etching process from below the substrate, known as a "back-etch". The sacrificial layers between the membrane 1 16 and second electrode 108 are removed later in the process to leave the membrane 106 suspended and free to move.

It will be appreciated that, in order to incorporate the transducers into useful devices, it is necessary to interface or couple them to electronic circuitry.

As shown in Figure 1 the membrane electrode 104 and back-plate electrode 108 are typically connected via tracks (not shown) to contact pads 1 16 and 118 respectively for connection to electronic circuitry. The tracks are formed during deposition and patterning of the relevant electrode and provide a connection from the electrode to a contact area a short distance away from the structure of the transducer. The conducting tracks are buried in subsequent deposition stages. Part of the fabrication process involves etching holes down to the end of the tracks and filling with conductive material to provide conductive vias. The top of the conductive vias are covered with the contact pads for connection to the electronic circuitry.

The circuitry may conveniently be CMOS circuitry and thus comprise various CMOS layers. As the skilled person will appreciate CMOS circuitry is formed by depositing appropriate metal and inter-metal dielectric (IMD) or inter layer dielectric (ILD) materials over appropriately doped regions of the substrate. Figure 2 shows an example cross section of some CMOS circuitry layers according to a typical CMOS process.

To date most MEMS capacitive transducers have been fabricated on a separate substrate to the electronics. Thus the contact pads 116 and 1 18 described above with reference to figure 1 are arranged as, or are electrically connected to, bond pads suitable for wire bonding to corresponding bond pads on a separate substrate carrying the electronic circuitry. The presence of such wire bonds can cause problems however.

For acoustic transducer applications it will be appreciated that the package containing the transducer must allow transmission of acoustic waves. Thus the package generally has an opening to the environment which means that humidity within the package can not be prevented. Humidity within the package can lead to a leakage current flowing between the wire bonds. The leakage current increases the noise in the system and thus degrades the signal to noise ratio.

Further the bond pads, both the bond pads on the transducer die and those on the circuitry die, are relatively large conductive regions and will tend to generate to unwanted capacitance in the system. Given that the capacitance of the MEMS transducer is small, even small additional capacitance can have a significant impact on the signal to noise ratio.

In addition the wire bonds may be susceptible to electromagnetic interference (EMI). One node of the electronic circuitry in a microphone application will be a biasing voltage supply to the microphone having very high impedance. This node is susceptible to small signal swings. Despite the fact that the transducer package is typically shielded to protect from EMI, as mentioned above the package is also partly open to the environment and thus some radiation within the package is likely, especially if the microphone is used in a device having RF communication capability. The wire bond can act like an antenna and thus introduce further noise into the system.

Thus the elimination of wire bonds and bond pads would be beneficial to transducer performance. Integration of the electronic circuitry and the transducer onto a single chip could eliminate the need for wire bonding and allow potential size reductions. However the integration of circuitry and a MEMS transducer onto a single chip presents various technical challenges.

US patent No. 7,215,527 describes an acoustic MEMS transducer formed on a silicon substrate which may also comprise audio circuitry fabricated on the circuitry. The acoustic diaphragm is manufactured according to the process described in US Patent No. 5,717,631. This process involves depositing a variety of metal and oxide layers using CMOS processing steps followed by some post processing to form the MEMS microstructures. Exactly how the electronic circuitry and transducer are actually integrated is not clear and this method does require the use of post CMOS processing.

GB2,435,544 teaches a method of fabricating a MEMS device, such as an acoustic transducer, which involves forming CMOS circuit regions on a substrate and subsequently forming a MEMS device on a different region of the substrate using CMOS compatible processes. The transducer is connected to the circuit region by interconnecting tracks on the surface. This method described in GB2,435,544 represents a useful process for forming a MEMS transducer which is integrated on a single substrate with circuit regions.

It is an aim of the present invention to provide improved methods for fabricating MEMS transducers integrated with electronic circuitry and to provide novel integrated MEMS and electronic circuitry structures.

Thus according to the present invention there is provided a method of fabricating a MEMS transducer and at least one circuit component on a substrate comprising the steps of: forming, on a first area of a substrate, a plurality of back-plate layers, at least one sacrificial structure and at least one membrane layer such that removal of the at least one sacrificial structure results in a moveable membrane and rigid back-plate; and forming on a second area of said substrate at least one circuit component from a plurality of circuit layers, wherein said method comprises depositing a plurality of common layers of material which form at least some of back-plate layers in the first area and also form at least some of the plurality of circuit layers in the second area wherein said plurality of common layers comprise at least one metal layer and at least one dielectric layer.

The method of the present invention thus fabricates the back-plate of the transducer, at least partly using some of the same layers that are used to form the circuitry. This means that the fabrication of the transducer and circuitry occurs at least partly in parallel. The layers of the back-plate that are common with the circuitry comprise at least one metal layer and at least one dielectric layer, although the back-plate may comprise a plurality of metal layers and/or dielectric layers.

At last one of the common metal layers may form the electrode for the back-plate. Thus the present invention uses a metal electrode for the back-plate and deposits the metal at the same time as the circuitry.

Additionally or alternatively at least one metal layer may be provided in the back-plate to control the mechanical properties of the back-plate, i.e. to control the strain/stress of the back-plate.

In another aspect of the invention there is provided a method of fabricating a MEMS transducer and at least one circuit component on a substrate comprising the steps of: forming, on a first area of a substrate, at least one back-plate layer, at least one sacrificial structure and at least one membrane layer such that removal of the at least one sacrificial structure results in a moveable membrane and rigid back-plate and forming on a second area of said substrate at least one circuit component from a plurality of circuit layers, wherein said method comprises depositing at least one layer of material which forms one of the membrane or back-plate layers in the first area and also forms one of the plurality of circuit layers in the second area.

The method of the present invention thus involves forming a MEMS transducer with integral circuitry on a single substrate in which at least one functional layer of the transducer, i.e. a membrane layer or a back-plate layer, is formed from the same material and deposited at the same time as one of circuit layers. The method of the present invention thus merges process steps for fabrication of the transducer with process steps for fabrication of the circuitry. The method of the present invention thus reduces costs compared to other fabrication methods. As used herein the term depositing refers to any suitable method for forming a layer of material onto the substrate or layers already present on the substrate and is not limited to any particular layer deposition or growth technique.

Conveniently the method comprises standard CMOS (Complementary-metal-oxide- semiconductor) processing steps. CMOS processing is a known fabrication technique for forming circuit components and includes steps such as ion implantation, photomasking, metal deposition, dielectric deposition and etching. The present invention therefore provides a method that can be implemented using standard CMOS processing steps in a single standard CMOS foundry to produce an integrated transducer and electronics. All of the functional layers for the transducer and electronics can be performed as part of a CMOS process.

The circuit layers may therefore comprise at least one metal layer and at least one dielectric layer.

The transducer is a capacitive transducer and thus comprises a membrane electrode and a back-plate electrode. If a suitably conductive material is used for the membrane layer or back-plate layer then a single layer may provide the structure of the membrane/back-plate and also function as the electrode. Conveniently however there are a plurality of membrane layers, comprising at least one structural membrane layer and at least one membrane electrode layer, and a plurality of back-plate layers comprising at least one structural back-plate layer and at least one back-plate electrode layer.

The transducer is fabricated in a first area on the substrate and the at least one circuit component in a second area of the substrate. The transducer and the circuitry are thus formed at different parts of the substrate. Preferably the method involves forming the circuit layers, i.e. the at least one metal layer and the at least one dielectric layer, into a plurality of circuit components in the second area. Thus some or all of the plurality of circuit components and the transducer may share common material deposited in the first area and the second area in the same process step. The circuit components may be arranged to provide suitable circuitry for the MEMS transducer. Suitable circuitry may include, without limitation, amplifier circuitry, voltage biasing circuitry, filter circuitry, analogue to digital converters and/or digital to analogue converters, oscillator circuitry, voltage reference circuitry, current reference circuitry and charge pump circuitry.

The second area may be located in a distinct region of the substrate to the first region. For instance the transducer may be formed such that it is located on one side of the substrate and the circuitry may be located on the other side of the substrate. As used herein the term substrate is taken to refer to the final substrate of an individual device. The skilled person will appreciate that multiple devices are typically processed on a single wafer and ultimately diced into individual substrates. To reduce the size of the finished device however it is preferable to arrange the circuit components around the transducer. Thus the second area may substantially surround the first area.

The second area, i.e. the area where the at least one circuit component is formed, may be a continuous area. However in some embodiments there may be circuit components in more than one distinct area of the substrate. Thus the second area may comprise a plurality of distinct regions of the substrate.

In one embodiment, the method comprises the step of forming the dielectric and metal layers of the circuit layers prior to forming any of the transducer layers. The transducer layers are thus formed on top of the dielectric layers deposited in the first area during formation of the circuit layers. It will be clear therefore that the transducer in this embodiment is not fabricated directly on the surface of the substrate but on top of other layers deposited on the substrate. As used herein the step of forming a layer on the substrate includes forming such a layer on top of any intervening layers formed on the substrate.

In this embodiment of the invention the layer which forms a membrane layer or a back- plate layer of the transducer also forms a passivation layer for the circuit components.

It should be noted that this embodiment of the present invention does not simply involve covering the transducer and the circuit components in a layer of protective material. The invention involves depositing a structurally functional layer of the transducer which also forms a passivation layer for the circuit components thus removing the need for a separate passivation layer step.

This embodiment of the invention preferably comprises the step of making an electrical connection between the membrane electrode and a circuit component and the step of making an electrical connection between the back-plate electrode and a circuit component prior to deposition of the membrane layer or back-plate layer which forms a passivation layer for the circuit components. In this way the electrical connections between the transducer and the circuitry are formed and buried in a subsequent deposition step. Thus the electrical connections between the transducer and the circuitry are not exposed and thus the problems of leakage current are much reduced.

The method according to this aspect of the invention thus may comprise the steps of: depositing a plurality of dielectric layers on the substrate and depositing a plurality of metal layers on the substrate to form a plurality of circuit components in the second area; forming a first sacrificial structure on the uppermost dielectric layer in the first area; forming a membrane having a membrane electrode over the sacrificial structure and the uppermost dielectric layer; forming a second sacrificial structure on the membrane; forming a first back-plate layer and back-plate electrode over the second sacrificial structure; making electrical connections between the membrane electrode and a first circuit component and making electrical connections between the back-plate electrode and a second circuit component; and depositing a further back-plate layer over the substrate, the further back-plate layer forming part of the back-plate of the transducer and forming a passivation layer for the circuit components.

The sacrificial material may then be removed to leave a moveable membrane with membrane electrode suspended under a rigid back-plate having a back-plate electrode.

The method may involve depositing a second back-plate layer over the substrate, after the step of formation of the first back-plate layer and back-plate electrode but prior to the step of forming the electrical connections. The second back-plate layer may also comprise part of the passivation layer for the circuit components. The first back-plate layer may also comprise part of the passivation layer for the circuit components.

The method may involve providing release holes in the back-plate and may also involve providing relief holes in the membrane. The method may also comprise the step of forming a through-hole through the substrate and dielectric layers underneath the membrane to provide a back-volume in use. In another embodiment of the invention the layer of material which forms a membrane layer or back-plate layer in the first area forms a metal layer or a dielectric layer in the second area. Thus at least one layer shared between the transducer and the circuit layers is a functional dielectric or metal layer of the circuit component. Sharing functional layers between the transducer and the circuit components reduces the number of process steps required in fabrication. Where photolithography steps are required it will be appreciated that photomasks are needed. If the same layers are used for making the transducer and the circuitry then these layers can be processed at the same time using the same masks.

One of the metal layers of the circuit layers may comprise a membrane electrode layer or a back-plate electrode layer. Forming the membrane or back-plate electrode of the transducer from the same metal layer as one of the circuit component metal layers also allows for ease of interconnection between the relevant electrode and a circuit component.

It should be noted that in embodiments of the present invention the membrane electrode for the transducer is a metal layer. The metal layer must be relatively thin in order that the membrane can move in use. Some known MEMS transducers use a conductive material to provide the membrane layer and thus have a single membrane layer that provides both the moveable element and electrode. Embodiments of the present invention use a thin metal layer as the electrode together with a structural layer to provide the moveable element and support the electrode and use of a metal membrane electrode represents another aspect of the invention.

Additionally or alternatively to one of the metal circuit layers also comprising the membrane or back-plate electrode, at least one dielectric layer of the circuit components may comprise a structural back-plate layer.

In addition a back-plate layer of the transducer may comprise a passivation layer for the circuit components.

Clearly, in order for an electrode layer and/or a back-plate layer of the transducer to be deposited at the same time as one of the metal or dielectric layers of the circuit layers the devices must be fabricated at least partly in parallel. It will be appreciated however that the membrane must be able to move in the finished device, i.e. it is suspended over a cavity.

In one embodiment therefore the method comprises forming at least one dielectric layer on the substrate, forming a cavity in the at least one dielectric layer in the first area, filling the cavity with sacrificial material, forming a membrane layer having a membrane electrode over the cavity and forming a sacrificial structure over the cavity.

To ensure that there is room for a membrane layer to move this embodiment of the present invention therefore involves defining a cavity in the at least one dielectric material in the fist area. This cavity is filled with sacrificial material to support the subsequent formation of a membrane layer. It will be apparent that the membrane layer should ideally be flat so preferably the step of filling the cavity with sacrificial material involves planarising the surface prior to formation of the membrane layer. The step of planarising the surface must be able to planarise the dielectric outside the cavity and the sacrificial material within the cavity. Preferably the step of planarising the surface comprises a chemical mechanical polishing (CMP) step.

The membrane layer is then deposited as a flat, i.e. planar, layer. Using a flat membrane layer is advantageous as there is no stress in the layer associated with any corners, i.e. regions of high curvature. The membrane layer may however extend for a significant distance beyond the cavity and thus will be strongly supported in use. Such a planar membrane configuration is thus advantageous and the use of a planar membrane configuration and method of producing such a planar membrane are aspects of the present invention. It will be appreciated that a planar membrane configuration could be advantageous in several transducers and it is not limited to use in transducers having integrated electronic and applies equally well to stand alone transducers on a substrate, i.e. having electronics on a different substrate.

To provide room for the membrane to move upwards a sacrificial structure is formed on top of the membrane to define a cavity between the membrane and the eventual back- plate. Once this sacrificial structure has been fabricated the processing of the circuitry regions can be continued. This will involve depositing at least one dielectric layer. Such at least one dielectric layer is deposited over the whole substrate and thus is deposited over the sacrificial structure and thus forms a first back-plate layer of the transducer.

In a convenient embodiment the step of forming the circuit layers comprises the step of forming at least one metal layer after a dielectric layer. In this case the dielectric layer comprises a back-plate layer of the transducer as described above and the metal layer forms the back-plate electrode. The metal layer may also may formed to provide an interconnect between the back-plate electrode and a circuit component. An electrical connection between the membrane electrode and a circuit component may also be formed by this metal layer. The method may subsequently involve deposition of a further dielectric layer which forms part of the circuit layers and also forms a further back-plate layer of the transducer. This further dielectric layer encapsulates the back- plate electrode and can bury the electrical connections between the transducer and the circuitry.

The method may involve deposition of at least one additional back-plate layer. The at least one additional back-plate layer may be deposited to provide the back-plate with the required mechanical properties such as rigidity, stress etc and can also form part of a passivation layer for the circuit components.

In an alternative embodiment movement of the membrane is achieved by forming the membrane at the uppermost layer in the transducer, i.e. the layer which is furthest from the substrate.

In this embodiment of the invention the back-plate of the transducer is formed first and comprises at least some of the dielectric layers which form part of the circuit components.

In one embodiment the method involves depositing a plurality of dielectric layers on the substrate and depositing a plurality of metal layers on the substrate to form a plurality of circuit components in the second area and to form a back-plate in the first area. The method may then involve forming a back-plate electrode on the uppermost dielectric layer in the first area. A first sacrificial structure may then be formed on the back-plate electrode prior to formation of a membrane layer and membrane electrode on the surface. Subsequent removal of the first sacrificial structure will leave a moveable membrane having a membrane electrode suspended above the back-plate and back- plate electrode. The membrane layer may also comprise a passivation layer for the circuit components.

Whilst a single membrane layer may be sufficient it may be beneficial to provide at least one strengthening layer to provide support for the membrane layer. The method may therefore comprise the step of forming a second sacrificial structure on the membrane and subsequently forming a strengthening layer on the surface. The strengthening layer may be subsequently removed from above the membrane but retained in the area of the membrane side walls for support. The strengthening layer may also comprise part of a passivation layer for the circuitry components. The strengthening layer may comprise the same material as the membrane layer.

The sacrificial layer may be formed as a protrusion above the surface of the dielectric layers. In another embodiment however the first sacrificial material may be arranged to fill a cavity formed in a spacing layer. The method may therefore involve forming a spacing layer on the substrate in the first area. The spacing layer may form at least part of a passivation layer for the circuit components. A cavity may be formed in the spacing layer and filled with sacrificial material in a similar manner as described above. The surface may be planarised and a planar membrane layer may then be deposited. The planar membrane layer has the advantages described above of not having stress concentration points. The spacing layer may comprise the same material as the membrane layer.

The method may involve the step of forming electrical connections between the membrane electrode and a circuit component and the step of forming electrical connections between the back-plate electrode and a circuit component prior to formation of the strengthening layer.

The method may involve the formation of release holes through the back-plate. The method may also comprise the step of forming relief holes through the membrane. The method may further involve formation of a through-hole through the substrate to provide an acoustic port.

In a further embodiment of the invention where the back-plate of the transducer is formed first, the sidewall supports for the membrane layer may be provided by dielectric layers which form part of the circuit layers. Additionally the back-plate electrode may be formed from a metal layer which also forms a metal layer of the circuit components.

Thus the method may involve the step of forming at least one dielectric layer on the substrate to form a dielectric circuit component layer in the second area and also to form a back-plate layer in the first area. A back-plate electrode is formed on the back- plate. The back-plate layer may conveniently be formed from a metal layer which also forms a metal layer of at least one circuit component. The method may then involve the steps of depositing at least one further dielectric layer to form a dielectric layer of a circuit component, forming a cavity in the at least one further dielectric layer in the first area, filling the cavity with sacrificial material, forming a membrane layer having a membrane electrode over the cavity and forming a sacrificial structure over the membrane layer over the cavity.

This embodiment of the present invention therefore defines a cavity in the at least one dielectric material in the first area which is filled with sacrificial material to support the subsequent formation of a membrane layer. As described above the membrane layer should ideally be flat so preferably the step of filling the cavity with sacrificial material preferably involves planarising the surface prior to formation of the membrane layer. Again the step of planarising the surface must be able to planarise the dielectric outside the cavity and the sacrificial material within the cavity. Preferably the step of planarising the surface comprises a chemical mechanical polishing (CMP) step.

The membrane layer is then deposited as a planar layer. As described above using a planar membrane layer is advantageous as there is no stress in the layer associated with any corners or areas of high curvature. The membrane layer may however extend for a significant distance beyond the cavity and thus will be strongly supported in use. The method may then comprise depositing at least one additional dielectric layer. The at least one additional dielectric layer comprises a dielectric layer of the circuit components and will provide support to the membrane layer in use. The method may also comprise depositing at least one additional metal layer which comprises a metal layer of at least one circuit component. An additional metal layer may also form an electrical connection between the membrane electrode and a circuit component.

The method may involve the step of depositing a strengthening layer on top of the substrate to provide further support to the membrane layer and to form at least part of a passivation layer for the circuit components.

The method may also comprise formation of a through hole through the substrate in the first area to provide an acoustic port.

The method according to this aspect of the invention thus shares several layers in common between the transducer and the circuit components and reduces the number of processing steps required.

It will be noted that several of the embodiments described above use dielectric layers both for the circuit components and the back-plate of the transducer. The skilled person will appreciate that the properties of such dielectric layers may not be compatible with the desired properties, for instance stress, of the back-plate. CMOS dielectric layers typically have compressive stress whereas tensile stress is preferred for the back-plate. Thus it may be necessary to control the properties of the back- plate. As mentioned above the use of additional overlying layers, which may comprise different material, may help control the stress of the back-plate.

In another arrangement however the back-plate comprises layers of dielectric material which form the dielectric layers of at least one circuit component and at least one metal layer which comprises a metal layer of at least one circuit component wherein the arrangement of the metal layer is such so as to control the mechanical properties of the back-plate layers. The use of at least one of the metal layers which are deposited anyway (for forming the circuit components) in an arrangement to provide desired mechanical properties of the resulting dielectric-metal stack allows a back-plate to be provided having the correct material properties but without requiring any additional process steps. The use of metal layers to control the back-plate properties as described represents another aspect of the present invention.

The metal layer or layers present in the back-plate may comprise continuous metal structures or a plurality of metal islands. The metal layers and/or metal structures may or may not be electrically connected to one another but in one embodiment at least some of the metal structures are connected together and arranged, in use, to be connected to ground to provide electrical shielding to the transducer.

As mentioned above the invention will generally be applied to wafer scale processing where multiple devices are formed on a single wafer and then diced into individual die, each having at least one transducer and associated circuitry. All of the embodiments described above are suitable for wafer scale processing.

The invention may involve fabricating a single transducer, with associated electronic circuitry, on a substrate or may comprise fabricating a plurality of transducers on a substrate. For instance an array of transducers may be produced on the same substrate along with integrated electronics for the array. For instance an array of microphones could be provided with electronics for read-out from the microphones for the purposes of noise-cancellation say. Where a plurality of transducers are provided the transducers may have different properties so as to be responsive to different frequencies. The transducers may include at least transducer arranged to transmit and at least one transducer arranged to receive acoustic waves.

Conveniently the method comprises a wafer scale packaging step. In other words the method comprises the step of fabricating a plurality of devices on a wafer, each device comprising at least one transducer and at least one circuit component associated with each transducer, and packaging each device on the wafer. Because the present invention may be implemented using entirely standard CMOS processing steps the method of the present invention is suitable for wafer scale packaging. The use of wafer scale packaging packages each device in parallel and allows for smaller packages than with conventional none wafer scale packaging methods. The application of wafer scale packaging to MEMS transducers with integrated circuitry represents another aspect of the present invention.

Various materials may be used in the embodiments described above and the skilled person will be aware of different material systems that may be used. A convenient material system which is particularly suitable for low temperature CMOS processing comprises silicon nitride for the membrane layer and polyimide as the sacrificial material. Polyimide can be easily deposited and baked at a relatively low temperature to form the required sacrificial structures. Silicon nitride can also be deposited and provides the desired microphone properties.

Where the back-plate comprises at least one layer which is not a functional circuit component dielectric layer, said layer may also comprise silicon nitride.

The membrane electrode and/or back-plate electrode may comprise aluminium.

The metal layers of the circuit components may comprise any suitable metal and may comprise aluminium. The intermetal dielectric (IMD) layers may, for example, comprise PE-TEOS (plasma enhanced tetra-ethyl-ortho-silicate) layers. An interlayer dielectric (ILD) layer may comprise Borophosphosilicate Glass (BPSG).

The present invention therefore fabricates a transducer in the first area and circuit components in the second area of the substrate. As mentioned above the circuit components on the substrate are preferably arranged so as to minimise the size of the required substrate, i.e. the size of the substrate when diced from the wafer. However there will generally be some areas of the substrate which are not used for forming the transducer or the circuit components or any electrical interconnections between the substrates. Whilst such regions of the substrate do not have any function in the finished device it nevertheless can be important to control the processing of these regions. As mentioned above there may also be multiple transducers formed on the same substrate and each may have its own associated circuitry. The circuitry for each transducer may be located separately on the substrate but in some embodiment, especially where general circuit components are provided, the circuitry may be located in one or more common circuitry regions. Such an arrangement may potentially increase the amount of unused substrate. Where multiple transducers are formed on a substrate the first area comprises each area of the substrate where a transducer may be formed and thus may comprise a plurality of distinct regions. Similarly the second area comprises any area of the substrate where circuit components are formed.

Some standard CMOS processes require the whole substrate to have certain properties in order to function correctly. Various steps such as chemical mechanical polishing require variations in feature density of a layer to be limited to achieve correct etch rates. Thus, typically the layout of circuit components in a CMOS ASIC is designed in accordance with certain design rules.

In the present invention however the substrate is used to fabricate circuitry in the second area and the transducer in the first area and there may be areas of the substrate which are not in the first or second areas, i.e. unused areas of the substrate. Generally the area required for the transducer is relatively large compared to the area required for the circuitry and the arrangement of the circuitry and transducer may result in a relatively large amount of unused substrate area. Thus the method may involve fabricating dummy structures in the areas of the substrate not in the first or second areas. The dummy structures are structures which are formed during the fabrication process but which serve no functional purpose in the transducer or associated circuitry. Thus, for example, each metal layer deposited during fabrication of the device will be deposited over the whole layer. The metal layer in the area outside the first and second areas is thus patterned into a plurality of dummy metal structures. The dummy metal structures have a size and spacing so as to provide the required density of metal across the substrate. Other material layers formed during the fabrication of the circuit components may also be formed into dummy structures, for instance floating gate (FG) layers, CPOLY layers and metal-insulator-metal (MiM) layers. The dielectric layers that form the circuit layers are also deposited over the whole substrate and thus, together with the dummy structures form layers on the substrate in the areas outside the first and second areas that have the desired surface properties.

As mentioned the dummy structures are formed outside the first and second areas of the substrate. The second area comprises circuit components which are designed according to any necessary CMOS design rules and hence meet the minimum density requirements. The first area, the area in which the transducer is formed, may also be free from dummy structures so that the dummy structures do not interfere with the fabrication or operation of the transducer. However, in some instances, at least some dummy structures may be fabricated in some layers of the first area.

For instance, as mentioned above, one embodiment of the invention involves formation of the transducer on a plurality of dielectric layers deposited during the processing of the circuit components. In this case dummy structures may be formed in the dielectric layers. It will be appreciated however that this embodiment may include a through hole etch of the substrate and said dielectric layers to provide a back-volume. If dummy structures were used the through hole etch would need to be able to etch through said structures and thus may be a wet etch rather than a dry etch for example.

It will also be noted that in a different embodiment of the invention a plurality of dielectric layers may form at least part of the back-plate of the transducer and that such a back-plate may comprise metal structures for control of stress or other mechanical properties. The metal structures may also be designed to act as dummy structures and provide the require density level.

Conveniently the dummy structures comprise a regular repeating array of isolated dummy structures having a desired size and spacing. In one embodiment at least some of the layers, for instance each metal layer has the same repeating regular array of isolated structures. In one embodiment the dummy structures of one layer overlap with the dummy structures of an adjacent layer. For example one metal layer may be formed as a regular array of dummy structures and the next metal layer may be formed as a regular array of the same size, shape and spacing but with a shift of the pattern so that the structures in the different layers are not aligned with one another but have a degree of overlap. Depending on the size and spacing of the dummy structures the structures in alternate metal layers may be aligned. Such an arrangement maintains the density rules well but also facilitates connections between the layers and the method may involve making at least some connections between the dummy structures in adjacent layers. Connecting at least some of the dummy structures in adjacent layers can be used to prevent unwanted charge build up and further, if the dummy structures are all connected to ground the dummy structures in effect as a shield to electromagnetic interference.

The use of dummy structures in areas of the substrate which do not form part of the circuitry or the transducer, and an apparatus having a MEMS transducer in a first area of a substrate and electronic circuitry in a second area of the same substrate and a plurality of dummy structures on the substrate outside of the first and second areas represents other aspects of the present invention.

The method of the present invention preferably comprises providing at least one sealing region. The at least one sealing region is arranged so that a seal can be created with an appropriate cap. Thus the sealing region is free of any circuit components. One continuous sealing region is provided around the periphery of the substrate, i.e. the substrate when diced from a wafer, to allow for sealing of the substrate to a cap. Additionally or alternatively there may be at least one sealing region disposed between the first area and the second area, i.e. between the transducer and the circuit components. As mentioned above the transducer will be generally open to the environment. Whilst this is necessary for transducer operation exposure of the circuit components to the environment can be detrimental. Humidity in the circuit region can affect device performance and thus a sealing region may be provided between the transducer and the circuitry. Where the circuit components are formed in a single continuous area which is on a separate part of the substrate to the transducer the sealing region between the first and second areas may comprise a region around the periphery of the second region. Where the circuit components are arranged in a plurality of distinct regions on the substrate, each region of circuit components may have a sealing region around the periphery. Alternatively the sealing region between the first area and the second area may be formed around the periphery of the first area, i.e. around the transducer region. This may be beneficial where the second area surrounds the first area for efficient use of space.

The, or each, sealing region may comprise at least one conductive layer and means for connecting the conductive layer to the cap. It is typical to package MEMS transducer devices in conducting containers which are usually grounded to act as Faraday cages and thus prevent EMI. The uppermost layer of the sealing region may be at the same level as the surrounding material or the sealing region may comprise an area which protrudes above the level of the surrounding material, i.e. the sealing region may comprise a sealing structure. The sealing structure can be formed by appropriate CMOS deposition and patterning steps.

Where a sealing region is provided between the circuit components and the transducer the sealing region will be arranged to not interfere with the electrical interconnects between the transducer and the circuit components and any interconnects between different circuit regions. The sealing region may be absent where it encounters an electrical connection or may be arranged to be non conductive in the vicinity of the interconnects.

The method of the present invention as described above can be used to make novel MEMS transducer devices having integrated electronic circuitry. Thus according to another aspect of the invention there is provided an apparatus comprising a capacitive MEMS transducer and at least one circuit component on the same substrate wherein the MEMS transducer comprises a moveable membrane having a membrane electrode and a back-plate having a back-plate electrode and the at least one circuit component comprises a plurality of CMOS layers and wherein at least one of the plurality of CMOS layers forms at least part of the back-plate of the transducer.

This aspect of the invention thus relates to an integrated MEMS transducer and electronics where the transducer and the electronics share material layers in common. The term CMOS layers refers to layers formed by standard CMOS processes as would be well understood by one skilled in the art and refers to the layers which form part of the circuit components. Such layers may, as described above, comprise at least one dielectric layer and at least one metal layer.

The transducer may be arranged with the membrane layer uppermost, i.e. the furthest from the substrate. In this case the back-plate may comprise at least one CMOS layer formed on the substrate. In one embodiment the membrane comprises a planar layer. As mentioned above the use of a planar membrane can be advantageous in terms of stress of the membrane. The planar membrane may be arranged over a cavity formed in at least one of the CMOS layers. Alternatively the planar membrane may be arranged over a cavity formed in a spacer layer.

In one embodiment the apparatus may comprise an acoustic port through the substrate under the transducer. An acoustic port is a channel or series of channels through which pressure waves of interest to the device can effectively pass, i.e. pressure waves to be detected by a sensing transducer such as a microphone and/or those generated by a generating transducer such as a loudspeaker. The term acoustic is used to imply any type of pressure wave and is not restricted to audible sound waves but in one embodiment the transducer is an audible sound transducer.

It will be appreciated that as used herein the terms uppermost, upper, above, below etc. as used in relation to the spacing and positioning of elements on the substrate are purely used to indicate relative positions and do not specify a particular orientation of the apparatus. Thus referring to the acoustic port being formed in the substrate below the transducer serves purely to identify the relevant region of the substrate (i.e. that area of the substrate which is behind the transducer when looking at the transducer along a direction normal to the substrate) and not any particular orientation.

The back-plate layer may comprise at least one dielectric CMOS layer and at least one metal CMOS layer, the metal CMOS layer in the back-plate being arranged to provide predetermined mechanical properties. The arrangement of the at least one metal layer may be designed to impart a desired overall stress to the back-plate.

In another aspect of the invention there is provided an apparatus having a capacitive MEMS transducer with at least one circuit component integrated on the same substrate wherein the transducer has an acoustic port formed in the substrate under the transducer. An integrated MEMS transducer and electronic circuitry which has an acoustic port through the substrate is advantageous and represents another aspect of the present invention. The transducer may comprise a moveable membrane having a membrane electrode and a back-plate having a back-plate electrode wherein the moveable membrane is above the back-plate, i.e. furthest from the substrate.

The MEMS capacitive transducers of the present invention may comprise sensing transducers such as a microphone and/or transmitting transducers such as loudspeakers. Where the apparatus comprises a plurality of transducers on the same substrate there may be one or transmitter and one or more receiver on the same substrate.

The circuit components of the transducer may therefore form suitable audio circuitry. For example the circuitry may comprise any or all of amplifier circuitry, voltage biasing circuitry, filter circuitry, analogue to digital converters and/or digital to analogues converters, oscillator circuitry, voltage reference circuitry, current reference circuitry and charge pump circuitry.

In another aspect of the present invention there is provided an apparatus having a MEMS capacitive transducer and at least one circuit component, the at least one circuit comprising a plurality of dielectric layers and a plurality of metal layers wherein the transducer back-plate comprises at least one of said dielectric layers and at least one of said metal layers and wherein the arrangement of the metal layers in the back-plate is chosen so as to provide the desired mechanical properties.

In a further aspect of the invention there is provided a method of forming a back-plate of a MEMS transducer formed on a substrate comprising the step of using at least one dielectric layer and at least one metal layer, which is deposited to form at least part of some circuitry on the substrate, to form at least part of said back-plate and arranging the at least one metal layer of the back-so as to provide the desired mechanical properties of the back-plate.

As mentioned above, another aspect of the present invention provides a method of forming a MEMS transducer having a moveable membrane comprising the steps of: forming a cavity in a first layer; filling said cavity with sacrificial material; and forming a membrane having a membrane electrode over said cavity such that the membrane is planar. The capacitive MEMS transducers of the present invention, or made by the methods of the present invention, may be used in a variety of applications such as medical ultrasound imagers and sonar receivers and transmitters, as well as mobile phones, PDAs, MP3 players and laptops for gesture recognition purposes. The transducers are particularly suitable for portable devices. For instance the transducer may be a MEMS microphone and the microphone may be used in a mobile device such as a mobile phone or other communication device, a personal data assistant or a laptop.

The invention will now be described by way of example only with respect to the following drawings, of which:

Figure 1 shows a known capacitive MEMS transducer;

Figure 2 shows a cross section of some typical CMOS circuitry;

Figure 3 illustrates an integrated MEMS transducer and circuitry arrangement according to one embodiment of the invention;

Figures 4a - 4o illustrate the processing steps involved in a method for fabricating the integrated transducer and circuitry arrangement shown in Figure 3;

Figure 5 shows an integrated MEMS transducer and circuitry arrangement according to another embodiment of the invention;

Figures 6a -6o illustrate the process steps involved in fabricating the structure shown in Figure 5 according to an embodiment of the invention;

Figure 7a shows an integrated MEMS transducer and circuitry arrangement according to another embodiment of the invention;

Figure 7b shows a variant of the embodiment shown in figure 7a; Figures 8a -8n illustrate the process steps involved in fabricating the structure shown in Figure 7a according to an embodiment of the invention;

Figure 9 illustrates a transducer having a back-plate consisting of IMD/ILD layers and metal layers;

Figure 10 shows an integrated MEMS transducer and circuitry arrangement according to a further embodiment of the invention;

Figures 1 1a -1 1o illustrate the process steps involved in fabricating the structure shown in Figure 10 according to an embodiment of the invention;

Figure 12 shows a possible layout of the transducer and circuitry region on a substrate; and

Figures 13a and 13b illustrate one embodiment of a pattern of dummy structures for the substrate outside the transducer and circuitry regions.

The examples described below will be described in relation to integration of a MEMS microphone with some CMOS circuitry but it will be appreciated that the general teaching applies to other capacitive MEMS transducers such as loudspeakers and pressure sensors.

Figure 3 shows an MEMS transducer, generally indicated 300 and an example of some CMOS circuitry 302 integrated on a substrate 304. The MEMS transducer is formed on top of dielectric layers 306 and comprises a membrane 308 having a membrane electrode 310 and a back-plate 312 having an embedded backplate electrode 314. The membrane electrode is electrically connected to contact 316 which is connected (not shown) to contact 320 of the circuitry. The back-plate electrode 314 is connected to contact 318 and through to contact 322 of the circuitry. It will be seen that the electrical connections between the transducer 300 and circuitry 302 are embedded in a protective/passivation layer, which is formed from the same material as the back-plate 312. Contact holes 324 and 326 are provided for connecting the circuitry to off chip components. Figures 4a - o illustrate the method of fabrication of the device shown in Figure 3.

First the necessary CMOS circuitry 302 is fabricated in a circuitry region using standard processing techniques such as ion implantation, photomasking, metal deposition and etching. The circuitry may, without limitation, comprise some or all of amplifier circuitry, voltage biasing circuitry, filter circuitry, analogue to digital converters and/or digital to analogues converters, oscillator circuitry, voltage reference circuitry, current reference circuitry and charge pump circuitry. The circuitry is fabricated such that dielectric layers, such as CMOS inter-metal dielectric (IMD) or inter layer dielectric (ILD) layers, are deposited over the area where the transducer is later to be fabricated. Figure 4a illustrates the substrate after processing of the circuitry up to depositing and patterning of the final metal layer.

It will be appreciated that the circuitry layers will actually be varied across the circuitry region of substrate to form distinct components and interconnections between components. The circuitry layers illustrated in figure 4a, and in the all the following examples, are for illustration purposes only. For the purposes of explaining the invention the contacts between different parts of the circuitry and the membrane and back-plate electrodes will be shown but the skilled person will appreciate that the respective connections may in practice be in separate regions of the device. Further in all of the examples a three metal layer CMOS circuitry arrangement is shown for purposes of illustrating the invention but the skilled person will be aware of other arrangements that may be used.

Referring back to Figure 4a, at this stage the processing steps for fabricating the circuitry are essentially complete apart from the provision of electrical contacts and a passivation layer.

As shown in Figure 4b the next step is deposition of a further dielectric layer 402. This layer may comprise the same material as the previous intermetal dielectric (IMD) layers used for the circuitry and may for example comprise plasma enhanced TEOS. Dielectric layer 402 is then planarised, for example using chemical mechanical polishing (CMP). This planarised dielectric layer forms the surface on which the transducer will be fabricated and forms part of the passivation layer for the circuitry 302. The thickness of the dielectric layer above the circuitry layer may be in the region of 0.3μm.

A layer of sacrificial material such as polyimide is then deposited and baked before being etched back to the desired thickness, for example in the range of 1 - 5 μm. The polyimide layer is then patterned with photoresist and, as shown in Figure 4c, etched to leave a shaped sacrificial layer 404 which will define the membrane that will be left behind when the sacrificial layer is removed. The polyimide layer will also later act as an etch stop for a back-side etch as will be described.

Next a membrane layer 406 is deposited as shown in Figure 4d. In a preferred embodiment the membrane layer comprises silicon nitride and is deposited using a plasma enhanced chemical vapour deposition (PECVD) process to a thickness of about 0.4μm for example. A membrane electrode layer is also deposited and patterned to form membrane electrode 310 connected via an interconnection track (not shown) to a contact pad 408. The membrane electrode may comprise any suitable metal which is compatible with CMOS processing, such as aluminium, and may be deposited by sputtering. The thickness of the membrane electrode may be about 0.05μm.

The membrane layer 406 is then patterned with photoresist and etched to remove any material of the membrane layer from above the circuitry region and to open relief holes 410 in the membrane as shown in Figure 4e.

A further layer of sacrificial material such as polyimide is then deposited and baked to result in a layer thickness of about 2.2μm. This layer of sacrificial material is patterned with photoresist and etched to produce, as shown in figure 4f, a sacrificial structure 412 which will define the air gap between the membrane and the back-plate. This sacrificial structure 412 is preferably further patterned and etched to form a dimpled pattern on the top surface. This dimpled pattern will be transferred to the subsequently deposited back-plate layer and will help reduce stiction effects in use should overpressure situations cause the moveable membrane to come into contact with the back-plate. A first back-plate layer 414 is then deposited as illustrated in Figure 4g. The first back- plate layer is preferably the same material as the membrane layer such as silicon nitride. The back-plate layer may be deposited by PECVD to a thickness of about 0.3μm. Next, as shown in Figure 4h, a back-plate electrode layer is deposited and patterned to form the back-plate electrode 314 connected by an interconnect track (not shown) to a contact pad 416. The back-plate electrode is conveniently formed from the same metal as the membrane electrode, such as aluminium, and may be of the order of 1 μm thick.

A further back-plate layer is then deposited as shown in Figure 4i to encapsulate the back-plate electrode 314. The further back-plate layer is preferably the same material as the first back-plate layer, e.g. silicon nitride and may be deposited to a thickness of about 1.5μm. Following this deposition step, as shown in Figure 4j, via holes are opened in the back-plate layer material to expose contact pads 408 and 416 and also to the top metal layer of the circuitry 302. The via holes are formed by applying photoresist, patterning and performing a suitable etch.

As shown in Figure 4k the via holes may be filled with a suitable metal and an metal layer deposited and patterned on top of the back-plate material layers to form interconnection tracks 418 between the contact pads 408 and 416 of the MEMS device and the circuitry 302 (only the track between contact pad 416 and the circuitry is shown for clarity). The metal interconnects may be a combination of metal such as titanium for adhesion and aluminium.

A final back-plate layer is then deposited as shown in Figure 4I. The final back-plate layer is conveniently the same material, e.g. silicon nitride, as the other back-plate layers but different materials may be used for one or more of the different back-plate layers if desired. The use of different material layers can be used to control the properties of the back-plate and provide desired stress characteristics to the back- plate. However the use of a single material such as silicon nitride for all of the back- plate layers is convenient and produces a back-plate having the necessary properties. The final back-plate layer may be deposited to a thickness of the order of 1.5μm. Next, referring to Figure 4m, the final layer of back-plate material is patterned with photoresist and etched to form release holes 420 through the back-plate of the MEMS transducer and also to expose contact holes 422 for external connections to the circuitry, i.e. signal out contacts, power in contacts, connections for testing etc.

A further sacrificial material coating 424 is then applied over the device as shown in figure 4n to provide protection to the transducer and circuitry contacts during the backside processing steps. The back-side processing steps involve a back grind of the substrate to reduce the thickness, for instance down to a thickness of the order of 500μm or so. After back grinding a through hole etch is conducted in the area under the transducer. As mentioned above the first layer of sacrificial material can act as an etch stop to this through hole etch and thus no separate etch stop layer is required. The first layer of sacrificial material may also be removed leaving the structure shown in figure 4o. Finally the covering of sacrificial material and remaining sacrificial material in the transducer device may be removed to leave the completed transducer.

The method of this embodiment of the present invention described above with reference to Figure 4a - 4o uses entirely standard CMOS processing steps to form the structural layers and may be conducted as a continuous process in a single standard CMOS foundry. There is no need for post-CMOS processing steps for device fabrication other than packaging and possibly the back processing steps. The method of the present invention therefore offers a truly CMOS process for the fabrication of integrated transducers and electronics.

The method of the present invention also merges transducer processing steps and circuitry processing steps. As described above, the back-plate of the transducer is formed by deposition of three layers of back-plate material and these layers of back- plate material comprise part of the passivation layer of the circuitry 302. Further the photomask used to define the release holes 420 in the transducer back-plate is also used to define the contact holes for external connection to the transistor circuitry. The merging of electronics processing steps and transducer processing steps is an advantage in terms of ease and cost of manufacture. Reducing the number of processing steps and, in particular, the number masks required can offer significant costs savings in terms of production cost. Whilst the method described with reference to Figures 4a to 4o therefore usefully merges some processing steps it is possible to further merge the transducer processing steps and circuitry processing steps to provide further gains in terms of manufacturing savings.

Figure 5 shows an arrangement of integrated transducer and electronics according to an alternative arrangement of the invention. Here transducer 500 is integrated with circuitry 502 but in this embodiment several of the functional layers of the transducer are shared with functional layers of the circuitry 302. The functional layers of the transducer are those layers which form the working parts of the transducer, i.e. the membrane, membrane electrode, back-plate and back-plate electrode. Functional layers of the circuitry comprise layers which form a metal or oxide layer of a CMOS circuit component.

The transducer 500 has a membrane layer 508 carrying a membrane electrode 510 and a structurally rigid back-plate 512. In this embodiment the transducer is formed on top of only some of the dielectric IMD/ILD layers 506 of the circuitry 302 and actually incorporates the other IMD layers 520 as part of the back-plate 512. Thus some of the functional back-plate layers of the transducer are shared with the circuitry as IMD layers. Further the back-plate electrode 514 is formed at the same time as the metal layer M3 of the circuitry as will be described below and hence the metal layer is shared.

Figures 6a to 6o illustrate a method of fabricating this embodiment of the invention. CMOS processing of the substrate 504 and formation of first and second metal layers is performed according to standard CMOS processing. As described above the fabrication of the circuitry comprises standard CMOS processing techniques such as ion implantation, photomasking, metal deposition and etching. Again the circuitry may, without limitation, comprise some or all of amplifier circuitry, voltage biasing circuitry, filter circuitry, analogue to digital converters and/or digital to analogues converters, oscillator circuitry, voltage reference circuitry, current reference circuitry and charge pump circuitry. The circuitry is fabricated such that dielectric layers are deposited over the area where the transducer is later to be fabricated. Following processing of the circuitry up to deposition and patterning of a second metal layer as described, a relatively thick layer 602 of IMD is deposited. The IMD material may for instance be PE-TEOS deposited to a thickness of 2.5μm or thereabouts.

As shown in figure 6b a well 604 is then etched through the IMD layer 602 and into the underlying IMD/ILD layers. The well is formed by conventional CMOS photolithography and etching. The well should be deep enough to allow for movement of the membrane 508 in use.

As shown in figure 6c a layer of sacrificial material is then deposited over the substrate to a thickness sufficient to ensure that the well 604 is completely filled. The sacrificial material may be polyimide and is baked after deposition. The sacrificial material is then etched back to the uppermost IMD layer 602 in the area outside of the well as shown in figure 6d and then the surface is planarised and thinned such that the IMD layer has an appropriate thickness in the circuitry region. It will be appreciated that the step of planarising needs to provide a plane surface in material which varies from IMD material outside the well to sacrificial material within the well. A CMP process may be used for planarisation, resulting in the structure shown in figure 6e.

Next a membrane layer 606 is deposited. Similarly to the embodiment described above the membrane layer may comprise silicon nitride and may be deposited to a thickness of about 0.4μm. A membrane electrode layer comprising a suitable metal material such as aluminium is then deposited, for example by sputtering to a thickness of 0.05μm or so, and patterned to form the membrane electrode 510 having a connecting track (not shown) to a contact pad 608 as shown in figure 6g.

The membrane layer above the circuitry regions is then removed in a photolithography step and, in the same step, relief holes are formed in the membrane 508 as shown in Figure 6h.

A further coating of sacrificial material such as polyimide is then deposited and baked to result in a layer thickness of about 2.2μm. This layer of sacrificial material is patterned with photoresist and etched to produce, as shown in figure 6i, a sacrificial layer 612 which will define the air gap between the membrane and the back-plate. This layer of sacrificial material is preferably further patterned and etched to form a dimpled pattern on the top surface. This dimpled pattern will be transferred to the subsequently deposited back-plate layer and will help reduce stiction effects in use.

An IMD layer 614 is then deposited as illustrated in Figure 6j. The IMD layer 614 is deposited to the thickness required for the circuitry and may be any suitable IMD material, such as PE-TEOS. The IMD layer is patterned using photolithography to etch the necessary contact holes 616 in the circuitry region and also to expose contact pad 608 which connects to the membrane electrode. The IMD layer is not however removed from the transducer structure and IMD layer 614 also comprises a first back- plate layer for the transducer. In this aspect of the invention therefore the functional IMD layer 614 which forms part of the circuitry also forms part of the functional structure of the transducer.

Next, as shown in Figure 6k, a metal layer is then deposited and patterned. This metal layer is patterned to form the back-plate electrode 514 and the required metal M3 layer 618, 620, 622 of the circuitry. The metal layer is also patterned to form a direct interconnect track (not shown) between the back-plate electrode 514 and the relevant part of the M3 layer of the circuitry 620. Further the metal layer forms a contact 624 and interconnecting track (not shown) which electrically connects the relevant part of the circuitry 618 to contact pad 608 and hence to membrane electrode 510. The metal layer may be any suitable metal material such as aluminium and may be deposited to a thickness of the order of 1 μm or less.

In this embodiment of the invention therefore a single deposition step and single patterning step (and hence a single photo mask) is all that is required to provide the back-plate electrode, the M3 layer for the circuitry and necessary electrical connections. As mentioned above a reduction in the number of process steps and the number of masks required can significantly reduce the cost of manufacture of the device.

Following the metal patterning step a further dielectric layer is deposited which forms part of a passivation layer for the circuitry and a second back-plate layer for the transducer. The dielectric layer may conveniently comprise the same material as the IMD layer 614, such as PE-TEOS of the order of 0.3μm. This is followed by deposition of a further back-plate layer 628. This further back-plate layer may be chosen to ensure the correct structural properties, such as stress, of the back-plate 512 of the finished transducer and may comprise silicon nitride. The material also forms part of the passivation layer over the circuitry.

The back-plate layer 628 is then patterned by appropriate photolithography steps to form release holes 630 in the transducer back-plate 512 and also to open contact holes for external contacts to the circuitry, i.e. signal out contacts, power in contacts etc.

A further sacrificial material coating 634 is then applied over the device as shown in figure 6n to provide protection to the transducer and circuitry contacts during the backside processing steps. The back-side processing steps involve a back grind of the substrate to reduce the thickness, for instance down to a thickness of the order of 500μm or so. After back grinding a through hole etch is conducted in the area under the transducer. In a similar manner as described above in relation to the first embodiment of the invention the layer of sacrificial material in the well can act as an etch stop to this through hole etch and thus no special etch stop layer is required.

Finally all the sacrificial material may be removed to leave the finished device.

The method of this embodiment of the present invention described above with reference to Figure 6a - 6o also uses entirely standard CMOS processing steps (apart from possibly the back-processing steps) and may be conducted as a continuous process in a single standard CMOS foundry. Again there is no need for post-CMOS processing steps other than packaging. The method of the present invention therefore offers a truly CMOS process for the fabrication of integrated transducers and electronics.

The method of this aspect of the present invention also merges several transducer processing steps and circuitry processing steps and results in a structure wherein the circuitry and the transducer comprise functional layers in common. As described above the back-plate comprises IMD material layers and the M3 layer of the CMOS circuitry is formed from the same metal layer as the back-plate electrode. As described this approach reduces the number of processing steps and allows transducer fabrication and the circuitry fabrication to be performed in the same steps and using shared masks.

Further embodiments of integrated transducers and electronic circuitry are shown in Figures 7a and 7b. The transducers shown in Figures 7a and 7b are different to those shown in Figures 3 or 5 in that the moveable membrane 708 is formed as the uppermost layer of the transducer 700, in the sense of being furthest from the substrate 704. In the embodiment shown in Figure 7a the back-plate 712 is formed by the ILD/IMD layers 706 on the substrate 704. The membrane has a membrane electrode 710 and a back-plate electrode 714 is provided on top of ILD/IMD stack 706. Contacts 716 and 718 connect the membrane electrode and back-plate electrode respectively to contacts 722 and 720 with the circuitry 702. The back through hole in this embodiment represents the acoustic port for transmission of the acoustic waves to the membrane.

The embodiment shown in Figure 7b is similar to that shown in figure 7a but has a membrane structure which comprises a membrane layer supported by vertical sidewalls. The layer corresponding to the moveable membrane effectively continues for a significant distance beyond the cavity. Such a structure may be beneficial in terms of stress. For a membrane structure with thin side walls, such as shown in Figure 1 , the use of vertical sidewalls may actually concentrate too much stress at the join between the moveable part of the membrane and the sidewalls and thus a slanted sidewall such as shown in Figure 7a may be preferred. However extending the thickness of the side wall and supporting the membrane later using such a thick sidewall can improve the stresses even further. When producing a stand alone transducer on its own chip typically the size of the chip should be as small as possible and hence the minimum width sidewalls are preferred. However, when the transducer is integrated with circuitry, the membrane layer can extend to areas between the transducer and the circuitry or even over the circuitry itself with no impact on size of the resulting integrated chip.

The embodiment shown in Figure 7b also has the electrical contact between the back- plate electrode and the circuitry implemented at a different level in the device to the contact 716, 720 between the membrane electrode and the circuitry. The embodiments of the invention shown in Figures 7 a and 7b again uses common layers to provide both functional layers of the circuitry and functional components of the transducer, namely the back-plane 712. These embodiments of the invention therefore eliminate the need for separate processing steps to form a back-plate.

A method of fabrication of the device shown in Figure 7a is illustrated with reference to figures 8a - 8n.

First the necessary CMOS circuitry 702 is fabricated in a circuitry region using standard processing techniques such as ion implantation, photomasking, metal deposition and etching. As described above in relation to the other embodiments of the invention, the circuitry may, without limitation, comprise some or all of amplifier circuitry, voltage biasing circuitry, filter circuitry, analogue to digital converters and/or digital to analogues converters, oscillator circuitry, voltage reference circuitry, current reference circuitry and charge pump circuitry. The circuitry is fabricated such that dielectric layers are deposited over the area where the transducer is later to be fabricated. Once the final metal layer has been deposited and patterned a further dielectric layer 802, which may comprise the same material as the previous IMD layers and may for example comprise plasma enhanced TEOS, is deposited and planarised, for example using chemical mechanical polishing (CMP). At this point the processing of the circuitry is essentially complete apart from the provision of contacts and contact holes.

Following the circuitry processing, which also has the effect of providing the back-plate material of the transducer, a back-plate electrode layer is deposited, patterned and etched as shown in Figure 8a to form a back-plate electrode 714 electrically connected via a connection track (not shown) to a contact pad 804. The electrode layer may comprise any suitable material such as aluminium and may be deposited by sputtering say to a thickness of about 1 μm. Alternatively, as shown in Figure 7b, prior to deposition of the back-plate electrode a contact hole to the relevant circuitry could be etched in the top IMD layer. The subsequent metal deposition could then provide metal for the contact with the circuitry, the back-plate electrode and the interconnecting track. Referring next to figure 8b, release holes 806 are etched through the IMD/ILD layers 706 down to the substrate 704. Whilst the metal of the back-plate electrode layer could be used as the mask for the release holes it is preferred to define the release holes by using a separate photolithography step.

A first layer of sacrificial material such as polyimide is then deposited and baked. The polyimide layer is then patterned with photoresist and, as shown in Figure 8c, etched to leave a shaped sacrificial layer 806 which will define the membrane that will be left behind when the sacrificial layer is removed.

Whilst this step of the process may involve a single deposition of polyimide as described it may be beneficial to perform a two stage deposition. Polyimide deposited in a single stage may end up having a profile on its top surface which includes recesses corresponding to the position of the release holes. This top surface profile of the sacrificial material will transfer (as the inverse profile) to the membrane layer deposited on top of the sacrificial layer and could have an effect on membrane properties and hence performance of the microphone. Thus it may be advantageous to deposit a first layer of sacrificial material to fill the release holes and then etch back to the top IMD/ backplate electrode, i.e. remove all sacrificial material outside the release holes 806. Sacrificial material deposited in a second deposition step, with the release holes already filled, will have a much flatter surface profile. Thus the method may involve such a second sacrificial material deposition step and it is after the second deposition step that the material is patterned and etched to form the sacrificial layer 808 shown in Figure 8c.

It should be noted that the process for the manufacture of the structure shown in Figure 7b varies from that described above. Instead of simply forming a stand-alone sacrificial structure such as 808, the method involves filling a well with sacrificial material in a similar manner as described above with relation to Figures 6a - 6e. Thus a first layer of material such as silicon nitride is deposited and a well is etched to define the required cavity and the well is filled with sacrificial material and planarised.

Next a membrane layer 810 is deposited as shown in Figure 8d. In a preferred embodiment the membrane layer comprises silicon nitride and is deposited using a PECVD process to a thickness of about 0.4μm for example. A membrane electrode layer is also deposited and patterned, as shown in figure 8e, to form membrane electrode 710 connected via an interconnection track (not shown) to a contact pad 812. The membrane electrode may comprise any suitable metal which is compatible with CMOS processing, such as aluminium, and may be deposited by sputtering. The thickness of the membrane electrode may be about 0.05μm.

The membrane layer 810 is then patterned with photoresist and etched to open relief holes 814 in the membrane as shown in Figure 8f.

A further layer of sacrificial material such as polyimide is then deposited, baked and etched back to achieve a layer thickness of about 1 μm. This layer of sacrificial material is patterned with photoresist and etched to produce, as shown in figure 8g, a sacrificial layer 816 which has a shape which substantially corresponds to a continuation of the internal sidewalls of the membrane layer in the transducer. A layer of strengthening material 818 is then deposited as shown in figure 8h. The purpose of the sacrificial layer 816 and strengthening layer 818 is to effectively increase the thickness and hence strength of the membrane sidewalls without increasing the thickness of the moveable part of the membrane. Conveniently therefore the layer of strengthening material comprises the same material as forms the membrane layer, such a silicon nitride, deposited to a suitable thickness such as around 1.5μm.

As shown in Figure 8i contact holes to contact pads 812 and 804 are then opened up through the strengthening layer 818 and, in case of contact pad 804, membrane layer 810. The contact holes are opened by photolithography using the metal of the contact pads as an etch stop.

Contact holes are also opened up to the circuitry through the strengthening layer, membrane layer and top layer IMD as shown in Figure 8j. Although shown as two steps in Figures 8i and 8j all the contact holes could be opened in a single step using an appropriate etch. It will be appreciated that if the contact between the back-plate electrode and circuitry had previously been fabricated already, such as described above in relation to the embodiment of Figure 7b, then only contact holes for connection of the membrane electrode to the circuitry are required. A metal layer is then deposited and patterned to form electrical contacts 716, 718, 722 and 720 as shown in Figure 8k along with connecting tracks (not shown) between the appropriate contacts.

For the embodiment shown in Figure 7a a further etch step is then performed to open a contact hole 820 to the circuitry to allow for external connection (only one such contact hole 820 is shown in Figure 8I for clarity). This etch step also removes material of the strengthening layer from above the membrane layer. This provides a release hole for later removal of the sacrificial material but also ensures that the area above the membrane can be part of a back volume. However for the embodiment shown in Figure 7b where there is a protective layer burying the electrical contact between the membrane electrode and the circuitry there will be an additional deposition step of a protective material such as silicon nitride prior to this etching step.

The front surface of the structure is then coated with a relatively thick layer of sacrificial material such as polyimide coating of the order of 3μm or so to provide protection of the structure during the back side processing. The coating is baked and then the backside processing starts. This comprises a back side grind to reduce the thickness of the substrate, say to about 500μm, followed by a through hole etch as shown in figure 8m. Finally the polyimide can be removed to leave the finished structure shown in Figure 8n.

The method of the present invention described above with reference to Figures 8a - 8n to produce the embodiments shown in Figures 7a and 7b again uses entirely standard CMOS processing steps and thus may be conducted as a continuous process in a single standard CMOS foundry. Again there is no need for post-CMOS processing steps for device fabrication other than packaging. The method of the present invention therefore offers a truly CMOS process for the fabrication of integrated transducers and electronics.

As mentioned above in the embodiments of the invention shown in Figures 7a and 7b the back-plate of the transducer is formed by the IMD/ILD layers deposited during processing of the circuitry. Hence the functional layers of the transducers of 7a and 7b share common layers with the functional layers of the circuitry. The method according to this aspect of the invention avoids the need for fabrication of a separate back-plate.

Although the layers which form the back-plate 712 of the transducer 700 shown in figures 7a and 7b are illustrated as being purely IMD/ILD layers 706 the back-plate may incorporate metal structures into the layers which are deposited at the same time as the metal layers in the circuitry. The metal structures would be deposited in a pattern so as not to interfere with the subsequent etch of the release holes through the back- plate. The pattern of the metal structures deposited in the back-plate layer can be designed to provide the back-plate layer with the desired mechanical properties and in particular can be used to control the stress in the back-plate. Figure 9 illustrates a transducer 900 having a membrane 908 with membrane electrode 910 suspended above a back-plate 912 with consists of IMD/ILD layers 906 and metal layers 930. Although three metal layers are shown corresponding to the three CMOS metal layers the back-plate 912 may comprises fewer metal layers than CMOS circuitry. Each metal layer in the back-plate may have a different pattern. A metal layer in the back- plate 912 may comprise one or more continuous structures or may comprise an array of discrete metal islands. Where the metal layers 930 are provided to achieve desired mechanical properties of the back-plate layer the metal layers may be isolated, i.e. not electrically connected to any controlled voltage source. The metal layers may or may not be electrically connected to one another. However, in one embodiment at least one metal layer is arranged to be connected to ground in use so as to effectively provide electric shielding of the transducer electrodes from interference.

Figure 10 shows embodiment of the invention having an integrated transducer 1000 and circuitry 1002 where the membrane is the uppermost layer of the transducer 1000. The embodiment shown in Figure 10 shares a number of layers between the circuitry and the transducer. In the illustrated embodiment the back-plate 712 is provided by the base ILD layer of the circuitry with a back-plate electrode 1014 disposed on top. The back-plate electrode 1014 is part of the first metal layer M1 of the circuitry. The transducer 1000 has a planar membrane layer 1008 and thus has no stress associated with any corners and is supported above and below by IMD layers of the circuitry. A method of fabricating the integrated transducer and circuitry arrangement shown in figure 10 is described with reference to figures 1 1a to 1 1o.

The substrate is initially processed for CMOS circuitry and ILD layer 1102 is deposited, patterned and etched. A metal layer is then deposited and patterned to form back- plate electrode 1014 and also the first metal layer M1 of the circuitry. An IMD layer 1 104 is then deposited to give the structure shown in Figure 11 a. Next the IMD layer 1 104 is patterned and the second metal layer of the circuitry is deposited any patterned. A further IMD layer is then deposited as shown in figure 1 1 b.

A well 1 108 is then etched in the IMD layers 1104 and 1 106 to define the cavity between the membrane of the transducer and the back-plate. Release holes 1 110 are also etched through ILD layer 1 102 to the substrate. The back-plate electrode metal may be used as the mask for the release holes 11 10.

A thick layer of sacrificial material 11 12 is then deposited as shown in figure 1 1d. For instance a polyimide coating may be applied and baked. The structure is then planarised back to the level of the IMD layer 1106. The planarisation process need to work with both the sacrificial material within the well and the IMD layer outside of the well. A CMP process may be used to give the desired planar surface as shown in figure 1 1e.

A membrane layer 11 14 is the deposited over the surface as shown in figure 1 1f. The membrane material may be any suitable material such as silicon nitride deposited to a thickness of 0.3μm or so. Next, as shown in figure 1 1 g, a thin metal layer is deposited and patterned to form the membrane electrode 1010 linked by a conducting track, not shown, to a contact pad 11 16.

The membrane layer is then etched using photolithography to open relief holes 1 1 18 in the membrane layer and to remove membrane layer material above the circuitry region. It will be noted however that the membrane layer is planar and hence has no stress concentration at any corner parts. A further layer of sacrificial material such is deposited and patterned and etched to form a structure 1120 above the transducer region as shown in figure 1 1 i. The sacrificial material is preferably the same material used for the well and may be polyimide. The deposition step may therefore include baking the polyimide.

The nest stage is deposition of a further IMD layer 1122. This IMD layer is patterned and etched to expose contact pad 1 116 and the relevant circuitry as shown in figure 1 1j. A further metal layer is deposited and patterned, as shown in figure 1 1 k, to form metal layer M3 of the circuitry and contact 1016, connected via tracks, not shown, to the relevant circuitry.

A further layer of IMD material 1124 and protective layer 1 126 are then deposited as shown in figure 1 11 to form a passivation layer of the circuitry. The IMD layer may be a layer of PE-TEOS deposited to a thickness of about 0.3μm and protective layer 1 126 may be the same material as membrane layer 1008, such as silicon nitride, with a thickness of about 1.5μm.

As shown in figure 11 m contact holes 1128 may then be opened up to allow for external connections to the circuitry. Further protective layer material 1 126 and IMD layers 1 122 and 1 124 are removed from above the transducer membrane to open up a back volume. The entire structure is then coated in sacrificial material as shown in figure 11 n to protect it during back side processing. Back side processing involves a back grind to reduce substrate thickness followed by a through hole etch to form a sound port for the device. Finally the sacrificial material is removed to reveal the finished structure.

The finished transducer and integrated electronics arrangement has a high number of common layers between the circuitry and the transducer.

Figure 12 illustrates a plan view of substrate 1200 having a transducer area 1202 and a circuitry region 1204. It will be understood that the arrangement shown in Figure 12 is only one of a number of possible arrangements and is illustrated as an example only. The arrangement of Figure 12 is not particularly efficient in terms of utilisation of substrate space and arrangement of the circuitry region around the transducer would, for instance, allow a reduction in the required substrate size.

The circuitry region 1204 will comprise a plurality of circuit components. For instance, if a MEMS microphone is formed in the transducer area 1202, the circuitry region may comprise voltage biasing circuitry and signal read out circuitry. The circuitry region will comprise connection pads for making off chip connections, for instance to a power supply unit and a signal out connection. It will be appreciated that when packaged the transducer area will be open to the environment in order to allow transmission of acoustic waves into or out of the package. The circuitry region is therefore surrounded by a sealing region and in fabrication of the device a seal ring is formed in the sealing region. The seal ring is designed to match with a corresponding sealing region on a package cap and thus seal the circuit region from the rest of the substrate. Thus whilst the transducer area is necessarily open to the environment, the circuitry region, which as explained may have exposed contact regions, is protected for humidity and contaminants and the like.

The seal ring may be formed by standard CMOS processes as conveniently comprises at least one conducting layer. The seal ring is preferably arranged to form an electrical contact with the cap when packaged to help form a Faraday cage around the circuit region to reduce EMI. It will be apparent however that the electrical connections between the transducer and the circuitry region will need to cross the sealing region.

Clearly any part of the sealing region in contact with the interconnect region must be insulating.

A second sealing region 1208 is provided around the periphery of the substrate to provide a seal ring for the entire substrate.

As can be seen from Figure 12 there may be relatively large areas of the substrate which are not in the transducer area 1202 or the circuitry region 1204, although careful design of the layout may reduce such areas. Whilst such areas of the substrate are unused in the finished transducer or circuitry the entire substrate will be subject to the processing steps used during device formation. Some CMOS processing steps may require certain material properties to function correctly. For instance chemical mechanical polishing, used in several etch steps, tends to require a certain density of material. In order to maintain these density ranges for instance dummy features may therefore be formed on the regions of the substrate outside of the first and second areas. The dummy features are patterns of material deposited in the CMOS processing steps which are arranged to ensure that the area outside the transducer region and circuitry region have the correct density as the device is fabricated, thus ensuring that the CMOS process steps can function correctly.

Dummy structures may be formed in the unused areas of the substrate for any of the non IMD/ILD layers deposited during circuit formation and for any metal layers deposited in the transducer fabrication or formation of interconnects between the transducer and the circuitry. Thus the unused areas of the substrate may comprise dummy features consisting of any of the layers used in the fabrication of the transducer and/or circuitry, for instance the dummy structures may comprise floating gate (FG) layers, polycrystalline, e.g. polysilicon, (CPOLY) layers, metal layers M1 , M2 or M3 of the circuit components, MiM layers, metal layers of the back-plate electrode and membrane electrode of the transducer (if different to the M1 , M2 or M3 layers), and interconnect metal layers.

The dummy structures may be formed as a repeating array of structures. The dummy structures in the various layers may share substantially the same pattern. The dummy structures in different layers may be aligned or different layers may share the same pattern but with an effective phase slip in the pattern so the structures are not aligned. Figures 13a and 13b show one example of a dummy structure pattern, Figure 13a shows the pattern in plan via and Figure 13b illustrates the dummy structures in cross section. The dummy pattern is illustrated with six metal layers but as will be apparent from the discussion above the number of metal layers can be reduced by sharing metal layers between the transducer and the circuitry.

The pattern shown in Figure 13a uses a repeating pattern of dummy structures, in this case square structures although other shapes could of course be used. The size and arrangement of the structures is chosen to meet the density requirements for the material. Thus all metal layers have a pattern of the same size and spacing of structures but alternating metal layers uses pattern A 1302 or pattern B 1304. Pattern A is the same as pattern B but with half a period phase slip in each direction. The FG layers also use pattern A. The CPOLY and MiM layers use patterns A and B but with different sized dummy structures.

The resulting cross sectional structure is shown in Figure 13b with the

ILD/IMD/transducer layers separating the various dummy features. The dummy features in various layers are connected by vias 1306 or contacts so that dummy features are electrically connected. This offset repeating pattern facilitates electrical interconnection of the layers. The dummy features may be connected to ground and thus contribute to electrical shielding of the device.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A method of fabricating a MEMS transducer and at least one circuit component on a substrate comprising the steps of: forming, on a first area of a substrate, a plurality of back-plate layers, at least one sacrificial structure and at least one membrane layer such that removal of the at least one sacrificial structure results in a moveable membrane and rigid back-plate; and forming on a second area of said substrate at least one circuit component from a plurality of circuit layers, wherein said method comprises depositing a plurality of common layers of material which form at least some of back-plate layers in the first area and also form at least some of the plurality of circuit layers in the second area wherein said plurality of common layers comprise at least one metal layer and at least one dielectric layer.

2. A method as claimed in claim 1 wherein the method comprises standard complementary-metal-oxide-on-semiconductor (CMOS) processing steps.

3. A method as claimed in claim 1 or claim 2 wherein at least one metal layer of said common layers comprises a back-plate electrode layer in the first area.

4. A method as claimed in any preceding claim wherein at least one metal layer and at least one dielectric layer of said common layers comprising structural back- plate layers in the first area.

5. A method as claimed in any preceding claim comprising forming the circuit layers, into a plurality of circuit components in the second area.

6. A method as claimed in any preceding claim wherein the second area may substantially surround the first area.

7. A method as claimed in any preceding claim wherein the second area comprises a plurality of distinct regions of the substrate.

8. A method as claimed in any preceding claim comprising depositing a layer which forms a membrane layer of the transducer which also forms a passivation layer for the circuit components.

9. A method as claimed in claim 8 further comprising the step of making an electrical connection between the membrane electrode of the transducer and a circuit component and the step of making an electrical connection between the back-plate electrode of the transducer and a circuit component prior to deposition of the membrane layer which forms a passivation layer for the circuit components.

10. A method according to any preceding claim wherein the method comprises the step of using at last one photomask which defines both circuit component features and transducer features.

1 1. A method according to any preceding claim wherein a back-plate layer of the transducer also comprises a passivation layer for the circuit components.

12. A method according to any preceding claim comprising the steps of: forming at least one dielectric layer on the substrate; forming a cavity in the at least one dielectric layer in the first area; filling the cavity with sacrificial material; forming a membrane layer having a membrane electrode over the cavity; and forming a sacrificial structure over the cavity.

13. A method as claimed in claim 12 wherein the step of filling the cavity with sacrificial material preferably comprises planarising the surface prior to formation of the membrane layer.

14. A method as claimed in claim 13 wherein the step of planarising the surface comprises a chemical mechanical polishing (CMP) step.

15. A method as claimed in any of claims 12 to 14 wherein the membrane layer is deposited as a planar layer.

16. A method as claimed in any of claims 12 to 15 wherein the step of deposition said plurality of common layers comprising the step of depositing at least one additional dielectric layer over the whole substrate so as to form a first back-plate layer in the first area and a dielectric circuit component layer in the second area.

17. A method as claimed in claim 16 wherein the step of deposition said plurality of common layers further comprises the step of forming a metal layer after said at least one additional dielectric layer so as to form the back-plate electrode in the first area and a circuit component layer in the second area.

18. A method as claimed in claim 17 wherein said metal layer which form the back- plate electrode also forms an interconnect between the back-plate electrode and a circuit component.

19. A method as claimed in claim 17 or claim 18 wherein said metal layer which forms the back-plate electrode also forms an electrical connection between the membrane electrode and a circuit component.

20. A method as claimed in any of claims 17 to 19 further comprising deposition of a further dielectric layer which forms part of the circuit layers and also forms a further back-plate layer of the transducer.

21. A method as claimed in any of claims 17 to 20 comprising deposition of at least one additional back-plate layer.

22. A method as claimed in claim 21 wherein said additional back-plate layer comprises a different material to the dielectric materials of the circuit component layers.

23. A method as claimed in claim 21 or claim 22 wherein said additional back-plate layer forms at least part of a passivation layer for the circuit components.

24. A method as claimed in any preceding claim wherein the back-plate of the transducer is formed first before the membrane of said transducer.

25. A method as claimed in claim 24 comprising the steps of depositing a plurality of dielectric layers on the substrate and depositing a plurality of metal layers on the substrate to form a plurality of circuit components in the second area and to form a back-plate in the first area.

26. A method as claimed in claim 25 further comprising the step of forming a back- plate electrode on the uppermost dielectric layer in the first area.

27. A method as claimed in claim 26 further comprising the steps of forming a first sacrificial structure on the back-plate electrode and subsequently forming a membrane layer and membrane electrode on the surface.

28. A method as claimed in claim 27 wherein the membrane layer comprises a passivation layer for the circuit components.

29. A method as claimed in claim 27 or claim 28 further comprising the step of forming a second sacrificial structure on the membrane and subsequently forming a strengthening layer on the surface.

30. A method as claimed in claim 29 wherein the strengthening layer is subsequently removed from above the membrane but retained in the area of the membrane side walls.

31. A method as claimed in claim 29 or claim 30 wherein the strengthening layer comprises at least part of a passivation layer for the circuitry components.

32. A method according to any of claims 29 to 31 further comprising the steps of forming electrical connections between the membrane electrode and a circuit component and forming electrical connections between the back-plate electrode and a circuit component prior to formation of the strengthening layer.

33. A method as claimed in any of claims 27 to 32 wherein the first sacrificial structure comprises a cavity in a spacing layer and wherein the method comprises the steps of: forming a spacing layer on the substrate in the first area; forming a cavity may in the spacing layer; and filling the cavity with sacrificial material to form the first sacrificial structure.

34. A method as claimed in claim 33 further comprising the step of planarising the spacing layer and sacrificial material in the cavity.

35. A method as claimed in claims 33 or 34 wherein the membrane layer is planar.

36. A method as claimed in any of claims 33 to 35 wherein the spacing layer comprises the same material as the membrane layer.

37. A method as claimed in any of claims 24 to 35 comprising the step of forming a through-hole through the substrate to provide an acoustic port.

38. A method as claimed in claim 24 wherein sidewall supports for the membrane layer are provided by dielectric layers which form part of the circuit layers.

39. A method as claimed in claim 38 wherein the back-plate electrode of the transducer is formed from a metal layer that also forms a metal layer of the circuit components.

40. A method as claimed in claim 38 or claim 39 comprising the steps of: forming at least one dielectric layer on the substrate to form a dielectric circuit component layer in the second area and also to form a back-plate layer in the first area; forming a back-plate electrode on the back-plate; depositing at least one further dielectric layer to form a dielectric layer of a circuit component; forming a cavity in the at least one further dielectric layer in the first area; filling the cavity with sacrificial material, forming a membrane layer having a membrane electrode over the cavity; and forming a sacrificial structure over the membrane layer over the cavity.

41. A method as claimed in claim 40 where the step of filling the cavity with sacrificial material comprises planarising the surface prior to formation of the membrane layer.

42. A method as claimed in claim 41 wherein the membrane layer is planar.

43. A method as claimed in claim 41 or claim 42 further comprising the step of depositing at least one additional dielectric layer comprising a dielectric layer of the circuit components.

44. A method as claimed in claim 43 further comprising the step of depositing at least one additional metal layer which comprises a metal layer of at least one circuit component.

45. A method according to claim 44 where the at least one additional metal layer forms an electrical connection between the membrane electrode and a circuit component.

46. A method according to any of claims 43 to 45 further comprising the step of depositing a strengthening layer on top of the substrate.

47. A method according to claim 46 wherein the strengthening layer forms at least part of a passivation layer for the circuit components.

48. A method as claimed in any of claims 40 to 47 formation of a through hole through the substrate in the first area to provide a sound port.

49. A method as claimed in any previous claims wherein the arrangement of at least one metal layer of said common layers is such so as to control the mechanical properties of the back-plate layers.

50. A method as claimed in claim 49 wherein at least one metal layer of said common layers is formed in the transducer back-plate as a plurality of metal islands.

51. A method as claimed in claim 49 or claim 50 wherein said common layers comprise, a plurality of metal layers in the first area which are electrically connected to one another.

52. A method as claimed in any of claims 49 to 51 wherein at least one metal layer of said common layers is arranged to be connected to ground in use.

53. A method according to any preceding claim further comprising a wafer scale packaging step.

54. A method according to any previous claim wherein at least one membrane layer comprises silicon nitride.

55. A method according to any preceding claim wherein the sacrificial material of the sacrificial structure comprises polyimide.

56. A method according to any preceding claim wherein at least one back-plate layer comprises silicon nitride.

57 A method according to any of claims 29 to 31 or claims 46 to 47 wherein the strengthening layer comprises silicon nitride.

58. A method according to any preceding claim wherein the membrane electrode and/or back-plate electrode comprise aluminium.

59. A method as claimed in any preceding claims wherein the circuit layers comprise at least one aluminium layer.

60. A method as claimed in any preceding claim wherein the circuit layers comprise at least one intermetal dielectric (IMD) layer which comprises a plasma enhanced tetra-ethyl-ortho-silicate layer.

61. A method as claimed in any preceding claim wherein the circuit layers comprise at least one interlayer dielectric (ILD) layer which comprise Borophosphosilicate Glass (BPSG).

62. A method as claimed in any preceding claim comprising the step of fabricating dummy structures in the areas of the substrate which are not in the first or second areas.

63. A method as claimed in claim 62 wherein the step of forming of forming at east one of the circuit layers comprises forming dummy structures in said layer in the areas of the substrate which are not in the first or second areas.

64. A method as claimed in claim 62 or claim 63 wherein, for each metal layer deposited during fabrication of the device, the metal layer in the area outside the first and second areas is patterned into a plurality of dummy metal structures.

65. A method as claimed in claim to 64 wherein the dummy metal structures have a size and spacing so as to provide the required density of metal across the substrate.

66. A method as claimed in any of claims 62 to 65 wherein the dummy structures comprise a regular repeating array of isolated dummy structures.

67. A method as claimed in any of claims 64 to 66 wherein each metal layer has the same repeating regular array of isolated dummy structures.

68. A method as claimed in claim 67 wherein the dummy structures of one layer overlap with the dummy structures of an adjacent layer.

69. A method as claimed in any of claims 62 to 68 wherein the method comprises forming at least some connections between dummy structures in adjacent layers.

70. A method as claimed in any of claims 62 to 69 wherein at least one layer of dummy structures is arranged to be connected to ground in use.

71. A method as claimed in any preceding claim further comprising providing at least one sealing region on the substrate.

72. A method as claimed in claim 71 wherein a continuous sealing region is provided around the periphery of the substrate.

73. A method as claimed in claim 71 or claim 72 further comprising forming at least one sealing region disposed between the first area and the second area.

74. A method as claimed in claim 73 wherein the sealing region between the first and second areas comprises a region around the periphery of the second region.

75. A method as claimed in claim 73 wherein the sealing region between the first area and the second area is formed around the periphery of the first area.

76. A method as claimed in any of claims 71 to 75 wherein the sealing region comprises at least one conductive layer and means for connecting the conductive layer to a cap.

77. A method as claimed in any of claims 71 to 76 wherein the sealing region comprises an area which protrudes above the level of the surrounding material.

78. A method as claimed in any preceding claim wherein the method comprises forming a plurality of MEMS transducers on the substrate.

79. An apparatus comprising a capacitive MEMS transducer and at least one circuit component on the same substrate wherein the apparatus is fabricated using the method of any of claims 1 to 78.

80. An apparatus comprising a capacitive MEMS transducer and at least one circuit component on the same substrate wherein the MEMS transducer comprises a moveable membrane having a membrane electrode and a back-plate having a back-plate electrode and the at least one circuit component comprises a plurality of CMOS layers and wherein a plurality of common layers form at least some of the CMOS layers and at least part of the back-plate of the transducer wherein the common layers comprise at least one metal layer and at least one dielectric layer.

81. An apparatus as claimed in claim 80 wherein the transducer is arranged with the membrane layer uppermost.

82. An apparatus as claimed in any of claims 80 to 81 wherein the membrane comprises a planar layer.

83. An apparatus as claimed in claim 82 wherein the planar membrane is arranged over a cavity formed in at least one of the CMOS layers.

84. An apparatus as claimed in claim 82 wherein the planar membrane is arranged over a cavity formed in a spacer layer.

85. An apparatus as claimed in any of claims 80 to 84 comprising an acoustic port through the substrate under the transducer.

86. An apparatus as claimed in any of claims 80 to 85 wherein at least one metal layer of said common layers is arranged in the back-plate of the transducer to provide predetermined mechanical properties.

87. An apparatus having a capacitive MEMS transducer with at least one circuit component integrated on the same substrate wherein the transducer has an acoustic port formed in the substrate under the transducer.

88. An apparatus as claimed in claim 87 wherein the transducer comprises a moveable membrane having a membrane electrode and a back-plate having a back-plate electrode wherein the moveable membrane is above the back-plate.

89. An apparatus having a MEMS capacitive transducer and at least one circuit component, the at least one circuit comprising a plurality of dielectric layers and a plurality of metal layers wherein the transducer back-plate comprises at least one of said dielectric layers and at least one of said metal layers and wherein the arrangement of the metal layers in the back-plate is chosen so as to provide the desired mechanical properties.

90. An apparatus comprising a MEMS capacitive transducer in a first area on a substrate and at least one circuit component in a second area on a substrate further comprising a plurality of dummy structures in areas of the substrate outside the first and second areas.

91. An apparatus as claimed in any of claims 80 to 90 comprising a plurality of MEMS transducers on the substrate

92. An apparatus as claimed in any of claims 80 to 91 wherein the MEMS capacitive transducer comprises a microphone.

93. An apparatus as claimed in any of claims 80 to 92 comprising a plurality of circuit components forming audio circuitry.

94. An apparatus as claimed in any of claims 80 to 93 wherein the apparatus forms part of an ultrasound imagers, a sonar device, a mobile phone, PDAs, an audio or video player or a laptop.

95. A method of forming a back-plate of a MEMS transducer formed on a substrate comprising the step of using at least one dielectric layer and at least one metal layer, which is deposited on the substrate to form circuitry, to form at least part of said back-plate and arranging the at least one metal layer within the back-plate so as to provide the desired mechanical properties of the back-plate. A method of forming a MEMS transducer having a moveable membrane comprising the steps of: forming a cavity in a first layer; filling said cavity with sacrificial material; and forming a membrane having a membrane electrode over said cavity such that the membrane is planar.