WO2010102264A3 - Statistical formal activity analysis with consideration of temporal and spatial correlations - Google Patents

Statistical formal activity analysis with consideration of temporal and spatial correlations Download PDF

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Publication number
WO2010102264A3
WO2010102264A3 PCT/US2010/026448 US2010026448W WO2010102264A3 WO 2010102264 A3 WO2010102264 A3 WO 2010102264A3 US 2010026448 W US2010026448 W US 2010026448W WO 2010102264 A3 WO2010102264 A3 WO 2010102264A3
Authority
WO
WIPO (PCT)
Prior art keywords
temporal
activity analysis
consideration
spatial correlations
sequential circuit
Prior art date
Application number
PCT/US2010/026448
Other languages
French (fr)
Other versions
WO2010102264A2 (en
Inventor
Zhenyu Gu
Kenneth S. Mcelvain
Original Assignee
Synopsys, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys, Inc. filed Critical Synopsys, Inc.
Priority to CN2010800198826A priority Critical patent/CN102439468A/en
Priority to EP10749422.1A priority patent/EP2414852A4/en
Publication of WO2010102264A2 publication Critical patent/WO2010102264A2/en
Publication of WO2010102264A3 publication Critical patent/WO2010102264A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3323Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00Details relating to CAD techniques
    • G06F2111/08Probabilistic or stochastic CAD
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06Power analysis or power optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.
PCT/US2010/026448 2009-03-06 2010-03-05 Statistical formal activity analysis with consideration of temporal and spatial correlations WO2010102264A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2010800198826A CN102439468A (en) 2009-03-06 2010-03-05 Statistical formal activity analysis with consideration of temporal and spatial correlations
EP10749422.1A EP2414852A4 (en) 2009-03-06 2010-03-05 Statistical formal activity analysis with consideration of temporal and spatial correlations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/399,795 2009-03-06
US12/399,795 US8161434B2 (en) 2009-03-06 2009-03-06 Statistical formal activity analysis with consideration of temporal and spatial correlations

Publications (2)

Publication Number Publication Date
WO2010102264A2 WO2010102264A2 (en) 2010-09-10
WO2010102264A3 true WO2010102264A3 (en) 2011-01-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/026448 WO2010102264A2 (en) 2009-03-06 2010-03-05 Statistical formal activity analysis with consideration of temporal and spatial correlations

Country Status (5)

Country Link
US (3) US8161434B2 (en)
EP (1) EP2414852A4 (en)
CN (1) CN102439468A (en)
TW (1) TWI484202B (en)
WO (1) WO2010102264A2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8042075B2 (en) * 2009-03-25 2011-10-18 International Business Machines Corporation Method, system and application for sequential cofactor-based analysis of netlists
US8707244B1 (en) * 2010-08-20 2014-04-22 Altera Corporation Methods and systems for performing signal activity extraction
US8335783B2 (en) 2010-12-28 2012-12-18 Teradata Us, Inc. Collection of statistics for spatial columns or R-tree indexes
US8504974B1 (en) * 2011-09-14 2013-08-06 Xilinx, Inc. Analysis of circuit designs
US20130096901A1 (en) * 2011-10-12 2013-04-18 International Business Machines Corporation Verifying Simulation Design Modifications
US8656326B1 (en) * 2013-02-13 2014-02-18 Atrenta, Inc. Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
US8966416B2 (en) * 2013-03-07 2015-02-24 Cadence Design Systems, Inc. Finite-state machine encoding during design synthesis
TW201514725A (en) * 2013-10-09 2015-04-16 Chi Mei Foundation Hospital Method and system for automatically determining statistical analysis approach
GB2518909B (en) * 2013-12-16 2015-10-28 Imagination Tech Ltd Encoder adaptation
US20150260768A1 (en) * 2014-03-13 2015-09-17 Kabushiki Kaisha Toshiba Detection method of algorithm in integrated circuit
US10402175B2 (en) 2015-06-01 2019-09-03 Assurant Design Automation LLC Parsing source code into a linear array
US20160350668A1 (en) * 2015-06-01 2016-12-01 Assurant Design Automation LLC Risk evaluation
US11610038B2 (en) * 2015-06-01 2023-03-21 Assurant Design Automation LLC Risk evaluation
US10747919B2 (en) 2015-06-01 2020-08-18 Assurant Design Automation LLC Generating path execution times
US10997334B2 (en) 2015-06-01 2021-05-04 Assurant Design Automation LLC Implementing a logic design
US10678980B2 (en) 2015-06-01 2020-06-09 Assurant Design Automation LLC Combination map based composite design
US10997335B2 (en) 2015-06-01 2021-05-04 Assurant Design Automation LLC Exceptional logic element management
CN105652182B (en) * 2015-12-28 2018-10-02 北京航天测控技术有限公司 A kind of board failure positioning system and method based on circuit network and graph search
CN107153682A (en) * 2017-04-23 2017-09-12 潘小胜 A kind of method of Auto-matching Explosion-Proof Tank storage information
TWI681311B (en) * 2018-04-27 2020-01-01 瑞昱半導體股份有限公司 Circuit design system and checking method
US10909283B1 (en) * 2018-11-21 2021-02-02 Cadence Design Systems, Inc. Hardware assisted weighted toggle count
CN117454813A (en) * 2023-12-22 2024-01-26 杭州行芯科技有限公司 Method and device for calculating flip probability information of circuit and computer equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5966523A (en) * 1996-01-12 1999-10-12 Kabushiki Kaisha Toshiba Method of estimating power consumption of semiconductor integrated circuit
US7076712B2 (en) * 2003-05-22 2006-07-11 Fujitsu Limited Generating a test sequence using a satisfiability technique
US7284218B1 (en) * 2005-03-18 2007-10-16 Calypto Design Systems, Inc. Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1300265C (en) * 1987-06-22 1992-05-05 William Curtis Newman Block diagram simulator
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5752000A (en) * 1994-08-02 1998-05-12 Cadence Design Systems, Inc. System and method for simulating discrete functions using ordered decision arrays
US5774370A (en) * 1995-09-18 1998-06-30 Vlsi Technology, Inc. Method of extracting implicit sequential behavior from hardware description languages
US6195786B1 (en) * 1997-12-23 2001-02-27 Nec Usa, Inc. Constrained register sharing technique for low power VLSI design
US6363520B1 (en) * 1998-06-16 2002-03-26 Logicvision, Inc. Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification
US6816825B1 (en) * 1999-06-18 2004-11-09 Nec Corporation Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
US6493853B1 (en) * 1999-07-15 2002-12-10 Texas Instruments Incorporated Cell-based noise characterization and evaluation
US6408428B1 (en) * 1999-08-20 2002-06-18 Hewlett-Packard Company Automated design of processor systems using feedback from internal measurements of candidate systems
JP3836276B2 (en) * 1999-09-17 2006-10-25 株式会社東芝 Method of evaluating integrated circuit noise and power
US6477685B1 (en) * 1999-09-22 2002-11-05 Texas Instruments Incorporated Method and apparatus for yield and failure analysis in the manufacturing of semiconductors
US6745160B1 (en) * 1999-10-08 2004-06-01 Nec Corporation Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US6578176B1 (en) * 2000-05-12 2003-06-10 Synopsys, Inc. Method and system for genetic algorithm based power optimization for integrated circuit designs
US6701501B2 (en) * 2000-10-16 2004-03-02 Simon Joshua Waters Structured algorithmic programming language approach to system design
US6687883B2 (en) * 2000-12-28 2004-02-03 International Business Machines Corporation System and method for inserting leakage reduction control in logic circuits
US7000213B2 (en) * 2001-01-26 2006-02-14 Northwestern University Method and apparatus for automatically generating hardware from algorithms described in MATLAB
US20020144092A1 (en) * 2001-01-31 2002-10-03 Siroyan Limited. Handling of loops in processors
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits
US7193504B2 (en) 2001-10-09 2007-03-20 Alien Technology Corporation Methods and apparatuses for identification
US6895545B2 (en) * 2002-01-28 2005-05-17 Broadcom Corporation System and method for generating cyclic codes for error control in digital communications
US6687882B1 (en) * 2002-01-31 2004-02-03 Synplicity, Inc. Methods and apparatuses for non-equivalence checking of circuits with subspace
US7134100B2 (en) * 2002-07-29 2006-11-07 Nec Usa, Inc. Method and apparatus for efficient register-transfer level (RTL) power estimation
US7224185B2 (en) * 2002-08-05 2007-05-29 John Campbell System of finite state machines
US6952816B2 (en) * 2002-10-07 2005-10-04 Hewlett-Packard Development Company, L.P. Methods and apparatus for digital circuit design generation
US7565631B1 (en) * 2004-07-02 2009-07-21 Northwestern University Method and system for translating software binaries and assembly code onto hardware
US7278120B2 (en) * 2004-07-23 2007-10-02 Synplicity, Inc. Methods and apparatuses for transient analyses of circuits
US20060259885A1 (en) * 2004-08-09 2006-11-16 Mortensen Michael P System and method for analyzing a circuit
US20080092092A1 (en) * 2004-10-04 2008-04-17 Damian Jude Dalton Method and Processor for Power Analysis in Digital Circuits
US7366997B1 (en) 2005-01-11 2008-04-29 Synplicity, Inc. Methods and apparatuses for thermal analysis based circuit design
US7882464B1 (en) * 2005-02-14 2011-02-01 Cadence Design Systems, Inc. Method and system for power distribution analysis
US7350166B2 (en) * 2005-04-14 2008-03-25 International Business Machines Corporation Method and system for reversing the effects of sequential reparameterization on traces
US7596770B1 (en) * 2005-06-02 2009-09-29 Cadence Design Systems, Inc. Temporal decomposition for design and verification
US7222039B2 (en) 2005-06-10 2007-05-22 Azuro (Uk) Limited Estimation of average-case activity for digital state machines
CN1710567A (en) * 2005-07-07 2005-12-21 复旦大学 Sequential circuit equivalent testing and verifying
US7434184B2 (en) * 2005-08-08 2008-10-07 Zhe Li Method for detecting flaws in a functional verification plan
US7469394B1 (en) * 2005-12-09 2008-12-23 Altera Corporation Timing variation aware compilation
TWI337715B (en) * 2006-11-08 2011-02-21 Inst Information Industry Method and system for complex event processing
US7698088B2 (en) * 2006-11-15 2010-04-13 Silicon Image, Inc. Interface test circuitry and methods
US7814448B2 (en) * 2007-04-09 2010-10-12 International Business Machines Corporation Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits
EP2006784A1 (en) * 2007-06-22 2008-12-24 Interuniversitair Microelektronica Centrum vzw Methods for characterization of electronic circuits under process variability effects
US7689957B2 (en) * 2007-09-10 2010-03-30 Synopsys, Inc. Identifying and improving robust designs using statistical timing analysis
EP2218024A1 (en) * 2007-10-03 2010-08-18 University College Dublin System level power evaluation method
US7904850B2 (en) * 2007-11-30 2011-03-08 Cebatech System and method for converting software to a register transfer (RTL) design
US8245165B1 (en) * 2008-04-11 2012-08-14 Cadence Design Systems, Inc. Methods and apparatus for waveform based variational static timing analysis
WO2009128115A1 (en) * 2008-04-15 2009-10-22 日東電工株式会社 Optical film layered roll and method and device for manufacturing the same
US7890903B2 (en) * 2008-05-29 2011-02-15 International Business Machines Corporation Method and system for formal verification of an electronic circuit design
US8141024B2 (en) * 2008-09-04 2012-03-20 Synopsys, Inc. Temporally-assisted resource sharing in electronic systems
US8694570B2 (en) * 2009-01-28 2014-04-08 Arun Mohanlal Patel Method and apparatus for evaluation of multi-dimensional discrete fourier transforms
US20120290278A1 (en) * 2011-03-14 2012-11-15 New York University Process, computer-accessible medium and system for obtaining diagnosis, prognosis, risk evaluation, therapeutic and/or preventive control based on cancer hallmark automata
JP5893954B2 (en) * 2012-02-24 2016-03-23 ルネサスエレクトロニクス株式会社 Equivalence verification method, equivalence verification program, and equivalence verification device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5966523A (en) * 1996-01-12 1999-10-12 Kabushiki Kaisha Toshiba Method of estimating power consumption of semiconductor integrated circuit
US7076712B2 (en) * 2003-05-22 2006-07-11 Fujitsu Limited Generating a test sequence using a satisfiability technique
US7284218B1 (en) * 2005-03-18 2007-10-16 Calypto Design Systems, Inc. Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design

Also Published As

Publication number Publication date
US20120210291A1 (en) 2012-08-16
US9195790B2 (en) 2015-11-24
TW201100829A (en) 2011-01-01
WO2010102264A2 (en) 2010-09-10
EP2414852A4 (en) 2014-07-30
US8161434B2 (en) 2012-04-17
US8656327B2 (en) 2014-02-18
US20100229132A1 (en) 2010-09-09
US20140165024A1 (en) 2014-06-12
CN102439468A (en) 2012-05-02
EP2414852A2 (en) 2012-02-08
TWI484202B (en) 2015-05-11

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