WO2010117618A3 - Debug signaling in a multiple processor data processing system - Google Patents
Debug signaling in a multiple processor data processing system Download PDFInfo
- Publication number
- WO2010117618A3 WO2010117618A3 PCT/US2010/028300 US2010028300W WO2010117618A3 WO 2010117618 A3 WO2010117618 A3 WO 2010117618A3 US 2010028300 W US2010028300 W US 2010028300W WO 2010117618 A3 WO2010117618 A3 WO 2010117618A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- debug
- processor
- synced
- clock
- request signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3632—Software debugging of specific synchronisation aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Debugging And Monitoring (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012504697A JP5459807B2 (en) | 2009-04-08 | 2010-03-23 | Debug signaling in multiprocessor data processing systems |
CN2010800155110A CN102365624B (en) | 2009-04-08 | 2010-03-23 | Multi-processor data processing system and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/420,521 | 2009-04-08 | ||
US12/420,521 US8275977B2 (en) | 2009-04-08 | 2009-04-08 | Debug signaling in a multiple processor data processing system |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010117618A2 WO2010117618A2 (en) | 2010-10-14 |
WO2010117618A3 true WO2010117618A3 (en) | 2011-01-13 |
Family
ID=42935272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2010/028300 WO2010117618A2 (en) | 2009-04-08 | 2010-03-23 | Debug signaling in a multiple processor data processing system |
Country Status (5)
Country | Link |
---|---|
US (1) | US8275977B2 (en) |
JP (1) | JP5459807B2 (en) |
CN (1) | CN102365624B (en) |
TW (1) | TWI483181B (en) |
WO (1) | WO2010117618A2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5400443B2 (en) | 2009-03-25 | 2014-01-29 | スパンション エルエルシー | Integrated circuit, debug circuit, and debug command control method |
TW201145016A (en) * | 2010-06-15 | 2011-12-16 | Nat Univ Chung Cheng | Non-intrusive debugging framework for parallel software based on super multi-core framework |
GB2483907A (en) * | 2010-09-24 | 2012-03-28 | Advanced Risc Mach Ltd | Privilege level switching for data processing circuitry when in a debug mode |
US8700955B2 (en) | 2011-09-22 | 2014-04-15 | Freescale Semiconductor, Inc. | Multi-processor data processing system having synchronized exit from debug mode and method therefor |
US9110142B2 (en) * | 2011-09-30 | 2015-08-18 | Freescale Semiconductor, Inc. | Methods and apparatus for testing multiple-IC devices |
US8819485B2 (en) * | 2012-03-12 | 2014-08-26 | Infineon Technologies Ag | Method and system for fault containment |
JP6360387B2 (en) | 2014-08-19 | 2018-07-18 | ルネサスエレクトロニクス株式会社 | Processor system, engine control system, and control method |
CN104484258A (en) * | 2014-12-05 | 2015-04-01 | 中国航空工业集团公司第六三一研究所 | Multi-processor synchronous debugging support circuit |
CN106776186B (en) * | 2016-12-29 | 2020-04-07 | 湖南国科微电子股份有限公司 | Method and system for debugging CPU running state under multi-CPU architecture |
CN106933721B (en) * | 2017-02-15 | 2020-06-26 | 北京四方继保自动化股份有限公司 | Remote monitoring method for serial port of in-situ protection device |
US10606764B1 (en) * | 2017-10-02 | 2020-03-31 | Northrop Grumman Systems Corporation | Fault-tolerant embedded root of trust using lockstep processor cores on an FPGA |
JP6981920B2 (en) * | 2018-05-25 | 2021-12-17 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and debugging methods |
JP7073285B2 (en) * | 2019-01-09 | 2022-05-23 | ルネサスエレクトロニクス株式会社 | Operation verification program, operation synchronization method and abnormality detection device |
JP7378254B2 (en) * | 2019-09-19 | 2023-11-13 | キヤノン株式会社 | multiprocessor device |
CN111240834B (en) * | 2020-01-02 | 2024-02-02 | 北京字节跳动网络技术有限公司 | Task execution method, device, electronic equipment and storage medium |
US11892505B1 (en) * | 2022-09-15 | 2024-02-06 | Stmicroelectronics International N.V. | Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus |
Citations (4)
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US5452437A (en) * | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
US6826717B1 (en) * | 2000-06-12 | 2004-11-30 | Altera Corporation | Synchronization of hardware and software debuggers |
US20070130492A1 (en) * | 2005-12-02 | 2007-06-07 | Piyush Jamkhandi | Testable design methodology for clock domain crossing |
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US5313618A (en) * | 1992-09-03 | 1994-05-17 | Metalink Corp. | Shared bus in-circuit emulator system and method |
US5537655A (en) * | 1992-09-28 | 1996-07-16 | The Boeing Company | Synchronized fault tolerant reset |
JPH07261814A (en) * | 1994-03-16 | 1995-10-13 | Yaskawa Electric Corp | Interruption synchronizing method for dual system of pc |
JP3175757B2 (en) * | 1996-08-13 | 2001-06-11 | 日本電気株式会社 | Debug system |
SE9801678L (en) * | 1998-05-13 | 1999-11-14 | Axis Ab | Computer chip and computer device with improved debugging ability |
US6321329B1 (en) * | 1999-05-19 | 2001-11-20 | Arm Limited | Executing debug instructions |
US6343358B1 (en) * | 1999-05-19 | 2002-01-29 | Arm Limited | Executing multiple debug instructions |
US7188063B1 (en) | 2000-10-26 | 2007-03-06 | Cypress Semiconductor Corporation | Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation |
US7206733B1 (en) | 2000-10-26 | 2007-04-17 | Cypress Semiconductor Corporation | Host to FPGA interface in an in-circuit emulation system |
US6675334B2 (en) * | 2001-05-31 | 2004-01-06 | Texas Instruments Incorporated | Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for hardware emulation |
US7774190B1 (en) * | 2001-11-19 | 2010-08-10 | Cypress Semiconductor Corporation | Sleep and stall in an in-circuit emulation system |
US6993674B2 (en) * | 2001-12-27 | 2006-01-31 | Pacific Design, Inc. | System LSI architecture and method for controlling the clock of a data processing system through the use of instructions |
EP1398700A1 (en) * | 2002-09-12 | 2004-03-17 | Siemens Aktiengesellschaft | Method and circuit device for synchronizing redundant processing units |
US7805638B2 (en) * | 2003-06-18 | 2010-09-28 | Nethra Imaging, Inc. | Multi-frequency debug network for a multiprocessor array |
US20050039074A1 (en) * | 2003-07-09 | 2005-02-17 | Tremblay Glenn A. | Fault resilient/fault tolerant computing |
US7219265B2 (en) * | 2003-12-29 | 2007-05-15 | Agere Systems Inc. | System and method for debugging system-on-chips |
US7055117B2 (en) * | 2003-12-29 | 2006-05-30 | Agere Systems, Inc. | System and method for debugging system-on-chips using single or n-cycle stepping |
US7237144B2 (en) * | 2004-04-06 | 2007-06-26 | Hewlett-Packard Development Company, L.P. | Off-chip lockstep checking |
DE102004038590A1 (en) | 2004-08-06 | 2006-03-16 | Robert Bosch Gmbh | Method for delaying access to data and / or commands of a dual-computer system and corresponding delay unit |
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DE102005037222A1 (en) * | 2004-10-25 | 2007-02-15 | Robert Bosch Gmbh | Mode signal evaluating method for computer system, involves generating mode signal and changes in mode signal in computer system, where changes in mode signal and mode signal are used for evaluation of signal in computer system |
CN101048757A (en) | 2004-10-25 | 2007-10-03 | 罗伯特·博世有限公司 | Method and device for switching over in a computer system having at least two execution units |
WO2006045798A1 (en) | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Method and device for distributing data from at least one data source in a multiprocessor system |
JP4154610B2 (en) * | 2004-12-21 | 2008-09-24 | 日本電気株式会社 | Fault tolerant computer and control method thereof |
US20060161818A1 (en) * | 2005-01-14 | 2006-07-20 | Ivo Tousek | On-chip hardware debug support units utilizing multiple asynchronous clocks |
US7549092B2 (en) * | 2005-09-29 | 2009-06-16 | Hynix Semiconductor, Inc. | Output controller with test unit |
TWI331278B (en) * | 2007-03-14 | 2010-10-01 | Ind Tech Res Inst | Debug method |
-
2009
- 2009-04-08 US US12/420,521 patent/US8275977B2/en active Active
-
2010
- 2010-03-23 WO PCT/US2010/028300 patent/WO2010117618A2/en active Application Filing
- 2010-03-23 JP JP2012504697A patent/JP5459807B2/en active Active
- 2010-03-23 CN CN2010800155110A patent/CN102365624B/en active Active
- 2010-04-06 TW TW099110613A patent/TWI483181B/en active
Patent Citations (4)
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US5452437A (en) * | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
US6826717B1 (en) * | 2000-06-12 | 2004-11-30 | Altera Corporation | Synchronization of hardware and software debuggers |
US20070130492A1 (en) * | 2005-12-02 | 2007-06-07 | Piyush Jamkhandi | Testable design methodology for clock domain crossing |
Non-Patent Citations (1)
Title |
---|
"Internet data, eXpressDSP Software and Development Tools (-)", 2004, Retrieved from the Internet <URL:http://focus.ti.com/lit/ml/sprue40/sprue40.pdf> * |
Also Published As
Publication number | Publication date |
---|---|
WO2010117618A2 (en) | 2010-10-14 |
JP5459807B2 (en) | 2014-04-02 |
US20100262811A1 (en) | 2010-10-14 |
US8275977B2 (en) | 2012-09-25 |
JP2012523616A (en) | 2012-10-04 |
TWI483181B (en) | 2015-05-01 |
CN102365624A (en) | 2012-02-29 |
TW201044268A (en) | 2010-12-16 |
CN102365624B (en) | 2013-10-16 |
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