WO2010133550A1

WO2010133550A1 - Method for coating a semiconductor substrate by electrodeposition

Info

Publication number: WO2010133550A1
Application number: PCT/EP2010/056738
Authority: WO
Inventors: Nadia Frederich
Original assignee: Alchimer
Priority date: 2009-05-18
Filing date: 2010-05-17
Publication date: 2010-11-25
Also published as: TW201108353A; FR2945665A1

Abstract

The invention relates to a method for treating a semiconductor substrate including the following steps: - etching step (S1 ) comprising etching the semiconductor substrate to form at least one pattern forming a cavity, particularly of the "through via" type, with respect to the surface of said semiconductor substrate; deposition step (S2) comprising deposition of an insulating dielectric layer on said surface of said semiconductor substrate; - deposition (S3) of a layer of phosphorus in situ doped polysilicon on said insulating dielectric layer; coating step (S4) comprising coating of said layer of phosphorus in situ doped polysilicon with a layer of metallic copper, wherein the coating step (S4) includes an electrodeposition using an electrodeposition solution made for growth of metallic copper on phosphorus in situ doped polysilicon.

Description

Method for Coating a Semiconductor Substrate by Electrodeposition

FIELD OF THE INVENTION The present invention relates in general to an electrodeposition composition intended for coating a surface of a substrate with copper, particularly a surface comprising an electrically resistive material.

STATE OF THE ART The invention may essentially be employed in the field of microelectronics for the metallization of through vias (also called "through silicon vias" or "through wafer vias" or "through wafer interconnects"), which are the cornerstone of the integration of electronic chips (or dies) in three dimensions (3D) or vertical integration. Contemporary electronic systems are mostly composed of a plurality of integrated circuits, or components, and each integrated circuit fulfils one or more functions. For example, a computer has at least one microprocessor and a plurality of memory circuits. Each integrated circuit usually corresponds to an electronic chip in its own package. The integrated circuits are soldered or inserted onto, for example, a printed circuit board (or PCB) which provides the connection between the integrated circuits. For the last several generations of integrated circuits, the constant need to increase the density of functionality has led to systems being designed according to the "system on chip" concept. All the components and circuit blocks necessary for implementing the set of functions of the system are then produced on the same chip, without using the support of a printed circuit. In practice, however, it is very difficult to obtain a high-performance "system on chip" because the methods of fabricating logic and memory circuits, for example, differ very substantially.

The "system on chip" approach therefore entails accepting a compromise between the performances of the various functions produced on the same chip. Furthermore, the size of such chips and their fabrication yield are reaching the limits of their economic viability.

Another approach consists in fabricating, in the same package, a module that provides the interconnection of a plurality of integrated circuits, which may in this case belong to the same semiconductor substrate or different substrates. The package thus obtained, a "multi-chip module" (or "MCM"), is thus in the form of a single component. There are various technologies for an "MCM" substrate, for example laminated, ceramic. In all cases, the "MCM" approach makes it possible to obtain a higher interconnection density and therefore better performance than a classical "PCB" approach. It is not, however, fundamentally different therefrom. Further to the bulk and weight of the package, the performances of an "MCM" remain limited by the parasitic elements associated with the length of the connections of the substrate and with the connection wires ("wire bonding") joining the substrate or the chips to the pins of the package.

By virtue of using integration in three dimensions (3D) or vertical integration, the chips are stacked and are connected together by vertical interconnects. The stack obtained has a plurality of layers or strata of active components or chips, and it constitutes an integrated circuit in three dimensions (3D integrated circuit or "3D IC"). The benefits of 3D integration relate simultaneously to:

(1 ) the improvement in performance, for example reduction of the propagation time and the power dissipated, increase in the operating speed of the system associated with accelerated communication between the functional blocks, increase in the passband of each functional block, increase in the noise immunity,

(2) the cost improvement, for example increase in the integration density, better fabrication yield owing to use of the electronic chip generation most appropriate for each functional block, increase in reliability, and

(3) the possibility of producing large-scale integrated systems by stacking heterogeneous technologies (or co-integration) i.e. employing different materials and/or different functional components.

Today, 3D integration proves to be an indispensable alternative to conventional approaches, which are reaching their limits in terms of performance, functionality diversification and production cost. After stacking, for example by adhesive bonding, the chips can be connected individually to the pins of the package by connection wires.

However, mutual interconnection of the chips with a high interconnect density can be obtained only by employing through vias. The fundamentals and advantages of 3D integration have been described for example in: A.W. Topol, D. C. La Tulipe, L. Shi, DJ.

Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A.M. Young, K. W. Guarini and M.

Leong, "Three-dimensional integrated circuits" IBM Journal Res. & Dev., vol. 50, N° 4/5,

July/September 2006, pages 491-506.

The thinning of the silicon wafers, the alignment between the layers, the bonding of the layers, the etching and the metallization of the through vias within each layer are elementary technologies necessary for the production of three-dimensional integrated circuits.

Three-dimensional integrated circuits can be produced by thinning the silicon wafer before fabricating the through vias (for example U.S. Patent Nos 7,060,624; 7,148,565). The etching and metallization of the vias may also be carried out before thinning the silicon wafer (for example U.S. Patent No 7,060,624; 7,101 ,792). In this case, the vias are etched into the silicon, then metallized to the desired depth before thinning the silicon wafer. During their metallization, the vias are therefore closed, or "blind vias". The good electrical conductivity of copper and its high resistance to the phenomenon of electromigration, that is to say little migration of copper atoms under the effect of the electrical current density, which is liable to be a major cause of a malfunction, make it in particular a material of choice for metallization of the through vias. The through vias are generally produced in a similar way to the "Damascene process" (used in the field of microelectronics to fabricate elements for interconnecting integrated circuits) according to a succession of steps involving: etching the vias into or through the silicon wafer; depositing a layer of insulating dielectric (generally consisting of silicon dioxide or nitride, for example); depositing a barrier layer or "liner" (generally consisting of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), tungsten titanate (TiW) and tungsten nitride or carbide (WCN) or combinations of these metals, for example) which is used to prevent the migration of copper; - depositing a thin layer of metallic copper, referred to as a seed layer;

- filling the vias by electrodeposition of copper; and removing the excess copper by chemical-mechanical polishing. This integration scheme allowing fabrication of through vias has a major weakness. The anisotropic etching of silicon (for example U.S. Patent No 5,501 ,893) leads most often to a profile which is barrel-shaped (also refered as "bowing"), rough, fluted or striated (also refered as "scalloping"). Thus, the sides of the layers may be partially uncovered or covered with an insufficient thickness of seed layer, then causing imperfect subsequent filling with material defects (also refered as "voids"). Furthermore, the barrier and seed layers formed on the sides of the patterns inherently have different adhesion from those deposited on the plane surface of the substrate.

These drawbacks make it very difficult to use processes for physical vapour deposition (PVD) or chemical vapour deposition () which may be used for depositing the barrier layer and the seed layer.

Under these conditions, the present invention aims at resolving the new technical problem consisting in the development of a new integration scheme that can be used for the fabrication of through vias, which makes it possible to avoid the technical difficulties arising from the anisotropic etching of silicon.

DISCLOSURE OF THE INVENTION To this end is proposed a method for treating a semiconductor substrate including the following steps: etching step (S1 ) comprising etching the semiconductor substrate to form at least one pattern forming a cavity, particularly of the "through via" type, with respect to the surface of said semiconductor substrate; deposition step (S2) comprising deposition of an insulating dielectric layer on said surface of said semiconductor substrate; deposition (S3) of a layer of phosphorus in situ doped polysilicon on said insulating dielectric layer; coating step (S4) comprising coating of said layer of phosphorus in situ doped polysilicon with a layer of metallic copper, wherein the coating step (S4) includes an electrodeposition using an electrodeposition solution made for growth of metallic copper on phosphorus in situ doped polysilicon.

Such a treatment method has the advantage of forming semi-conductor substrates with a flat profile in which defects due to etching are not present in the copper layer. Indeed, the deposition of phosphorus in situ doped polysilicon has the advantage of not being influenced by defects in the substrate surface, so that the surface of the resistive layer made up of phosphorus in situ doped polysilicon is plane, or at least without substantial defects. The subsequent electrodeposition step which is made to allow deposition of metallic copper on such a layer of phosphorus in situ doped polysilicon allows the formation of a stack with no apparent defects.

Some preferred but non-limiting variants of this treatment method, taken alone or in combination, are the following:

- the coating step (S4) includes the following successive sub-steps: o contacting sub-step (S4-0) comprising bringing said layer of phosphorus in situ doped polysilicon in contact with the electrodeposition solution, and o polarization sub-step (S4-2) comprising polarization of said layer of phosphorus in situ doped polysilicon at an electrical potential adapted for electrodeposition of metallic copper on said layer of phosphorus in situ doped polysilicon.

- the coating step (S4) further includes a holding sub-step (S4-1 ), in which, for a determinate duration, said layer of phosphorus in situ doped polysilicon is held in contact with the electrodeposition solution without electrical polarization, said holding sub-step (S4-1 ) being carried out between the contacting sub-step (S4-0) and the polarization sub-step (S4-2). the coating step (S4) further includes a hot exit sub-step (S4-3) during which said layer of phosphorus in situ doped polysilicon is separated from the electrodeposition solution while still under electrical polarization, said hot exit sub- step (S4-3) being carried out after the polarization sub-step (S4-2). the coating step (S4) includes a prior pre-wetting step comprising bringing the semiconductor substrate in contact with a liquid solution. - the contacting of the semiconductor substrate with the liquid solution is carried out by a physico-chemical technique comprising use of jets to drive the liquid solution under high pressure, and/or use of ultrasound, and/or use of vacuum.

- the method further includes an annealing step (S5) carried out after the coating step (S4), said annealing step (S5) being carried out at a temperature chosen to allow diffusion of the copper into the layer of phosphorus in situ doped polysilicon so as to form copper suicide.

- the electrodeposition solution includes, in solvent solution copper ions at a concentration of between 14 and 120 mM, and ethylenediamine, wherein the molar ratio between ethylenediamine and copper is between 1.80 and 2.03, and the pH of said electrodeposition solution is between 6.6 and 7.5.

According to another aspect, is proposed a multilayer stack comprising: a semiconductor substrate with a surface having a pattern forming at least one cavity, particularly of the "through via" type, - an insulating dielectric layer covering said surface, a layer of phosphorus in situ doped polysilicon covering said insulating dielectric layer, and a layer of metallic copper covering said layer of phosphorus in situ doped polysilicon.

According to a preferred embodiment, the copper layer in such a stack fills said at least one cavity and includes a plane external surface.

DESCRIPTION OF FIGURES Further characteristics and advantages of the invention will become evident from the following description, which is purely illustrative and not limitative and must be read in connection with the appended drawings, in which:

Figure 1 is a schematic diagram illustrating the steps of the treatment method according to an embodiment of the invention; - Figure 2 is a schematic diagram illustrating the sub-steps of the coating step in the treatment method according to an embodiment of the invention; Figure 3 represents the pulse galvanostatic protocol for growth of the seed layer; Figure 4 represents a section view on the scanning microcope of a via of dimensions 50μm x 200μm covered with a seed layer like that deposited in example 4;

Figure 5 represents a section view on the scanning microscope of the lower part of a via of dimensions 50μm x 300μm covered with a seed layer like that deposited in example 5;

Figure 6 represents a section view on the scanning microscope of the lower part of a via of dimensions 50μm x 400μm covered with a seed layer like that deposited in example 5.

DETAILED DESCRIPTION OF THE INVENTION

It has been discovered, and this constitutes the basis of the present invention, that it was possible to resolve the technical problem described above by replacing the barrier layer and seed layer deposition steps with new steps. Figure 1 is a schematic diagram illustrating the steps of the treatment method according to an embodiment of the invention.

According to a first aspect, the deposition of a barrier layer may be advantageously replaced by the deposition of a layer of phosphorus in situ doped polysilicon, or ISDP layer, whose function is to smooth out the defects due to anisotropic etching of silicon. The deposition of the seed layer is replaced by a copper growth by electrodeposition step carried out from a specific electrodeposition composition design so that the metallic copper can grow on the layer of phosphorus in situ doped polysilicon.

The electrodeposition solution used is preferably a precisely selected mixture of copper and ethylenediamine. In particular, it comprises, in solvent solution: - copper ions in a concentration of between 14 and 120 mM; ethylenediamine; the molar ratio between ethylenediamine and copper being between 1.80 and

2.03; the pH of said composition being between 6.6 and 7.5. By electrodeposition is meant a process which allows the surface of a substrate to be covered with a metallic or organometallic coating, in which substrate is electrically polarised and put into contact with a liquid containing precursors of said metallic or organometallic coating, so as to form said coating. When the substrate is electrically conductive, electrodeposition is carried out for example by passing a current between the substrate to be coated, constituting one electrode (the cathode in the case of a metallic or organometallic coating) and a second electrode (the anode) in a bath containing a source of precursors of the coating material (for example metal ions in the case of a metallic coating) and optionally various agents for improving the properties of the coating that is formed (regularity and conformity of the deposity, resistivity, etc.), optionally in the presence of a reference electrode. By international convention, the current and voltage passing through or applied to the substrate of interest, that is to the cathode, are negative. Throughout this text, when these currents and voltages are given with a positive value, it is understood that this value represents the absolute value of said current or of said voltage.

The electrodeposition compositions presented may be used for any manufacturing sequence for three-dimensional circuits (metallization before or after the silicon wafer thinning step). Such electrodeposition compositions make it possible to obtain a copper growth layer leading to an especially high substrate coverage (greater than 99%), including the most critical areas, even when the structure has a high form factor (aspect ration greater than 3:1 ; even on the order of 10 to 15:1 ) and a relatively high via volume (from 0.8 x 10¹ to 5 x 10⁶ μm³). These compositions are therefore perfectly compatible with industrial scale use.

One family of preferred compositions includes those in which copper ions are present in a concentration of between 15 and 64 mM.

Another preferred family of compositions includes those in which the molar ratio between copper ions and ethylenediamine is between 1.96 and 2.00. Though there is no limitation in principle on the nature of the solvent (as long as it adequately dissolves the active species in the solution and does not interfere with electrodeposition), it will preferably be water.

Generally, the electrodeposition composition according to the invention will include a source of copper ions, particularly Cu²⁺ cupric ions. Advantageously, the copper ion source is a copper salt such as copper sulfate, copper chloride, copper nitrate, copper acetate in particular, preferably copper sulfate, and more preferably copper sulfate pentahydrate.

According to one particular feature, the copper ions are present within the electrodeposition composition at a concentration of between 14 and 120 mM; preferably between 16 and 64 mM.

Excellent results have been obtained with compositions in which the copper ion source is present in a concentration of between 16 and 32 mM.

In the electrodeposition composition used, the molar ratio between copper ions and ethylenediamine is advantageously situated between 1.80 and 2.03, preferably between 1.96 and 2.00.

Generally, the electrodeposition composition used has a pH of between 6.6 and 7.5. This value is normally attained when the electrodeposition composition is made up only of copper ions and ethylenediamine in the proportions given previously. The pH of the composition may optionally be regulated within the aforementioned pH range by means of a buffer such as one of those described in: Handbook of Chemistry and Physics - 84th edition by David R. Lide, CRC Press, in the event that the electrodeposition composition according to the invention includes compounds other than the copper ion source and ethylenediamine.

A currently preferred electrodeposition composition includes, in aqueous solution: copper ions at a concentration of between 16 and 64 mM; ethylenediamine; the molar ratio between ethylenediamine and copper ions being between 1.96 and 2.00; the pH of said composition being between 6.6 and 7.5.

The method for coating the layer of in situ doped polysilicon with phosporus with metallic copper can be implemented by a simple electrodeposition step using the specific electrodeposition solution presented above. According to this electrodeposition method, the in situ doped polysilicon with phosporus layer formed on the semiconductor substrate is first put into contact with the specified electrodeposition solution, then the surface of said layer of in situ doped polysilicon with phosporus is polarised long enough to form said copper coating. Prior to the electrodeposition process, a pre-wetting for the purpose of forcing penetration of the electrodeposition solution into the "through vias" may be necessary in certain cases, as for example in the case of through vias with very high form factors. This pre-wetting may be carried out with the electrodeposition solution itself or with acidic, basic or neutral solutions, as for example deionized water. Said substrates are put into contact with said liquid solutions using various physico-chemical technique capable of forcing penetration of the liquid solutions into the through vias. These physico-chemical techniques may be jets driving the liquids under high pressure, ultrasound or the use of vacuum.

According to a preferred embodiment as illustrated in Figure 2, the step in which in situ doped polysilicon with phosporus is coated with metallic copper is implemented according to the electrodeposition process comprising: a step (S4-0/S4-1 ) called "cold entry" during which the surface of the layer of in situ doped polysilicon with phosporus to be coated is put into contact without electrical polarization with an electrodeposition bath containing the specified electrodeposition solution (S4-0), and is preferably maintained in this condition for a period of at least 1 minute (S4-1 ); a coating formation, or copper growth step (S4-2) during which said surface is polarised for a long enough time to form said coating; a step (S4-3) called "hot exit" during which said surface is separated from the electrodeposition bath while it is still electrically polarised.

In the electrodeposition method, the copper growth stage as such, by electrodeposition, is carried out for a sufficiently long time to form the desired coating. This time may be determined by a person skilled in the art, considering that the film growth is a function of the charge which is equal to the time integral of the electrical current passed through the circuit during the deposition time (Faraday's Law).

During the step of forming the coating, the surface to be coated may be polarized cathodically, either in galvanostatic mode (fixed imposed current) or in potentiostatic mode (imposed and fixed potential, optionally with respect to a reference electrode), or alternatively in pulsed (current or voltage) mode.

Generally, it has been observed that a particularly satisfactory coating may be obtained by polarization in pulsed mode, preferably so as to impose current pulses.

In general, this step may be carried out by imposing square current waves corresponding to a maximum current per unit area in a range of from 0.6 mA/cm² to 10 mA/cm², more particularly from 1 mA/cm² to 5 mA/cm², and a minimum current per unit area in a range of from 0 mA/cm² to 5 mA/cm², preferably 0 mA/cm².

More particularly, the polarization time at maximum current may be between 2^*10^"3 second and 1.6 seconds, preferably between 0.1 second and 0.8 second, for example of the order of 0.35 second, while the polarization time at minimum current may be between

2^*10^"3 second and 1.6 seconds, preferably between 0.1 second and 0.8 second, for example of the order of 0.25 second.

The number of cycles to be carried out during the step depends on the desired thickness of the coating. This embodiment of the invention has made it possible to produce copper seed layers having a thickness of between 50 nm and 1 μm on highly resistive substrates of structures of the "through via" type, the "sheet resistance" of which may be as much as 1000 ohms/square, or even several megaohms/square.

Following deposition of the copper layer, annealing is preferably carried out to improve adhesion between the copper layer and the doped polysilicon layer. This annealing is carried out at a temperature allowing diffusion of the copper into the silicon to form copper suicide. This temperature, as described in numerous works on metallurgy, must be on the order of 550⁰C.

The fabrication scheme for stacks with "through vias" arising from the present invention is therefore generally divided into a series of steps comprising: - etching (S1 ) the vias into or through the silicon wafer; deposition (S2) of an insulating dielectric layer (generally made up of silicon dioxide or nitride, for example); deposition (S3) of a layer of phosphorus in situ doped polysilicon which smooths out the defects arising from etching the vias into or through the silicon wafer; deposition (S4) of a thin layer of metallic copper, called a "seed layer" by an electrodeposition process, and optionally filling in the vias by this same copper electrodeposition process; and removing the excess copper by chemical-mechanical polishing.

According to a second aspect, the present invention is intended for use in fabricating a structure of the "through via" type in the fabrication of interconnects for integrated circuits.

The dimensions of these "through via" type structures have high form factors (aspect ratio greater than 3:1 , even on the order of 10 to 15:1 ) and a relatively high via volume (0.8^*10¹ μm³ to 5^*10⁶ μm³). These compositions are therefore perfectly compatible with industrial scale use. This fabrication method is particularly useful for the fabrication of through vias covered with an insulating dielectric layer having a thickness which can be on the order of 10 nm to 10 μm, preferably from 200 nm to 2 μm, for example on the order of 1.5 μm, with a layer of phosphorus in situ doped polysilicon having a thickness which can be on the order of 10 nm to 10 μm, preferably from 200 nm to 2 μm, for example on the order of 1.5 μm, and with a copper seed layer having a thickness which can be on the order of 50 nm to 2 μm, preferably from 200 nm to 1.5 μm, for example on the order of 300 nm.

The present invention will now be illustrated by the following nonlimiting examples, in which the series of steps according to the invention is used to fabricate through vias coated with an insulating dielectric layer, with a layer of phosphorus in situ doped polysilicon and with a copper seed layer.

These examples apply particularly to the fabrication of copper interconnect structures for integrated circuits.

EXAMPLE 1: Preparation of a copper seed layer on a layer of ISDP using an electrodeposition composition based on a mixture of copper and ethylenediamine..

A. Material and equipment

A1. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm in thickness. This wafer is coated with a layer of silicon dioxide having a thickness of 1.6 μm, itself covered with a coating of phosphorus in situ doped polysilicon (ISDP) 1.5 μm in thickness. A2. Electrodeposition solution:

The electrodeposition solution used in this example is an aqueous solution containing 8.4 mL/L (or 128 mM) of ethylenediamine and 16 g/L (or 64 mM) of CuSO₄ (H₂O)₅, giving a pH of 7.2. A3. Equipment:

In this example, electrolytic deposition equipment representative of that used in the microelectronics industry was used, capable of processing wafers 150 mm in diameter.

This equipment has an electrochemical deposition cell, in which deposition of the seed layer is carrier out, and a rinsing/drying station used after deposition. The electrolytic deposition cell includes a copper anode, the silicon wafer coated with a layer of ISDP constituting the cathode of this cell.

This cell furthermore has a stabilized electrical power supply making it possible to deliver up to 120 V and 15 A and a device, physically isolated from the solution by a sealing gasket, for making electrical contact with the cathode. This electrical contacting device is generally of an annular shape and allows the substrate to be supplied at a plurality of contact points arranged regularly on it.

The cell further comprises a device for supporting the wafer to be coated, having means for setting said wafer in rotation at a predetermined speed.

B. Experimental protocol

B1. Step 1 : "prewetting"

In this example, no prewetting of the substrate was carried out.

B2. Step 2: "cold entry"

This step can be divided into two sub-steps: B2-1. The aforementioned substrate is inserted into the electrochemical deposition cell in such a way that the face having the ISDP layer comes into contact with the electrical contacting device, which is not yet supplied with electricity.

B2-2. The assembly made up of the electrical contating device and the substrate, hereafter called "cathodic assembly," is put into contact with the electrodeposition solution by dipping. This contact, the duration of which is generally less than or equal to 5 seconds (2 seconds, for example), is carried out while the device is still not supplied with electricity. Preferably, the cathodic assembly is then kept in the electrodeposition solution, without polarization, for a period of at least 1 minute.

B3. Step 3: Formation of the copper coating The cathodic assembly is then polarized in galvano-pulsed mode and simultaneously rotated at a speed of from 20 to 100 revolutions per minute (for example 20 revolutions per minute). Figure 3 describes in detail the galvano-pulsed protocol which may be used, with a total period P of between 10 ms and 2 s (0.6 s in the example), a polarization time T_ON of between 2 ms and 1.6 s (0.24 s in the example), while imposing a current per unit area generally lying between -0.6 mA/cm² and -10 mA/cm² (-1.34 mA/cm² in the example), and a resting time without polarization of between 2 ms and 1.6 s (0.36 s in the example).

As will be understood, the duration of this step depends on the desired thickness of the seed layer. This time may be determined easily by the person skilled in the art, the growth of the film being a function of the charge passed through the circuit.

Under the aforementioned conditions, the deposition rate is about 1.6 nm per coulomb of charge passed through the circuit, which gives an electrodeposition step duration of the order of 60 minutes in order to obtain a coating having a thickness of 950 nm.

B4. Step 4: "cold exit"

This step can be divided into two sub-steps: B4-1. After the electrodeposition step, the polarization is stopped and the copper- coated cathodic assembly is withdrawn from the electrodeposition solution at zero rotation speed. The duration of this phase is around 2 seconds.

Rotation speed is then raised to 500 revolutions per minute for 10 seconds, the polarization of the cathodic assembly being cut during this latest phase. A preliminary rinse with deionized water is carried out in the cell.

B4-2. The seed-layer coated substrate is then transferred into the rinsing/drying module to undergo a rinse with deionized water.

The rinsing water is subsequently discharged, then drying is carried out while flushing with nitrogen. Rotation is then stopped to allow removal of the coated and dried substrate.

C. Results obtained

By applying the experimental protocol explained above, a copper layer with a thickness of 950 nm and 400 nm was obtained. The measurements and characterizations carried out after deposition of the seed layer are presented in examples 7 and 8.

EXAMPLE 2: Preparation of a copper seed layer on a layer of ISDP with its native silicon dioxide removed, using an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Material and equipment

A1. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm in thickness. This wafer is coated with a layer of silicon dioxide 1.6 μm thick, itself coated with a layer of phosphorus in situ doped polysilicon (ISDP) 1.5 μm thick.

In this example, a chemical treatment of the substrate has been carried out before starting the electrodeposition process. This treatment was to remove the silicon dioxide formed at the surface of the ISDP. It consists for instance in immersing the wafer in a liquid solution of NH₄F/HF in 50:1 proportion by volume, for a duration of 4 minutes.

A2. Electrodeposition solution:

The electrodeposition solution used in this example is identical to that of Example 1.

A3. Equipment:

The equipment used in this example is identical to that of Example 1.

B. Experimental protocol The experimental protocol used in this example is identical with that of Example 1.

C. Results obtained

By applying the experimental protocol explained above, a copper layer with a thickness of 950 nm was obtained. The measurements and characterizations carried out after deposition of the seed layer are presented in Examples 7 and 8.

EXAMPLE 3: Preparation of a copper seed layer on a layer of ISDP using an electrodeposition composition based on a mixture of copper and ethylenediamine, with augmentation of the deposition rate.

A. Material and equipment

A1. Substrate:

The substrate used in this example is identical to that of Example 1. A2. Electrodeposition solution:

The solution used in this example is identical to that of Example 1.

A3. Equipment:

The equipment used in this example is identical to that of Example 1.

B. Experimental protocol

B1. Step 1 : "pre-wetting"

In this example, no pre-wetting of the substrate was carried out.

B2. Step 2: "cold entry" This step is identical to that in Example 1.

B3. Step 3: Formation of the copper coating

The cathodic assembly is then polarized in galvano-pulsed mode and simultaneously rotated at a speed of 20 to 100 revolutions per minute (20 revolutions per minute, for example).

Figure 3 describes in detail the galvano-pulsed protocol which may be used, with a total period P of between 10 ms and 2 s (0.2 s in the example), a polarization time T_ON of between 2 ms and 1.6 s (0.1 s in the example), while imposing a current per unit area generally lying between -0.6 mA/cm² and -10 mA/cm² (-1.34 mA/cm² in the example), and a resting time without polarization of between 2 ms and 1.6 s (0.1 s in the example).

Under the aforementioned conditions, the deposition rate is about 2.7 nm per coulomb of charge passed through the circuit, which gives an electrodeposition step duration of the order of 29 minutes in order to obtain a coating having a thickness of 1 μm.

B4. Step 4: "cold exit"

This step is identical to that in Example 1.

C. Results obtained

By applying the experimental protocol explained above, a copper layer with a thickness of 1 μm was obtained.

The measurements and characterizations carried out after deposition of the seed layer are presented in Examples 7 and 8.

EXAMPLE 4: Preparation of a seed layer in structures of the "through via" type using an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Material and equipment

A1. Substrate:

The substrate used in this example consists of a silicon wafer with a diameter of 150 mm and a thickness of 675 μm, etched with cylindrical patterns of the "through via" type with a depth of 200 μm and a diameter of 50 μm. This wafer is covered with a silicon dioxide layer having a thickness of 1.6 μm, itself coated with a layer of phosphorus in situ doped polysilicon (ISDP) 1.5 μm thick.

A2. Electrodeposition solution: The electrodeposition solution used in this example is identical to that of Example 1.

A3. Equipment:

The equipment used in this example is identical to that of Example 1.

B. Experimental protocol B1. Step 1 : "pre-wetting"

A physico-chemical treatment is carried out before Step 2 "cold entry" for the purpose of increasing the wettability of the electrodeposition solution in the vias and removing air bubbles. It consists of immersing the wafer in an acidic or neutral solution (deionized water, for example) and in placing whole arrangement in an ultrasound tank for a time of at least 5 minutes (10 minutes, for example). This chemical treatment may vary according to the nature of the substrate and the dimensions of the through vias. The wafer can thus be removed from the solution and introduced wet into the electrodeposition cell. B2. Steps 2, 3, and 4:

These steps are identical to those in Example 1.

C. Results obtained

The measurements and characterizations carried out after deposition of the seed layer by applying the experimental protocol explained above are presented in Example 9.

EXAMPLE 5: Preparation of a seed layer in structures of the "through via" type using a composition according to the invention based on a mixture of copper and ethylenediamine.

A. Material and equipment

A1. Substrate:

The substrate used in this example consists of a silicon wafer with a diameter of 150 mm and a thickness of 675 μm, etched with cylindrical patterns of the "through via" type with a depth of 300 μm and diameter of 50 μm.

This wafer is covered with a silicon dioxide layer having a thickness of 1.6 μm, itself coated with a layer of phosphorus in situ doped polysilicon (ISDP) 1.5 μm thick.

A2. Electrodeposition solution:

A3. Equipment:

The equipment used in this example is identical to that of Example 1. B. Experimental protocol

B1. Step 1 : "pre-wetting"

A physico-chemical treatment is carried out before Step 2 "cold entry" for the purpose of increasing the wettability of the electrodeposition solution in the vias and removing air bubbles. This treatment is carried out in the rinsing/drying module also used in Step 4.

The substrate is inserted into the rinsing/drying module and rotated at a speed of 1 rpm for at least 1 minute (for example 7 minutes), then at 100 rpm for at least 1 minute (fir example 7 minutes) and finally at 1 rpm for at least 1 minute (for example 7 minutes). A neutral or acidic solution (for example deionized water) is flowed over the substrate for the entire period of rotation of said substrate, using opposing arrays of spray nozzles.

Following this treatment, rotation is stopped to allow withdrawal of the substrate. The wafe in introduced wet into the electrodeposition cell. B2. Steps 2, 3, and 4:

These steps are identical to those in Example 1.

C. Results obtained

EXAMPLE 6: Preparation of a seed layer in structures of the "through via" type using a composition according to the invention based on a mixture of copper and ethylenediamine.

A. Material and equipment

A1. Substrate:

The substrate used in this example consists of a silicon wafer with a diameter of 150 mm and a thickness of 675 μm, etched with cylindrical patterns of the "through via" type with a depth of 400 μm and a diameter of 50 μm.

A2. Electrodeposition solution:

A3. Equipment:

B1. Step 1 : "pre-wetting"

A physico-chemical treatment is carried out before Step 2 "cold entry" for the purpose of increasing the wettability of the electrodeposition solution in the vias and removing air bubbles. This treatment is carried out in a specific cell where a vacuum can be applied.

The substrate is inserted into this cell and a vacuum is applied using a vane pump

(the pressure is 1 mbar in the example). Still under vacuum, an acidic or neutral solution

(for example deionised water) is introduced into this cell and covers the substrate. When the entire wafer is immersed, the cell is slowly brought to atmospheric pressure. The wafer can thus be withdrawn and introduced wet into the electrodeposition cell.

B2. Steps 2, 3, and 4:

These steps are indentical to those in Example 1.

C. Results obtained

EXAMPLE 7: Characterization of the resistivity of the seed layer obtained on the ISDP layer with the aid of an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Material and equipment

The "sheet resistance" was measured with the aid of a measuring apparatus of the "4 point" type (also called "four point probe") which is well known to the person skilled in the art for measuring the electrical resistance of thin layers. It is expressed in ohms/square, and it is equivalent to the resistivity for a bidimensional system i.e. one in which the current flows in the plane of the layer rather than in a plane perpendicular to this layer. Mathematically, the value of the sheet resistance is obtained by dividing the resistivity of the material (expressed in ohm.m or micro-ohm. cm) constituting the layer by the thickness of this layer (expressed in m or nm).

Annealing is carried out in a horizontal tubular oven. It comprises a base that supports a cylindrical body, itself made up of an internal ceramic tube around which the heating element is wound. The whole arrangement is surrounded by a metal housing and cylindrical metal grille to allow ventilation of the ceramic tube. The oven is used in conjunction with a quartz tube used to hold the samples. This quartz tube is inserted into the ceramic tube. The quartz tube is provided at its left end with a separable ground connector to which a flexible tube is connected that allows gas (96% N₂ / 4% H₂ mixture) flushing of the tube. This allows sample annealing to be carried out under N₂/H₂ atmosphere with an extremely low oxygen level. Annealing can also be carried out in equipment types such as RTP (Rapid Thermal Processing) or RTA (Rapid Thermal Annealing). In these fast annealing ovens, the heating elements are lamps and the substrate is heated by infrared radiation.

B. Measurement Method

The sheet resistance value multiplied by the thickness of the seed layer gives the resistivity of the copper.

C. Results obtained

The copper resistivities obtained in foregoing Examples 1 through 3 are given in Table 1.

Table 1: resistivity of copper seed layers obtained according to Examples 1 though 3.

An increase in resistivity of the seed layer is observed after annealing in every case, due to the formation of copper suicide. These measured resistivity levels before and after annealing are completely compatible with use on an industrial scale.

EXAMPLE 8: Characterization of adhesion of the seed layer obtained on the ISDP layer using an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Material and equipment

The equipment used in this example is identical to that of Example 7, but annealing can also be carried out in various types of equipment, such as of the RTP type. B. Measurement Method

The adhesion or interface energy was measured using the so-called "squares test" technique. A pattern representing 16 squares with a side measuring 0.5 cm is scribed into the seed layer using a diamond point. An adhesive tape is then laid on these squares, and a vertical tension force is applied manually by tearing off this adhesive tape. A count of the number of squares remaining on the sample is then performed, representative of the adhesion energy between the ISDP substrate and the seed layer

C. Results obtained

Table 2 below is a compilation of the results obtained in the foregoing Examples 1 through 3.

Table 2: adhesion of the copper seed layers obtained accordin to Examples 1 throu h 3.

EXAMPLE 9: Characterization of the coverage of the seed layer obtained in structures of the "through via" type using an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Material and equipment

The coverage and conformity of the copper seed layer were evaluated based on examination of sections under the scanning electron microscope, focussing on the lower part of the structures which constitutes the most difficult area to cover.

B. Measurement Method

The percentage of coverage is measured in the lower area of the structures, from the bottom of the vias to 4 μm above them. A percentage of 100% corresponds to complete coverage, i.e. in the lower area the surface of the barrier is completely covered with copper. A surface partially covered with copper is characterized by the fraction of the surface that is covered by copper, expressed as per cent. When coverage is complete, the percentage of conformity is calculated by normalizing the thickness of the seed layer on the vertical surfaces (profile or side) of the via to that on the horizontal surfaces on top of the via. The thickness on the vertical surfaces is measured at a given depth of the via (4 μm above the bottom of the via). A percentage of 100% corresponds to perfect conformity.

C. Results obtained

Table 3 below is a compilation of the results obtained on the copper seed layers prepared using the compositions of the foregoing Examples 4 through 6. Examinations using the scanning electron microscope are plotted in Figure 4 in the case of Example 4, Figure 5 for the case of Example 5 and Figure 6 in the case of Example 6.

Table 3: conformity and coverage of the copper seed layers obtained according to Examples 4 through 6.

Claims

1. A method for treating a semiconductor substrate including the following steps: etching step (S1 ) comprising etching the semiconductor substrate to form at least one pattern forming a cavity, particularly of the "through via" type, with respect to the surface of said semiconductor substrate; deposition step (S2) comprising deposition of an insulating dielectric layer on said surface of said semiconductor substrate; deposition (S3) of a layer of phosphorus in situ doped polysilicon on said insulating dielectric layer; - coating step (S4) comprising coating of said layer of phosphorus in situ doped polysilicon with a layer of metallic copper, wherein the coating step (S4) includes an electrodeposition using an electrodeposition solution made for growth of metallic copper on phosphorus in situ doped polysilicon.

2. The method of Claim 1 , in which the coating step (S4) includes the following successive sub-steps: contacting sub-step (S4-0) comprising bringing said layer of phosphorus in situ doped polysilicon in contact with the electrodeposition solution, and polarization sub-step (S4-2) comprising polarization of said layer of phosphorus in situ doped polysilicon at an electrical potential adapted for electrodeposition of metallic copper on said layer of phosphorus in situ doped polysilicon.

3. The method of Claim 2, in which the coating step (S4) further includes a holding sub- step (S4-1 ), in which, for a determinate duration, said layer of phosphorus in situ doped polysilicon is held in contact with the electrodeposition solution without electrical polarization, said holding sub-step (S4-1 ) being carried out between the contacting sub- step (S4-0) and the polarization sub-step (S4-2).

4. The method of either Claim 2 or Claim 3, in which the coating step (S4) further includes a hot exit sub-step (S4-3) during which said layer of phosphorus in situ doped polysilicon is separated from the electrodeposition solution while still under electrical polarization, said hot exit sub-step (S4-3) being carried out after the polarization sub-step (S4-2).

5. The method of any one of Claims 1 to 4, in which the coating step (S4) includes a prior pre-wetting step comprising bringing the semiconductor substrate in contact with a liquid solution.

6. The method of Claim 5, in which the contacting of the semiconductor substrate with the liquid solution is carried out by a physico-chemical technique comprising use of jets to drive the liquid solution under high pressure, and/or use of ultrasound, and/or use of vacuum.

7. The method of any one of Claims 1 to 6, further including an annealing step (S5) carried out after the coating step (S4), said annealing step (S5) being carried out at a temperature chosen to allow diffusion of the copper into the layer of phosphorus in situ doped polysilicon so as to form copper suicide.

8. The method of any one of Claims 1 to 7, in which the electrodeposition solution includes, in solvent solution: copper ions at a concentration of between 14 and 120 mM, and ethylenediamine, wherein the molar ratio between ethylenediamine and copper is between 1.80 and 2.03, and the pH of said electrodeposition solution is between 6.6 and 7.5.

9. A multilayer stack comprising: a semiconductor substrate with a surface having a pattern forming at least one cavity, particularly of the "through via" type, an insulating dielectric layer covering said surface, - a layer of phosphorus in situ doped polysilicon covering said insulating dielectric layer, and a layer of metallic copper covering said layer of phosphorus in situ doped polysilicon.

10. The stack of Claim 9, in which the copper layer fills the at least one cavity and includes a plane external surface.