WO2010141059A3 - Methods for controlling host memory access with memory devices and systems - Google Patents

Methods for controlling host memory access with memory devices and systems Download PDF

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Publication number
WO2010141059A3
WO2010141059A3 PCT/US2010/001521 US2010001521W WO2010141059A3 WO 2010141059 A3 WO2010141059 A3 WO 2010141059A3 US 2010001521 W US2010001521 W US 2010001521W WO 2010141059 A3 WO2010141059 A3 WO 2010141059A3
Authority
WO
WIPO (PCT)
Prior art keywords
systems
methods
memory access
controlling host
memory
Prior art date
Application number
PCT/US2010/001521
Other languages
French (fr)
Other versions
WO2010141059A2 (en
Inventor
Neal A. Galbo
Peter Feeley
William H. Radke
Victor Y. Tsai
Robert N. Leibowitz
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to KR1020127000024A priority Critical patent/KR101371936B1/en
Priority to CN201080024691.9A priority patent/CN102460405B/en
Priority to EP10783693.4A priority patent/EP2438522B1/en
Priority to JP2012513924A priority patent/JP5638069B2/en
Publication of WO2010141059A2 publication Critical patent/WO2010141059A2/en
Publication of WO2010141059A3 publication Critical patent/WO2010141059A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices

Abstract

The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.
PCT/US2010/001521 2009-06-03 2010-05-24 Methods for controlling host memory access with memory devices and systems WO2010141059A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020127000024A KR101371936B1 (en) 2009-06-03 2010-05-24 Methods for controlling host memory access with memory devices and systems
CN201080024691.9A CN102460405B (en) 2009-06-03 2010-05-24 For being carried out the method and system of main control system memory access by storage arrangement
EP10783693.4A EP2438522B1 (en) 2009-06-03 2010-05-24 Methods for controlling host memory access with memory devices and systems
JP2012513924A JP5638069B2 (en) 2009-06-03 2010-05-24 Method and system for controlling host memory access by a memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/477,204 2009-06-03
US12/477,204 US8225052B2 (en) 2009-06-03 2009-06-03 Methods for controlling host memory access with memory devices and systems

Publications (2)

Publication Number Publication Date
WO2010141059A2 WO2010141059A2 (en) 2010-12-09
WO2010141059A3 true WO2010141059A3 (en) 2011-03-03

Family

ID=43298357

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/001521 WO2010141059A2 (en) 2009-06-03 2010-05-24 Methods for controlling host memory access with memory devices and systems

Country Status (7)

Country Link
US (3) US8225052B2 (en)
EP (1) EP2438522B1 (en)
JP (1) JP5638069B2 (en)
KR (1) KR101371936B1 (en)
CN (1) CN102460405B (en)
TW (1) TWI436217B (en)
WO (1) WO2010141059A2 (en)

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US9824004B2 (en) 2013-10-04 2017-11-21 Micron Technology, Inc. Methods and apparatuses for requesting ready status information from a memory
CN103631534B (en) * 2013-11-12 2017-01-11 北京兆芯电子科技有限公司 Data storage system and managing method thereof
CN104636081B (en) * 2013-11-12 2017-11-14 上海兆芯集成电路有限公司 Data-storage system and its management method
US10108372B2 (en) 2014-01-27 2018-10-23 Micron Technology, Inc. Methods and apparatuses for executing a plurality of queued tasks in a memory
US9454310B2 (en) 2014-02-14 2016-09-27 Micron Technology, Inc. Command queuing
US11030122B2 (en) * 2014-04-08 2021-06-08 Micron Technology, Inc. Apparatuses and methods for securing an access protection scheme
US9851901B2 (en) * 2014-09-26 2017-12-26 Western Digital Technologies, Inc. Transfer of object memory references in a data storage device
US9535850B1 (en) 2015-01-28 2017-01-03 Google Inc. System and method for efficient DMA transfers
US10120818B2 (en) * 2015-10-01 2018-11-06 International Business Machines Corporation Synchronous input/output command
KR20170046862A (en) * 2015-10-21 2017-05-04 에스케이하이닉스 주식회사 Memory system and operating method of memory system
KR20180018886A (en) 2016-08-09 2018-02-22 삼성전자주식회사 Operation method of storage system and operation method of host
US10621117B2 (en) * 2017-06-15 2020-04-14 Micron Technology, Inc. Controlling memory devices using a shared channel
KR20190106228A (en) * 2018-03-08 2019-09-18 에스케이하이닉스 주식회사 Memory system and operating method of memory system
US10853273B2 (en) * 2018-08-01 2020-12-01 Micron Technology, Inc. Secure memory system programming
US11599481B2 (en) 2019-12-12 2023-03-07 Western Digital Technologies, Inc. Error recovery from submission queue fetching errors
CN116964565A (en) * 2020-12-17 2023-10-27 华为技术有限公司 Data processing method and related equipment
US20220291947A1 (en) * 2021-03-10 2022-09-15 Meta Platforms, Inc. Apparatus, systems, and methods for facilitating efficient hardware-firmware interactions

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Also Published As

Publication number Publication date
US20120284466A1 (en) 2012-11-08
EP2438522A2 (en) 2012-04-11
CN102460405B (en) 2015-11-25
CN102460405A (en) 2012-05-16
TW201104438A (en) 2011-02-01
KR20120014938A (en) 2012-02-20
US9811258B2 (en) 2017-11-07
JP5638069B2 (en) 2014-12-10
TWI436217B (en) 2014-05-01
US20100312973A1 (en) 2010-12-09
KR101371936B1 (en) 2014-03-07
EP2438522A4 (en) 2013-05-08
US20150153956A1 (en) 2015-06-04
US8918600B2 (en) 2014-12-23
US8225052B2 (en) 2012-07-17
JP2012529103A (en) 2012-11-15
EP2438522B1 (en) 2015-10-28
WO2010141059A2 (en) 2010-12-09

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