WO2011056668A3 - Selective die electrical insulation additive process - Google Patents

Selective die electrical insulation additive process Download PDF

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Publication number
WO2011056668A3
WO2011056668A3 PCT/US2010/054325 US2010054325W WO2011056668A3 WO 2011056668 A3 WO2011056668 A3 WO 2011056668A3 US 2010054325 W US2010054325 W US 2010054325W WO 2011056668 A3 WO2011056668 A3 WO 2011056668A3
Authority
WO
WIPO (PCT)
Prior art keywords
die
electrical insulation
additive process
die electrical
insulation additive
Prior art date
Application number
PCT/US2010/054325
Other languages
French (fr)
Other versions
WO2011056668A2 (en
Inventor
Jeffrey S. Leal
Original Assignee
Vertical Circuits, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits, Inc. filed Critical Vertical Circuits, Inc.
Publication of WO2011056668A2 publication Critical patent/WO2011056668A2/en
Publication of WO2011056668A3 publication Critical patent/WO2011056668A3/en

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Abstract

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
PCT/US2010/054325 2009-10-27 2010-10-27 Selective die electrical insulation additive process WO2011056668A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25542909P 2009-10-27 2009-10-27
US61/255,429 2009-10-27

Publications (2)

Publication Number Publication Date
WO2011056668A2 WO2011056668A2 (en) 2011-05-12
WO2011056668A3 true WO2011056668A3 (en) 2011-09-15

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Application Number Title Priority Date Filing Date
PCT/US2010/054325 WO2011056668A2 (en) 2009-10-27 2010-10-27 Selective die electrical insulation additive process

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US (2) US9147583B2 (en)
TW (1) TWI520213B (en)
WO (1) WO2011056668A2 (en)

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KR101554761B1 (en) * 2008-03-12 2015-09-21 인벤사스 코포레이션 Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
JP5512292B2 (en) * 2010-01-08 2014-06-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
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US20160020188A1 (en) 2016-01-21
US9147583B2 (en) 2015-09-29

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