WO2011067625A1

WO2011067625A1 - A system for processing audio data

Info

Publication number: WO2011067625A1
Application number: PCT/IB2009/055442
Authority: WO
Inventors: Santosh Narayan Shilimkar
Original assignee: Nxp B.V.
Priority date: 2009-12-01
Filing date: 2009-12-01
Publication date: 2011-06-09

Abstract

A device (100) for processing audio data, wherein the device (100) comprises a detection unit (102) adapted for detecting a transition between a first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency, a control unit (104) adapted for disconnecting, during the transition, audio domain clocks from a clock frequency relating to the first sampling frequency and connecting the audio domain clocks to a transition frequency, wherein the control unit (104) is further adapted for disconnecting, after the transition, the audio domain clocks from the transition frequency and connecting the audio domain clocks to a clock frequency relating to the second sampling frequency.

Description

A SYSTEM FOR PROCESSING AUDIO DATA

FIELD OF THE INVENTION

The invention relates to a device for processing audio data.

Beyond this, the invention relates to a method of processing audio data.

Moreover, the invention relates to a program element.

Furthermore, the invention relates to a computer-readable medium.

BACKGROUND OF THE INVENTION

Audio playback devices become more and more important. Particularly, an increasing number of users buy headphone-based audio players and loudspeaker-based audio surround systems.

When different audio items are played back by an audio player one after another, it is desirable to have an apparently seamless transition between two subsequent tracks.

US 2005/0080500 Al discloses an audio device which includes a DVD player for decoding an input audio signal and for outputting a digital audio signal, an audio amplifier for outputting an analog audio signal based on the digital audio signal, an audio decoder for detecting a change of an audio attribute, a decoding suspension unit for muting an output from the audio amplifier and temporarily suspending an operation of the decoder when the change of the attribute is detected, and a setting changing unit for changing operation conditions of the audio amplifier so as to correspond to the changed audio attribute when a muting part operates.

However, a transition between two audio pieces may still sound artificial for a human listener.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide an audio data processing system allowing for a proper experience even at the beginning or end of an audio item or when changing the audio track.

In order to achieve the object defined above, a device for processing audio data, a method of processing audio data, a program element and a computer-readable medium according to the independent claims are provided.

According to an exemplary embodiment of the invention, a device for processing audio data is provided, wherein the device comprises a detection unit adapted for detecting a transition between a first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency (which may differ from the first sampling frequency), and a control unit adapted for disconnecting, during the transition, audio domain clocks (for instance all audio domain clocks of an audio playback system) from a clock frequency relating to the first sampling frequency (for instance a clock frequency being an integer multiple of the first sampling frequency, for instance 256 times the first sampling frequency) and connecting the audio domain clocks to a transition frequency, wherein the control unit is further adapted for disconnecting, after the transition, the audio domain clocks from the transition frequency and connecting the audio domain clocks to a clock frequency relating to the second sampling frequency (for instance a clock frequency being an integer multiple of the second sampling frequency, for instance 256 times the second sampling frequency).

According to another exemplary embodiment of the invention, a method of processing audio data is provided, wherein the method comprises detecting a transition between a first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency, disconnecting, during the transition, audio domain clocks from a clock frequency relating to the first sampling frequency and connecting the audio domain clocks to a transition frequency, and disconnecting, after the transition, the audio domain clocks from the transition frequency and connecting the audio domain clocks to a clock frequency relating to the second sampling frequency.

According to still another exemplary embodiment of the invention, a program element (for instance a software routine, in source code or in executable code) is provided, which, when being executed by a processor, is adapted to control or carry out a data processing method having the above mentioned features.

According to yet another exemplary embodiment of the invention, a computer- readable medium (for instance a CD, a DVD, a USB stick, a floppy disk or a harddisk) is provided, in which a computer program is stored which, when being executed by a processor, is adapted to control or carry out a data processing method having the above mentioned features.

Data processing for audio transition purposes which may be performed according to embodiments of the invention can be realized by a computer program, that is by software, or by using one or more special electronic optimization circuits, that is in hardware, or in hybrid form, that is by means of software components and hardware components.

The term "piece of audio data" may denote a file or a data collection including data representing acoustic data such as a song, a speech, or the like. Such a piece of audio data may have a quality depending on a sampling frequency (for instance 48 kHz)

characterizing the audio piece. The higher the sampling frequency, the better the quality of the audio piece may be.

The term "transition between pieces of audio data" may particularly denote a time interval after a previous audio piece has faded out and a subsequent audio piece starts to fade in. When the sampling frequencies of the two audio pieces differ from one another, an adjustment of clock frequencies (which may be correlated to sampling frequencies) may be necessary which may conventionally result in an annoying audible artefact that may be denoted as an audio "plop". The term "transition between pieces of audio data" may also denote a change between different audio tracks.

The term "audio domain clock" may particularly denote one or more clocks which are used by an audio playback or audio processing system for driving various components such as an interpolator, a digital to analog converter, etc. One or more audio domain clocks may be generated by a clock factory or clock generation unit (CGU).

The term "transition frequency" may particularly denote an auxiliary frequency, which may be provided by a frequency generator or clock generator such as a fixed oscillator and which has a specific frequency of, for instance, 12 MHz. Such a frequency may be constant with a high precision.

The term "clock" may denote a sequence of alternating "high" logical values and "low" logical values. Thus, such clocks may define processing speed.

According to an exemplary embodiment of the invention, an audio plop may be efficiently suppressed by avoiding a stop or break of a clock during a transition between two audio pieces having different sampling frequencies. This may be achieved by bridging a switching period by providing a transition frequency such as a frequency generated by a fixed oscillator between the two pieces of audio data having possibly different sampling frequencies. Thus, a software based and therefore cheap way of preventing an audio plop may be provided, thereby significantly improving the audible acoustic quality without involving additional hardware costs.

According to an exemplary embodiment of the invention, an audio processing device may be provided comprising means to prevent a hearable spike (audible "plop") in case of switching between audio streams of different sampling frequency.

An aim according to an exemplary embodiment of the invention is to prevent or suppress an audio plop that can be heard on speakers because of the change in the sampling frequency. In contrast to purely hardware based solutions trying to avoid such a plop but adding additional costs for portable audio solutions, embodiments add a software based plop suppression at very low cost. Another disadvantage which may be overcome according to an exemplary embodiment of the invention is that hardware based solutions occupy area on a

Printed Circuit Board which may be undesirable in view of a portable player form factor.

Moreover, pure hardware solutions add to die size which is also expensive. Embodiments of the invention are software based so that an additional cost is almost zero.

During an audio clock switching, the whole audio domain clock (like BCK,

WCK, Fs, 256*Fs, 1024*Fs, etc., wherein Fs may denote a sampling frequency) values will be changed as per the new sampling frequency. During switching, for a small period of time (a few microseconds, depending on the clock systems of an SOC, System on Chip), the clocks to the audio hardware system are stopped. A root cause of such an issue is that the clock of the stereo audio DAC is getting stopped. However, the clock to the stereo audio DAC should not be stopped at any point of time when the audio sub-system is active because this may result in a spike (plop) at the audio output.

Conventional hardware based solutions try to cancel out this spike by applying cosine roll-off curves or kind of S-curves. If the root cause (the clock of the audio DAC should keep running during the sampling frequency change) is solved by embodiments of the invention, there remains no need to implement any hardware based work-around solution.

Embodiments of the invention actually solve the root cause with a software based technique using the clock system hardware.

In the following, further exemplary embodiments of the device will be explained. However, these embodiments also apply to the method, to the program element and to the computer-readable medium.

The detection of the change in the sampling frequency may be done at a software application level. For example in MP3 tracks, the ID3 tag may provide such information. So in software before the first track ends, a user can already read the ID3 tag of the next song and find out the next audio sampling frequency. So this change detection may be handled completely in software by the software application.

The control unit may be adapted for processing the first piece of audio data and the second piece of audio data in such a manner that an audible spike is suppressed during the transition. Thus, the clock management may be specifically adjusted to eliminate the audible plop or to at least suppress it efficiently. For this purpose, an uninterrupted supply of clock signals may be guaranteed during sampling frequency switch.

The control unit may be adapted for processing the first audio piece of audio data and the second piece of audio data in such a manner that an audio domain clock is prevented from being stopped during the transition. It has been recognized by the present inventor that a stop or interruption of a clock, i.e. a time interval in which no clock signal is provided, may be a course of an audio plop. By preventing such a stop, particularly of a clock of a digital to analog converter (DAC) for converting decoded audio data from the digital to the analog domain, it is possible to significantly improve the audio quality.

The control unit may be adapted for disconnecting, during the transition, the audio domain clocks from an audio phase locked loop (PLL). Such an audio phase locked loop may provide a contribution to clock generation. During the transition period, the fixed oscillator may be used for providing a clock signal.

The control unit may be adapted for configuring, during the transition, the audio phase locked loop to the second sampling frequency. Therefore, while the transition frequency is active, the system may continue for adapting the system to the sampling frequency of the subsequent audio piece.

The control unit may be adapted for reconnecting, after the transition, the audio domain clocks to the audio phase locked loop (PLL). When the transition has been finished, the transition frequency may be deactivated, and the system may continue to work on the basis of the second sampling frequency that may be the base of the generation of all audio clocks.

The transition frequency may be approximately a binary power (2ⁿ, n=l,2,...) of the first sampling frequency and/or of the second sampling frequency. For example, the first sampling frequency may be 44, 1 kHz, which is a characteristic sampling frequency of an MP3 song, whereas the second sampling frequency may be a 48 kHz song. In such a scenario, the transition frequency may be 12 MHz, which is approximate 2⁸ of the sampling frequencies.

For instance, a sampling frequency may be 44.1 kHz or 48 kHz, the

corresponding clock frequencies may be 256x44.1 kHz=l 1.29MHz or 256x48

kHz=12.29MHz, and the transition frequency may be 12MHz.

The device may comprise a fixed oscillator (such as a quartz oscillator) which may provide a transition frequency. This transition frequency may be a very constant frequency of, for instance, 12 MHz, which may serve for bridging the reconfiguration interval or the transition period between the two audio pieces. The control unit may be adapted for disconnecting the audio domain clocks from the first sampling frequency and connecting the audio domain clocks to the transition frequency when the audio domain clocks are low (or on a falling edge). The clocks are sequences of logical values of "1" and "0", whereas "1" can be indicated with a "high" logic state, whereas the logic state "0" can be assigned to a "low" logic state. When the transition is performed at a point of time when the clocks are low, the audible plop can be suppressed extremely efficiently. In a similar manner, the control unit may further be adapted for disconnecting the audio domain clocks from the transition frequency and connecting the audio domain clocks to the second sampling frequency when the audio domain clocks are low (or on a falling edge). Thus, also the reconnection can be performed in the low state of the clock, thereby significantly improving a signal quality and suppressing the audible plop.

The device may comprise an audio playback unit adapted for reproducing the processed audio data. Such a reproduction unit may generate acoustic waves based on the processed audio data, which can be listened to by a human being. Such an audio playback unit may include earpieces, loudspeakers, etc.

However, although the system according to an embodiment of the invention primarily intends to improve the quality of sound or audio data, it is also possible to apply the system for a combination of audio data and visual data. For instance, an embodiment of the invention may be implemented in audiovisual applications like a video player or a home cinema system in which a transition between different audiovisual items (such as music clips or video sequences) takes place. In an embodiment, it is thus also possible that the device processes combined audio and video data. Video streams may comprise audible portions and image portions. When two video items, such as two music clips, are played back one after the other, an audible plop may occur as well during a transition. By processing the audio data in a manner as described herein, the quality of the audiovisual reproduction may be further increased.

The device for processing audio data may be realized as at least one of the group consisting of an audio surround system, a mobile phone, a headset, a loudspeaker, a hearing aid, a television device, a video recorder, a monitor, a gaming device, a laptop, an audio player, a DVD player, a CD player, a harddisk-based media player, an internet radio device, a public entertainment device, an MP3 player, a hi-fi system, a vehicle entertainment device, a car entertainment device, a medical communication system, a body-worn device, a speech communication device, a home cinema system, a home theatre system, a flat television, an ambiance creation device, a subwoofer, and a music hall system. Other applications are possible as well.

At a transition between two audio pieces, an audio plop may occur due to a sudden change of the sampling frequencies. The sampling frequencies may be an indicator for a quality of an audio piece. The audio plop may be audible as an annoying noise between two pieces because of this limitation. According to an exemplary embodiment of the invention, such an audio block may be eliminated. This may be performed with lower costs and more efficiently as compared to conventional solutions involving complex hardware circuits for the suppression of audio plops.

When processing audio data, the audio data are first decoded and the decoded output is then sampled, for rendering purposes. Rendering may involve components such as an interpolator (which may comprise FIFO buffers pushing audio samples in a forward direction), before these data are supplied to a stereo DAC (digital to analog converter). Subsequently, the audio data may be amplified and played back by speakers.

Each audio component needs clocks for being operated, which clocks may depend on the sampling rate. Clocks may be basically multiples of the sampling frequencies. Using clocks, a synchronization of the different components of an audio playback system may be achieved. For example, an interpolator may require clocks for being operated properties.

In order to prevent an audio plop according to an embodiment of the invention, it may be important that the clock is never stopped during the processing. In a clock factory section, a phase locked loop (PLL) may generate a clock and may be connected to a crystal oscillator during a transition period.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited.

Fig. 1 illustrates a system of processing audio data according to an exemplary embodiment of the invention.

Fig. 2 illustrates a flow-chart diagram illustrating a method of processing audio data according to an exemplary embodiment of the invention.

Fig. 3 is a block diagram of an audio processor which can be implemented according to an exemplary embodiment of the invention. Fig. 4 illustrates a block diagram of a switch box module of the system shown in Fig. 3.

Fig. 5 illustrates a block diagram of an audio playback path in silicon architecture.

DESCRIPTION OF EMBODIMENTS

The illustration in the drawing is schematically. In different drawings, similar or identical elements are provided with the same reference signs.

Fig. 1 illustrates a system 100 for processing audio data according to an exemplary embodiment of the invention.

An audio source 120 is provided which can be a harddisk storing different audio pieces, a CD inserted in a reception of a CD player, etc. The audio source 120 may be or may be part of a portable player.

The audio playback system 100 further comprises an input/output unit 130 which allows a user to bidirectionally communicate with the various components of the system 100. The input/output unit 130 may comprise input elements such as buttons, a keypad, a joystick, etc. and may include a display element such as a liquid crystal display so that information regarding audio items to be played back may be displayed to a user. Via the input/output unit 130, a user may select audio pieces and a sequence/order of audio pieces stored in the audio source 120 to be played back by the system 100.

Via a bi-directional communication, the input/output unit 130 may communicate with a control unit 104 such as a microprocessor or a CPU (central processing device). The control unit 104 may be supplied with data representing audio pieces stored on the audio source 120 for playback.

In the following, a scenario will be considered in which a first audio piece (such as a first song) stored on the audio source 120 is played back first, and subsequently a second audio piece (such as a second song) is to be played back which has a different sampling frequency than the first audio piece.

Before reproduction, the audio pieces are supplied to a detection unit 102 which may be adapted for detecting a transition between the first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency. For example, it is possible that the detection unit 102 analyzes the headers of the respective audio pieces to thereby detect that a transition between a first and a second audio piece will occur soon. This information may be supplied in the form of a control signal from the detection unit 102 to the control unit 104.

The control unit 104 is also supplied with the audio data to be played back and allows for an audio processing which can suppress an undesired audio plop in a transition period between the two audio pieces having different sampling frequencies. For that purpose, the control unit 104 disconnects, during the transition, all audio domain clocks from a clock signal which may be adjusted in accordance with the first sampling frequency and connects the audio domain clocks to a fixed transition frequency which may be provided by a fixed oscillator 106 coupled to the control unit 104. Furthermore, after the transition, the control unit 104 disconnects all audio domain clocks from the transition frequency and connects the audio domain clocks to a clock signal which may be adjusted in accordance with the second sampling frequency of the second audio piece provided by the audio data source 120.

Therefore, the control unit 104 may control clocks of the various components of the audio playback device 100 in a transition to prevent a clock signal from being stopped during the transition.

The processed audio data may then be reproduced by a loudspeaker 108 to generate acoustic waves 150 which can be listened by a human listener without involving undesired audible plops.

Fig. 2 shows a flow-chart 200 illustrating a method according to an exemplary embodiment of the invention which can be carried out by the system 100 shown in Fig. 1.

A block 205 indicates an end of an MP3 song sampled at a sampling frequency of 44.1 kHz. As can be taken from a block 250, a subsequent song may be played back at a sampling frequency of 48 kHz. Conventionally, the transition between different clocks after the reproduction of the first audio song at the first playback rate of 44.1 kHz and before the reproduction at a second sampling frequency of 48 kHz may result in an annoying audio plop.

However, by performing the measures according to the blocks 210, 220 and

230 shown in Fig. 2, such an audible plop may be securely prevented.

As can be taken from block 210, the audio domain clocks are disconnected from an audio PLL (phase locked loop) and are connected to a fixed oscillator 106 (for instance a crystal oscillator having an oscillation frequency of 12 MHz, using a switch box module which will be explained below in more detail).

During the procedures according to block 210, a very short stop may take place. In order to prevent any audio plop here, the switch or the disconnection and connection of block 210 may be performed in a clock factory module (see Fig. 3) during a phase when the clock is low. Thus, a low pulse of the clock may be used for the switching within the block 210.

During the procedure of block 220, the system runs on the basis of the 12 MHz crystal frequency. Simultaneously, it is possible to configure the audio PLL (phase locked loop) for the new sampling frequency of 48 kHz.

In a block 230, the audio domain clocks are reconnected from the fixed oscillator 106 (that is a 12 MHz clock frequency) and are connected to an audio PLL (phase locked loop) again using the switch box module illustrated below in Fig. 3 and Fig. 4. Also this reconnection and connection may be performed during a low pulse of the clocks or at a falling edge of the clock.

Thus, a complete (software) flow diagram 200 of an embodiment of the invention is shown in Fig. 2. Suppose a 44.1 kHz MP3 song playback is going on and the next song is of 48 kHz sampling frequency.

So as shown in the flow diagram 200 also, whenever there is a need to change of the audio sampling frequency the above procedure may be used:

1. Sampling frequency change needs to be detected in the system by the software. This may be done in the application by reading the stream headers, (for instance ID3 tag information for MP3 files). So whenever the new stream (audio and/or video) has a different audio sampling rate than the previously played stream, the software application can detect this easily. Upon detection the next steps are followed.

2. Since the audio clocks needs to be changed from the existing clock (related to 44.1 kHz) to the new clock (related to 48 kHz ) without stopping the clocks to the audio DAC module, an intermediate transition may be done to a fixed clock (for instance 12 MHz crystal). The clock running to the audio DAC and different audio modules may be 256 fs, 128 fs, 512 fs, 1024 fs, wherein fs is the sampling frequency. So in the given example case, the clock is switched from 11.2896 MHz (that is 256 44.1 kHz ) to 12 MHz. This transition is handled using the software functions which controls the clock generation unit of the system. Underneath software functions which handle the switching from one clock to the another clock is a hardware block called switchbox provided by the CGU (Clock Generation Unit) hardware.

More details are given on the clock switching process at the hardware level.

Information about the CGU and switchbox hardware used in a PNX0103 system are as described below. The CGU generates all the clock signals in the PNX0103 system. As shown in the block diagram of the CGU of Fig. 3, the CGU has a regular structure.

Each output clock generated by the CGU, belongs to one of the system or audio clock domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources.

Within a clock domain, fractional dividers are available to divide the base clock into a lower frequency. Within most clock domains, the output clocks are again grouped into one or more sub domains. All output clocks within one sub domain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one sub domain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock The CGU has a reference clock (generated by the oscillator) and several external clock inputs.

The CGU also has several phase locked loop (PLL) circuits to generate clock signals that can be used for system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can be used as reference input for the PLL.

The audio clocks are generated from an audio PLL in the PNX0103 System. The block diagram of the switchbox module is given in Fig. 4.

Selection multiplexer switches allow each reference frequency to be passed to each base frequency. Frequency switches allow safe run-time changes of base frequency selection.

A two path switch may be used because there are no guaranteed clocks, making the use of state machines difficult. The frequency selector uses two multiplexers on all of the reference frequency inputs, resulting in the frequency fl and f2. Two multiplexers are used to avoid glitches. Glitches can occur either, when multiplexing, or because the two frequencies are asynchronous (which they usually are) and the switching results in pulse- clipping.

The switch, as implemented above, solves these problems. This is done by selecting the new frequency on the multiplexer towards the switch side that is not activated, then by both removing the enable on one side, and activating the enable on the other side, switching take place. The construction of the switch is such that a base clock (the base frequency) is stopped when its level is low and after (at least) a complete period, at the falling edge of the new frequency, base clock will start to run again with this new frequency.

The CGU module is controlled using a software driver. This software driver routines uses the hardware as described above to ensure that the clock is not stopped during the change over from one clock to the another.

1. This steps configures all the PLL hardware registers to the new sampling frequency. (12.228 MHz = 256 48 kHz in an example ). The audio DAC and different audio modules are still running at the 12 MHz crystal clock.

2. In this step the audio clocks are reconnected to the audio PLL base from the crystal. So now audio DAC and audio modules are running with the new sampling frequency.

3. From here the new stream of 48 kHz can be played.

In the following, an example software code will be given:

Application ()

{

/*User wants to play a audio stream of 44.1 kHz Sampling frequency */

the audio clocks for 44.1 KHz with proper switching */ vhClk_SwitchDomain( VH_CLK_CLK1024FS_BASE7,

VH CLK DOMAIN DISABLE);

vhClk_SetSampFreq ( VH CLK A UDIOPLL ID

, VH CLK FS 44100HZ);

vhClk_SwitchDomain( VH_CLK_CLK1024FS_BASE7,

VH CLK DOMAIN DISABLE);

/* start playback of audio stream of 44.1 Khz sampling frequency */ Playback ( songl _44.1kHz);

/* songl _44.1 kHz is over */

/* User wants to playback the song of 48 kHz sampling freq */

the audio clocks for 48 KHz with proper switching */ vhClk_SwitchDomain( VH_CLK_CLK1024FS_BASE7,

VH CLK DOMAIN DISABLE);

vhClk_SetSampFreq ( VH CLK A UDIOPLL ID

, VH CLK FS 48KHZ);

vhClk_SwitchDomain( VH_CLK_CLK1024FS_BASE7,

VH CLK DOMAIN DISABLE);

/* start playback of audio stream of 48 Khz sampling frequency */ Playback ( song2 _48kHz) ; /* Continue */

}

The software driver (CGU) attached with this invention has the implementation of the functions that are used during the sampling frequency change. Fig. 5 illustrates a block diagram 500, which is showing an audio playback path in an integrated architecture.

A bold line 502 shows an audio playback path from a memory device 504 providing audio samples to a headphone 506.

Relevant blocks in the playback path 502 are:

SAO 510/SAI 508: Simple audio input/ output units are used to stream the audio data from a memory bus to DAO 512/DAI 514. These are kind of hardware FIFOs and work with DMA flow control.

DAI 514/DAO 512:These are 12 S audio input and output devices.

DMUX 516: This is used to switch between audio sources. This is a demultiplexer which can select the input signal depending on control setting and connect it to an output.

INT (Interpolator) 518: This is a stereo interpolation filter with a noise shaper circuit. Upsamling, demphasis, digital mute signal, silence detection, and noise shaping is done in this block. I2S signal is converted to the up sampled digital audio samples.

SDAC (Stereo DAC) 520: This block is a digital to analog converter which converts a digital audio signal to an analog audio signal.

CLASS AB 522: It is the headphone amplifier to drive the

speakers/headphones 506.

The rest of the blocks are less relevant and provide the following functionality:

LNA 524: Low Noise amplifier used for low microphone signals.

PGA 526 (Programmable Gain Amplifier): Input stage audio gain can be controlled here.

MUX 528: Selects one of the input signal depending on the control settings

SDC 530: Differential Converter.

ADC 532: Analog to digital converter.

DEC 534: Digital audio to I2S audio converter.

AVC 536: Analog Bypass Modules

It should be noted that the term "comprising" does not exclude other elements or features and the "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined.

It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims

CLAIMS:

1. A device (100) for processing audio data, wherein the device (100) comprises

a detection unit (102) adapted for detecting a transition between a first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency;

a control unit (104) adapted for disconnecting, during the transition, audio domain clocks from a clock frequency relating to the first sampling frequency and connecting the audio domain clocks to a transition frequency;

wherein the control unit (104) is further adapted for disconnecting, after the transition, the audio domain clocks from the transition frequency and connecting the audio domain clocks to a clock frequency relating to the second sampling frequency.

2. The device (100) according to claim 1, wherein the control unit (104) is adapted for processing the first piece of audio data and the second piece of audio data in such a manner that an audible spike is suppressed during the transition.

3. The device (100) according to claim 1, wherein the control unit (104) is adapted for processing the first piece of audio data and the second piece of audio data in such a manner that audio domain clocks, particularly a clock of a digital to analog converter for converting digital audio data into analog audio data, is prevented from being stopped during the transition.

4. The device (100) according to claim 1, wherein the control unit (104) is adapted for disconnecting, during the transition, the audio domain clocks from an audio phase locked loop.

5. The device (100) according to claim 4, wherein the control unit (104) is adapted for configuring, during the transition, the audio phase locked loop to operate with the second sampling frequency.

6. The device (100) according to claim 4, wherein the control unit (104) is adapted for reconnecting, after the transition, the audio domain clocks to the audio phase locked loop.

7. The device (100) according to claim 1, wherein the transition frequency is larger than the first sampling frequency and/or the second sampling frequency.

8. The device (100) according to claim 1, wherein the transition frequency is a fixed frequency.

9. The device (100) according to claim 1, comprising a fixed oscillator (106) adapted for providing the transition frequency.

10. The device (100) according to claim 1, wherein the control unit (104) is adapted for disconnecting the audio domain clocks from the first sampling frequency and for connecting the audio domain clocks to the transition frequency during a low clock state.

11. The device (100) according to claim 1, wherein the control unit (104) is further adapted for disconnecting the audio domain clocks from the transition frequency and for connecting the audio domain clocks to the second sampling frequency during a low clock state.

12. The device (100) according to claim 1, comprising an audio playback unit (108) adapted for reproducing the processed audio data.

13. The device (100) according to claim 1, adapted for processing combined audio and video data.

14. The device (100) according to claim 1, adapted for at least one of the group consisting of an automatic disc jockey system, a broadcasting channel switch system, a public Internet page switch system, a telephony channel switch system, and an audio item playback system.

15. The device (100) according to claim 1, realized as at least one of the group consisting of an audio surround system, a mobile phone, a headset, a headphone playback apparatus, a loudspeaker playback apparatus, a hearing aid, a television device, a video recorder, a monitor, a gaming device, a laptop, an audio player, a DVD player, a CD player, a harddisk- based media player, a radio device, an internet radio device, a public entertainment device, an MP3 player, a hi-fi system, a vehicle entertainment device, a car entertainment device, a medical communication system, a body-worn device, a speech communication device, a home cinema system, a home theatre system, a flat television apparatus, an ambiance creation device, a subwoofer, and a music hall system.

16. A method of processing audio data, wherein the method comprises

detecting a transition between a first piece of audio data having assigned a first sampling frequency and a second piece of audio data having assigned a second sampling frequency;

disconnecting, during the transition, audio domain clocks from a clock frequency relating to the first sampling frequency and connecting the audio domain clocks to a transition frequency;

disconnecting, after the transition, the audio domain clocks from the transition frequency and connecting the audio domain clocks to a clock frequency relating to the second sampling frequency.

17. A computer-readable medium, in which a computer program of processing audio data is stored, which computer program, when being executed by a processor (100), is adapted to carry out or control a method according to claim 16.

18. A program element of processing audio data, which program element, when being executed by a processor (100), is adapted to carry out or control a method according to claim