WO2011132310A1

WO2011132310A1 - Information processing device and semiconductor storage device

Info

Publication number: WO2011132310A1
Application number: PCT/JP2010/057248
Authority: WO
Inventors: 関口　知紀; 俊樹菅原; 斎藤　慎一
Original assignee: 株式会社日立製作所
Priority date: 2010-04-23
Filing date: 2010-04-23
Publication date: 2011-10-27

Abstract

There is a demand to increase the data transfer speed between dynamic random access memory (DRAM) and a system LSI or CPU chip having multiple CPU cores. In order to meet this demand, a memory module is disclosed which is mounted with multiple DRAM chips and multiple interface chips corresponding to each of the chips. Each DRAM chip is divided into multiple DRAM cores, and the interface chips are divided into interface cores corresponding to each DRAM core. Via the corresponding interface chip, the DRAM cores send and receive command address signals and data signals to and from the corresponding memory controller core by using each single optical interface.

Description

Information processing apparatus and semiconductor memory device

The present invention relates to an information processing apparatus and a semiconductor memory device.

Currently, in system LSIs and microprocessors, a multi-core configuration in which a plurality of CPU (Central Processing Unit) cores are provided inside has become widespread. When the multi-core configuration is adopted, the calculation performance can be increased without excessively increasing the clock frequency of the chip, so that power consumption can be kept low. As for the number of CPU cores mounted on one chip, microprocessors for personal computers and servers are beginning to mount 2 to 4 cores, and this number is expected to increase to 100 or more in the future. As the number of CPU cores increases in this way, the data rate required for calculation increases accordingly.

Currently, the DDR3 DRAM used as the main memory constitutes a 64-bit width module at 1.6 Gbps per bit, and a data rate of 38.4 GB / s is obtained by using three modules in parallel. However, since the demand for increasing the data rate will continue to increase, a memory module having a data rate of 1 TB / s will be required in the future.

In order to realize such a high-speed main memory, even if four modules having a 64-bit bus width are used in parallel, the transmission speed per pin is required to be 32 Gbps. When the transmission speed exceeds 10 Gbps, even when the transmission is performed at a distance of several tens of centimeters as in a printed circuit board, when an electric signal is used, reflection and interference of the signal become significant, and stable high-speed transmission becomes difficult. Therefore, it is desirable to use a transmission means with low loss and less interference such as optical transmission.

Patent Document 1 discloses an information processing system that performs transmission using an optical interface between a CPU and a memory MEM, as shown in FIG. Here, a CPU, a bus control device (BUS CNTL), an electricity → light conversion unit (E → O), and a photoelectric conversion unit (O → E) are mounted on the host device (HOST). In the bus control device, the write data from the CPU is passed through a DC balance converter (DC-ENC), converted into serial data by a multiplexer (MUX), and then a check bit is added by an ECC encoder (ECC-ENC). The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO). This write data is input to the photoelectric conversion unit (O → E) on the memory device (MEM BRD), and the error is corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS MEM CNTL) on the memory device. After that, the data is converted into parallel data by a demultiplexer (DMUX) and then written to a memory (MEM).

Conversely, read data read from the memory is error-corrected by the ECC decoder (ECC-DEC) of the bus controller (BUS MEM CNTL) on the memory device, and then converted to serial data by the multiplexer (MUX) The electrical-to-optical conversion is performed, and the optical signal is output to the optical bus (OPIO). This read data is input to the photoelectric conversion unit (O → E) on the host device (HOST), error-corrected by the ECC decoder (ECC-DEC) on the bus control device (BUS CNTL), and then demultiplexer ( DMUX) is converted into parallel data, and then read through the DC balance inverse converter (DC-DEC) to the CPU.

Patent Document 2 describes an example in which parallel data transmission is performed between a memory module in which a plurality of memory chips are arranged and a CPU in order to further improve the data transfer speed using such an optical interface. As shown in FIG. 30A, a plurality of memory chips (MEMIC) are arranged on a memory module substrate (MEMMOD), and as shown in FIG. 30B, these are an optical bus (OPIO), an input / output adapter ( Sends and receives data to and from the memory controller (MEM CNTL) via IOADPT. A converter (CONV) that performs parallel / serial conversion of data, an optical-electrical signal conversion circuit (OE), an address buffer (CAB), and a clock driver (CKD) are arranged on the memory module. In this configuration, the clock (LCLK) of the optical signal is supplied to the memory chip, converter, and address buffer in the module by the clock driver (CKD), and data transmission of each chip is performed in synchronization with LCLK.

JP 2007-52714 A International Publication No. WO99 / 00734

In order to achieve a data rate of 1 TB / s between a multi-core system LSI or microprocessor and DRAM, as described above, the data rate of the signal line by one optical interface is increased to 32 Gbps. Must be a 64-bit configuration and 4 modules must be operated in parallel. According to the method shown in Patent Document 2, it is necessary to synchronize the timing of a large number of bits output from a plurality of chips with respect to a single clock within the module. However, when the data rate is 32 Gbps, one bit is set. Since the transmission time is shortened to about 30 ps, it is very difficult to achieve such synchronization.

The circuit delay for each signal generally differs depending on device variations and circuit placement locations on the chip. In order to synchronize such signals, it is necessary to add a variable delay circuit to each signal and change the delay amount so that the rising timing of the signal matches the rising timing of the clock. However, since even a wiring delay on a module of about 10 cm is several tens of ps, it is difficult to synchronize signal lines having a period of about 30 ps.

Therefore, an object of the present invention is to mount a plurality of memory chips, connect a plurality of signal lines output from the memory chip to an optical memory bus connected to a system LSI or CPU by an optical interface, and synchronize each signal line. It is to provide a memory module capable of speeding up to several tens of Gbps and stably transmitting data.

Among the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

In a memory module equipped with a plurality of DRAM chips and a plurality of interface chips corresponding to each chip, each DRAM chip is divided into a plurality of DRAM cores, and the interface chip is divided into interface cores corresponding to each DRAM core. The DRAM core transmits / receives a command / address signal and a data signal to / from a corresponding memory controller core using a single optical interface via a corresponding interface chip.

The command address signal and data signal include clock phase information. In the interface core corresponding to each DRAM core, the clock recovery circuit recovers the clock from the command address signal and data signal, In addition to receiving an address and data, each DRAM core operates at an independent timing by this clock.

Of the inventions disclosed in this application, the processing performance of the system can be enhanced by simply explaining the effects obtained by the representative embodiments.

It is a figure which shows the structure of the optical interface utilization many core DRAM module of this invention. It is a timing diagram of data transmission / reception of the optical interface utilization many core DRAM module of the present invention. It is a figure which shows the connection relation of the memory controller block in a CPU chip, and the DRAM chip in a DRAM module. It is a figure which shows the connection relation of the memory controller core in a CPU chip, and the DRAM core in a DRAM chip. FIG. 3 is a configuration diagram showing a plurality of DRAM cores in a DRAM chip and an interface core in an interface chip stacked thereon. It is a block diagram which shows the example which laminated | stacked the several DRAM chip and the interface chip. It is a figure which shows a part of (a) sectional drawing and (b) top view of an optical bus and DRAM module. It is a block diagram which shows the example of a DRAM side interface core. It is a waveform which shows the operation | movement at the time of the command input of DRAM side interface core. It is a waveform which shows the operation | movement at the time of read of DRAM side interface core. It is a waveform which shows the operation | movement at the time of writing of the DRAM side interface core. It is a block diagram which shows the example of a CPU side interface core. It is a block diagram which shows the example at the time of dividing | segmenting a DRAM side interface chip into an optical interface chip and an electric serial interface chip. It is a block diagram which shows the example of a DRAM chip with an electrical serial interface circuit, and an optical interface chip. It is a block diagram which shows the example of the DRAM chip of many core structure. FIG. 16 is a diagram illustrating an internal configuration example of one DRAM core disposed in the DRAM chip of FIG. 15. FIG. 20 is a diagram showing through via input / output circuits used in the DRAM core of FIG. 16 and the interface core of FIG. 19. It is a figure which shows the operation | movement waveform of the input-output circuit for through-vias of FIG. It is a block diagram which shows the structural example of the interface chip by the side of DRAM. It is a block diagram which shows the structural example of the memory bank of DRAM. FIG. 21 is a circuit diagram showing a connection example of a memory array, a sub word driver column, and a sense amplifier column used in the memory bank of FIG. 20. FIG. 21 is a circuit diagram showing an example (open bit line system) of a memory array used in the memory bank of FIG. 20. FIG. 21 is a circuit diagram illustrating a configuration example of a sense amplifier used in the memory bank of FIG. 20. FIG. 21 is a circuit diagram showing a configuration example of a sub word driver used in the memory bank of FIG. 20. FIG. 21 is a circuit diagram illustrating a configuration example of a cross area used in the memory bank of FIG. 20. 1 is a configuration diagram of an optical bus, a CPU chip, and a DRAM module using a wavelength multiplexing system. It is sectional drawing of the optical bus using a wavelength multiplexing system. It is a block diagram of the CPU side interface core using a wavelength division multiplexing system. It is a block diagram which shows the example of the memory using the conventional optical bus. It is a block diagram which shows the example of the memory module using the conventional optical bus.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawings, the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate. Further, in the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally.

Note that the memory module of the present embodiment described below uses a plurality of bit width optical interfaces between a system LSI or CPU chip having a plurality of CPU cores and a dynamic random access memory (DRAM). The memory core is divided into a plurality of memory cores that can communicate independently and can be operated independently, and the memory core corresponding to each CPU core uses a 1-bit optical interface to perform data input / output with an independent clock. This technology is useful when the CPU or system LSI with the configuration is connected to the DRAM via an optical interface. Not only this, but also when a logic chip such as an ASIC or DSP and a memory such as SRAM or FLASH are connected via an optical interface. Applicable.

FIG. 1 is a conceptual diagram showing a configuration example of a plurality of DRAM chips (DRAMIC0-7) and interface chips (IFDIC0-7) in a memory module according to an embodiment of the present invention. The DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via. Here, the DRAM chip includes four DRAM cores (DRAMC0-3), the interface chip includes four interface cores (IFDC0-3), and each DRAM core uses an interface core having a corresponding number. The CPU transmits and receives data. Each DRAM core has a clock (CK), a command address signal (CAI), and a data signal (DQI) independently. Each DRAM core accepts an input of a command address at an independent timing, and inputs and outputs data. Is possible.

Each interface core has a corresponding memory controller (described later) via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). Perform data transfer. This module shows an example of an optical bus (OPIO) in which eight DRAM chips each having four DRAM cores are mounted and which is composed of 32 command / address optical waveguides and data optical waveguides.

The operation of the memory module will be described by taking the DRAM core (DRAMC0) on the DRAM chip (DRAMIC0) and the interface core (IFDC0) on the IFD chip (IFDIC0) as examples, but other DRAM cores and interface cores also perform the same operation. . First, a command and an address are input from the memory controller via an optical waveguide corresponding to the command / address signal (CA0). These are multi-bit data on the CPU core, but are converted to serial data and transmitted to the command / address optical terminal (CA) on the interface core (IFDC0) for transmission as a single optical signal. The After this optical signal is converted into an electrical signal, a command / address clock (CKA) is taken out by a clock recovery circuit (CDR), and a command / address signal (CAI) converted into parallel data is taken in by using the command / address clock (CKA). . The command address clock is input to the frequency divider (DIV), and a DRAM clock (CK) having a long period is generated. The command / address signal is input to the DRAM core (DRAMC0) by the DRAM clock, and operations such as writing and reading are started.

In the read operation, parallel data (DQI) read from the DRAM core is input to the interface core (IFDC0) by the DRAM clock, and serial data is synchronized with the command / address clock (CKA) in the clock recovery circuit (CDR). Is converted into an optical signal, output to the optical waveguide corresponding to the data optical signal (DQ0), and transmitted to the memory controller.

In the case of a write operation, write data is input from the memory controller using an optical waveguide corresponding to the data signal (DQ0). These are multi-bit data on the CPU core, but are converted to serial data and transmitted to the data input / output terminal (DQ) on the interface core (IFDC0) for transmission as a single optical signal. The After this optical signal is converted into an electrical signal, the clock recovery circuit (CDR) takes out the data clock (CKD) and uses it to take in the data signal (DQI) converted into parallel data. This data is input to the DRAM core (DRAMC0) by the DRAM clock (CK), and a write operation is performed.

With this configuration, the memory controller can perform data transmission independently of many DRAM cores. As will be described later, in a large number of current systems, the CPU side also has a many-core configuration, and this memory module can process independent memory accesses from a large number of cores at the same time, which can greatly improve the calculation performance. In addition, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.

FIG. 2 shows a timing diagram of data transmission / reception in the DRAM chip and the interface chip. Here, data transmission / reception of the DRAM core (DRAMC0, 1) on the DRAM chip (DRAMIC0) and the DRAM core (DRAMC3) on the DRAM chip (DRAMIC7) is shown.

In the DRAM core (DRAMC0) on the DRAM chip (DRAMIC0), first, an activation command (ACT) and a row address (AX) are input as optical serial signals to CA0 of the corresponding interface core. From this, a command / address clock (CKA) is taken out by a clock recovery circuit (CDR) and converted into a parallel signal (CAI). The activation command and the row address are transmitted to the DRAM core in synchronization with the DRAM clock (CK) generated by dividing the command / address clock, and the operation of the DRAM is started. Subsequently, a read command (READ) and a column address (AY) are input to CA0 and similarly transmitted to the DRAM core, and read data is read out. The data signal DQI output from the DRAM core is output as the data optical signal DQ0 from the interface core in synchronization with CKA.

In the DRAM core 1 on the DRAM chip 0, first, an activation command (ACT) and a row address (AX) are input as serial signals of optical signals to the corresponding interface core CA1, and transmitted to the DRAM core in the same manner as above. Thus, the operation of the DRAM is started. Subsequently, a write command (WRITE) and a column address (AY) are input to CA1. Write data DQ1 is input as an optical signal to the interface core. From this, a data clock (CKD) is taken out by a clock recovery circuit (CDR) and converted into a parallel data signal (DQI). These command / column address and data are transmitted to the memory core, and a write operation is performed. As shown in the figure, the operation timing and clock of the DRAM core 1 are independent of those of the DRAM core 0.

The example in which the activate command and the read command are executed in the DRAM core 3 on the DRAM chip 7 as well as the DRAM core 0 on the DRAM chip 0 has been shown. It operates at completely independent timing without synchronization.

FIG. 3 is a diagram showing a state in which two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO). A plurality of DRAM chips (DRAMIC0-N) and interface chips (IFDIC0-N) are arranged on the DRAM module. The DRAM chip and the interface chip are stacked and mounted using a three-dimensional connection technique such as a through via. A plurality of CPU cores (CPUC0-M) and a plurality of memory controller blocks (MCB0-N) are arranged on the CPU. A signal output from the memory controller block is connected to an optical bus via an interface chip (IFCIC).

Here, each memory controller block (MCB0-N) transmits and receives data only to and from the corresponding DRAM chip on each DRAM module. For example, if a memory access requested from a certain CPU core is received by a memory controller core included in the memory controller block 0, this memory controller core is the DRAM core included in the DRAM chip 0 on the DRAM module 0 or the DRAM module 1. To read and write data. In this way, since a plurality of memory controller cores can read and write data with the DRAM core at independent timing, it is not necessary to synchronize between different signals on the optical bus, and high-speed transmission is possible. It becomes possible.

FIG. 4 is a diagram showing a connection relationship between the memory controller block (MCB0) on the CPU chip (CPUIC) and the DRAM chip (DRAMIC0) on the DRAM module (DRAMMOD0). Here, four DRAM cores (DRAMC0-3) are arranged in the DRAM chip, and four interface cores (IFDC) are arranged in the interface chip (IFDIC0). In addition, a control circuit (CNTL) and four memory controller cores (MCC0-3) are arranged in the memory controller block (MCB0), and four interface cores (IFCC) are arranged on the interface chip (IFCIC). .

The DRAM core transmits / receives data to / from the memory controller core using the corresponding interface core. Each DRAM core has a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI) independently. Each DRAM core accepts an input of a command address at an independent timing and inputs data. Output is possible.

Each interface core transfers data to and from a corresponding memory controller via an optical waveguide (WG) corresponding to one command / address optical signal (CA) and an optical waveguide corresponding to one data optical signal (DQ). I do.

The operation of this memory module will be described by taking the DRAM core 0 on the DRAM chip 0 and the MC core 0 on the CPU chip as an example. A case where a memory access input from a certain CPU core on the CPU chip to the memory controller block 0 is processed by the MC core 0 by the control circuit is shown. The MC core 0 inputs a multi-bit command / address signal (CAI) for the DRAM core 0 and a CPU clock (CKC) to the interface core (IFCC). On the interface core, the input CPU clock is multiplied by a PLL to generate a high-speed command / address clock (CKA). In the clock recovery circuit CDR, the command address (CAI) is converted into serial data in synchronization with CKA, then converted into an optical signal, and output from the command / address optical terminal (CAP) to the optical waveguide (CA0).

This command / address signal is input as serial data to the command / address input terminal (CA) on the interface core (IFDC0). As described above, in the read operation, the data read from the DRAM core is converted into serial data. After the conversion, it is converted into an optical signal and output to the optical waveguide corresponding to the data signal (DQ0). This data is input to an interface core (IFCC) on an interface chip on the CPU side, converted from an optical signal to an electrical signal, and then a data clock (CKD) is taken out and used by a clock recovery circuit (CDR). The data signal (DQI) converted into parallel data is taken in. This data is transmitted to the memory controller core (MCC0) by the CPU clock (CKC).

Conversely, in the case of a write operation, a parallel data signal (DQI) is input from MCC0 to IFCC in synchronization with the memory controller clock, and serial data is synchronized with the command / address clock (CKA) in the clock recovery circuit (CDR). Is converted to an optical signal, output to the optical waveguide corresponding to the data signal (DQ0), and transmitted to the interface core (IFDC) on the DRAM-side interface chip. This data is transmitted to the DRAM core as described above, and writing is performed.

As described above, one memory controller core and one DRAM core perform serial transmission using one command / address signal and one data signal, so that the memory controller is independent of many DRAM cores. Data transmission can be performed. Therefore, when connected to a CPU having a many-core configuration, the present memory module can simultaneously process independent memory accesses from a large number of CPU cores, so that the calculation performance can be greatly improved. In addition, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each DRAM core operates at an independent timing. There is no need to synchronize, and high-speed transmission of several tens of Gbps can be stably performed.

Also, each core can operate in parallel with other cores. That is, each channel can transmit and receive data regardless of the state of other cores. In this way, using the optical interface, each CPU core and DRAM core can operate in parallel, that is, by having a channel that can operate regardless of the state of other CPU cores and DRAM cores. In addition to improving the bandwidth of transmission and reception, it is possible to operate at any timing, unlike the case where the channel is shared, so an arbitration and synchronization mechanism is not required, and the information processing system There is an advantage that the hardware configuration and the software configuration are simplified.

FIG. 5 shows a block diagram when a DRAM chip (DRAMIC0), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked by using a through via (VIA). Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip. In this example, the DRAM chip includes four DRAM cores (DRAMC0-3), and the interface chip includes four interface cores (IFDC0-3). The DRAM core transmits / receives data to / from the CPU using an interface core having a corresponding number.

In addition to the memory array (ARY), each DRAM core can independently input / output a DRAM clock (CK), a command / address signal (CAI), and a data signal (DQI), a clock terminal (CKP), a command / address terminal ( Data is transmitted to and received from the interface core via a data input / output terminal (DQIP). It is possible to input and output data individually by receiving command and address inputs at independent timings.

The interface core includes a command / address optical terminal (CAP) and a data optical terminal (DQP) for inputting an optical signal from an optical waveguide through a printed circuit board, and a clock terminal (CKP) and a command / address terminal ( Data is transmitted to and received from the DRAM core via the CAIP) and data terminal (DQIP). The optical interface circuit (OPIF) performs conversion from an optical signal to an electrical signal and conversion from an electrical signal to an optical signal. The clock recovery circuit (CDR) performs clock extraction from the command / address signal and data signal, data capture, conversion from serial data to parallel data, and conversion from parallel data to serial data. The frequency divider (DIV) divides the clock CKA extracted from the command / address signal and generates a DRAM clock (CK) having a low frequency. The power of the DRAM core and interface core is supplied from the printed circuit board to the power supply pad (VSP) in each core through a through via.

By laminating the DRAM chip and the interface chip using the through vias in this way, the number of signal lines between the chips can be increased, thereby dividing the DRAM and the interface chip into a plurality of cores, which are independent of each other. It is possible to operate with a clock.

FIG. 6 shows a block diagram when four DRAM chips (DRAMIC0-3), an interface chip (IFDIC), and a printed circuit board (BASE) are stacked using through vias (VIA). Through-vias can have an interface with chips stacked above and below a specific chip by vias penetrating the chip. In this example, only one DRAM core (DRAMC0) of the plurality of DRAM cores mounted on the DRAM chip is shown, and only one interface core (IFDC0) of the plurality of interface cores mounted on the interface chip is shown. However, other DRAM cores are similarly connected to the interface core. The DRAM C0 included on the four chips uses IFDC0 to transmit and receive data to and from the CPU as in the case of FIG.

The difference from the case of FIG. 5 is that a command decoder (CDC) is provided on the interface core, and a command / address signal (CAI) is sent to one of a plurality of stacked chips in accordance with an address from the memory controller core. ). At this time, in order to select the stacked chips, each chip has an independent chip selection signal or an ID number is assigned to each chip. With this configuration, there is an advantage that the capacity of the DRAM stacked on the interface chip can be increased, and a large-capacity memory system can be realized without increasing the number of modules and the board area.

FIG. 7 shows the structure of an optical interface / memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide. A sectional view is shown in (a), and a part of the top view is shown in (b). The DRAM module is configured by laminating a plurality of DRAM chips (DRAMIC) and an interface chip (IFDIC) on a printed circuit board (BASE). The CPU module (CPUMOD) is configured by stacking a CPU chip (CPUIC) and an interface chip (IFCIC) on a printed circuit board (BASE). These modules are arranged on a board substrate (SUB). A plurality of optical waveguides (WG) are wired in the board substrate, and optical signals are transmitted between corresponding terminals of the CPU module and the DRAM module. Can be transmitted.

As shown in (a), an optical coupler (COUP) is provided at the lower part of each DRAM module, and an optical signal input from the CPU can be branched from the optical waveguide at a certain rate and guided to the module. . The end portion of the optical waveguide is subjected to antireflection coating (AR), and almost 100% is transmitted without reflection of light. As a result, no signal reflection or interference occurs on the optical waveguide, and a stable signal with less waveform distortion can be transmitted. When the optical signal is bent, a mirror structure (ML) having a surface inclined by 45 degrees with respect to the light traveling direction is created and reflected by 90 degrees. With this configuration, data can be transmitted and received between a plurality of memory modules and a CPU with a single waveguide, so that the number of optical waveguides can be reduced, and the size and cost of the board can be reduced. .

FIG. 8 shows the configuration of the interface core (IFDC) on the memory side interface chip (IFDIC), and its operation will be described with reference to the waveforms in FIG. The command / address optical signal (CA) is input from the memory controller to the command / address optical terminal (CAP) using the optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF1), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the command / address clock (CKA) is taken out in the PLL in the clock recovery circuit (CDR1). Command / address serial data (CAIS) latched by CKA is parallelized by a demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. This is decoded by an 8 / 10B decoder (8 / 10BDEC) to convert it into a command / address signal (CAI) of parallel data and transmitted to the DRAM chip via an interface terminal (CAIP) of an electric signal. . CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip selection signal (CSB), reset signal ( RESETB). FIG. 9 shows an example in which an activate command (ACT) and a row address (AX) are transmitted first, followed by a read command (READ) and a column address (AY). The command / address clock is input to the frequency dividing circuit (DIV) to generate a DRAM clock (CK) having a long period, and this is also transmitted to the DRAM chip via the clock terminal (CKP). The command / address signal is input to the DRAM core by the DRAM clock, and operations such as writing and reading are started.

In the case of a read operation, a parallel data signal (DQI) read from the DRAM core is input to the electrical signal interface terminal (DQIP) of the interface core (IFDC) by the DRAM clock. DQIP includes a DQ terminal (DQI0-3) and a data mask (DM). The parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address It is converted into serial output data (DOS) by a multiplexer (MUX) and a DQ latch in synchronization with the clock (CKA). Thereafter, in the optical interface (OPIF2), the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and the light is transmitted from the data optical terminal (DQP) as shown in FIG. It is output to the waveguide and transmitted to the memory controller.

In the write operation, an optical signal (DQ) corresponding to the write data is input from the memory controller to the data optical terminal (DQP) using the optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2). Serial input data (DIS) taken in by the DQ latch by CKD is parallelized by the demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. This is decoded by an 8 / 10B decoder (8 / 10BDEC) to generate a write data signal (DQI) converted into parallel data, and through an electrical signal interface terminal (DQIP) as shown in FIG. And transmitted to the DRAM chip.

With this configuration, each interface core extracts the clock from the command / address signal and the data signal itself, performs data transmission at its own timing, and each DRAM core operates at independent timing. It is not necessary to synchronize between them, and high-speed transmission of several tens of Gbps can be stably performed.

FIG. 12 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC). A command / address signal (CAI) of parallel data is input from the memory controller core to the command / address terminal (CAIP) by the CPU clock (CKC). CAI includes address (A0-A10), bank address (BA0-BA1), row address strobe signal (RASB), column address strobe signal (CASB), write enable (WEB), chip select (CS), and reset signal (RESETB). ) Is included.

The parallel data is first encoded by the 8 / 10B encoder (8 / 10BENC) in the clock recovery circuit (CDR3) so that the time during which the data does not change when serialized does not continue for a certain time or longer, and then the CKC Is converted into command / address serial data (CAIS) by a multiplexer (MUX) and a latch in synchronization with a high-speed command / address clock (CKA) multiplied by PLL. Then, in the optical interface (OPIF3), the light output from the laser (LD) is converted into a command / address optical signal (CA) by a modulator (MOD), and the command / address optical terminal (CAP) is converted into an optical waveguide. Is output and transmitted to the DRAM module.

In the case of a write operation, a parallel data signal (DQI) transmitted from the memory controller core is input to the data terminal (DQIP) of the interface core (IFCC) by the CPU clock (CKC). DQIP includes a DQ terminal (DQI0-3) and a data mask (DM). The parallel data is encoded by the 8 / 10B encoder (8 / 10BENC) so that the time during which the data does not change when serialized in the clock recovery circuit (CDR2) does not continue for a predetermined time or longer, and then the command address In synchronization with the clock (CKA), the data is converted into serial output data (DOS) by a multiplexer (MUX) and a latch. Then, in the optical interface (OPIF2), the light output from the laser (LD) is converted into the data optical signal (DQ) by the modulator (MOD), and output from the data optical terminal (DQP) to the optical waveguide, and the DRAM Transmitted to the module.

In the case of a read operation, an optical signal (DQ) corresponding to the read data is input from the DRAM module to the data optical terminal (DQP) using an optical waveguide. This optical signal is converted into a current signal by a photodetector (PD) in an optical interface circuit (OPIF2), and then converted into a voltage signal by a transimpedance amplifier (TIA). From this signal, the data clock (CKD) is taken out in the PLL in the clock recovery circuit (CDR2). Serial input data (DIS) fetched by the CKD latch is parallelized by the demultiplexer (DMUX). The transmitted serial data is 8 / 10B encoded so that the time during which the data does not change does not continue for a certain time or longer on the memory controller side. By decoding this data with an 8 / 10B decoder (8 / 10BDEC), read data (DQI) converted into parallel data is generated and transmitted to the DRAM chip via the data terminal (DQIP).

With this configuration, each interface core extracts the clock from the command / address signal and the data signal itself, transmits data at its own timing, and each memory controller core operates at an independent timing. There is no need to synchronize the lines, and high-speed transmission of several tens of Gbps can be stably performed.

FIG. 13 shows a configuration in the case where the memory side interface chip (IFDIC) shown in FIG. 8 is divided into an optical interface chip (IFD-OIC) and an electrical interface chip (IFD-EIC). A plurality of optical interface cores (IFD-OC) are arranged in the optical interface chip, and a plurality of electric interface cores (IFD-EC) are arranged in the electric interface chip, and one set is shown in the figure. The operation of the circuit block included in each core is the same as that in FIG. 8, but for the command / address signal, the output of the optical interface circuit (OPIF1) in the optical interface core is sent via the command / address serial terminal (CASP). To the through via (VIA), and this is input to the clock recovery circuit (CDR1) in the electrical interface core. As for the data signal, the input signal (DIS) and output signal (DOS) of the clock recovery circuit in the electrical interface core are output to the through via via the serial input data terminal (DSP) and the serial output data terminal (QSP). The optical interface circuit (OPIF2) in the optical interface core is connected. Thus, by dividing the interface chip, the characteristics of the optical element are improved using a compound semiconductor substrate such as GaAs or InP for the optical interface chip, and a CMOS logic circuit is mounted using the Si substrate for the electrical interface chip. As a result, it is possible to increase the degree of integration of electronic devices and reduce power consumption.

FIG. 14 shows an example in which the electrical interface core (IFD-EC) of FIG. 13 is integrated on a DRAM chip. A plurality of DRAM cores and an electrical interface core are mounted on the DRAM chip, but only one set is shown here. The operation of each circuit block is the same as in FIG. In this case, the characteristics of the optical element can be improved by using a compound semiconductor substrate such as GaAs or InP for the optical interface chip as in FIG. 13, and the DRAM chip and the optical interface chip can be directly connected. Since there is no need to increase the number of chips, the cost of the package can be reduced.

FIG. 15 is a plan view showing the configuration of a DRAM chip (DRAMIC). Common to a plurality of DRAM cores such as a plurality of DRAM cores (MEM0 to 7 (corresponding to DRAMC in FIG. 1 and the like; the same applies hereinafter)), a transmission / reception circuit, a power generation circuit, and the like in the chip. There are provided circuits (hereinafter referred to as a common circuit (COMC)), and a bus (BUS) is wired between them. Here, by providing the power supply generation circuit in common, it is possible to design a circuit with a small area.

Here, an example is shown in which 8 DRAM cores of 2 rows × 4 columns are arranged. If the size of the area where each memory core is arranged is about 3 mm square, the entire DRAM chip is about 6 mm × 12 mm square. This is a value close to the chip size of DRAM chips that are currently mass-produced, which is advantageous in that it can achieve the same manufacturing yield and price as before.

In the DRAM core, a command / address terminal (CAIP) and a data terminal (DQIP) are arranged on the second side located on the chip center side. With this arrangement, command / address terminals and data terminals can be concentrated in the center of the chip. For this reason, even when the shapes of the DRAM chip and the SoC chip are relatively different, it is easy to stack the command / address terminals and the data terminals together.

FIG. 16 is a plan view showing an internal configuration example of one DRAM core (MEM). A command / address terminal (CAIP), a data terminal (DQIP), and a clock terminal (CKP) are arranged on one side of the core. A plurality of memory banks (BANK) are arranged, and a read / write circuit (R / W AMP) is arranged between the memory bank and the data terminal. Defect relief fuses (FUSE) are arranged on both sides of the core.

Here, the command signals are a reset signal, a row address strobe, a column address strobe, a write enable and a chip select signal, and input / output terminals corresponding to these are provided in the command / address terminal area. Each input / output terminal is provided with a TSV input / output circuit to receive a command signal. Similarly, the address signal is also input via a TSV input / output circuit provided for each terminal corresponding to the address signal (A0-A10) or the bank address signal (BA0-1). The command / address control circuit determines the operation mode of the DRAM chip, predecodes the address, controls the operation timing, and the like.

The data signal is input / output to / from the data terminal (DQIP) via the TSV input / output circuit. Here, the data signal includes a data input / output signal (DQ0-3) and a data mask signal (DML). By having a DRAM clock (CK) for each DRAM core, a DRAM chip in which a plurality of DRAM cores can operate in parallel at independent timings can be realized.

Here, the command / address terminal of the interface chip is arranged vertically below the printed circuit board (PCB) of the command / address terminal (CAIP) of the DRAM chip, and the printed circuit board (PCB) of the data terminal (DQIP) of the DRAM chip. On the other hand, the interface chip (IFDIC) and the DRAM chip (DRAMIC) are stacked and mounted so that the data terminals of the interface chip are arranged vertically below. With this configuration, the data transmission distance between chips can be shortened, and the data transfer efficiency is improved.

In the memory bank (BANK), as shown in FIG. 16, a memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA) and a sub word driver array (SWDA) are arranged around it. Be placed. A column decoder (YDEC) is arranged in parallel with the sense amplifier column on the outer periphery of the memory bank, a row decoder (XDEC) is arranged in parallel with the sub word driver column (SWDA), and an array control circuit is arranged in addition. By having a defect relief fuse (FUSE) for each DRAM core and replacing a defective memory cell with a redundant memory cell in the same DRAM core, it is not necessary to send a relief judgment signal out of the core, thereby shortening the access time. can do.

In the configuration shown in FIG. 16, the number of bits of the data input / output circuit (DQ) is 4, but as an example, when a DRAM core is created as a DDR2-SDRAM base, 16 bits of data are paralleled in the memory array. The data is read out, converted into parallel-serial by a 4-to-1 multiplexer, and then output outside the chip. The DRAM core is based on DDR3-SDRAM or other DRAM, and the number of address terminals and data pins can be changed.

FIG. 17 shows a TSV input / output circuit (TSVC) used in the DRAM core of FIG. 16 and the CPU core of FIG. This circuit includes an output circuit (OBC3) and an input circuit (IBC3), and a plurality of such circuits are provided on a DRAM chip (DRAMIC) and an interface chip (IFDIC). A through via pad (PAD) is provided at the ND terminal of the input / output circuit on the DRAM chip, and a similar pad is also provided at the NS terminal of the input / output circuit on the interface chip.

When data is transmitted from the DRAM chip to the interface chip, the output circuit (OBC3) is activated on the DRAM chip to cause a potential change in ND. Since ND and NS are connected by the through via, this potential change is directly transmitted to the terminal NS on the interface chip side, amplified by the input circuit (IBC3), and reproduced as digital data. On the other hand, when data is transmitted from the interface chip to the DRAM chip, the output circuit is activated on the interface chip to generate a potential change in NS, and a voltage is applied to a terminal ND on the DRAM side connected to NS via. Is generated. This voltage is amplified by an input circuit on the DRAM side and reproduced into digital data.

In FIG. 18, the operation will be described by paying attention to a set of TSV input / output circuits (TSVC) for receiving data. In the output circuit (OBC3), the MOS transistors MP5 and MN5 are turned off when the output enable signal (OED) is in the inactive state (VSS). When OED is activated and becomes VDD, MP5 or MN5 is turned on corresponding to the data output terminal (DOD). When DOD is VSS, MN5 is turned on and ND is driven to VSS. On the interface chip, the voltage of NS is pulled toward VSS. This signal is amplified by the amplifier circuit (AMP), the latch signal (LTS) is activated, the VSS level data is latched by the latch circuit (LTC), and is output to the data input terminal (DIS). When DOD is VDD, signal transitions having opposite polarities occur, and a VDD level signal is output to DIS. When data transmission / reception is performed between the DRAM core and the interface core using the through via using this method, there is an advantage that the number of signal lines can be increased to a large number. The through via method is characterized in that the voltage of VDD or VSS output from the output circuit is input to the input circuit, so that the circuit is simple and the reliability of signal transmission is high.

FIG. 19 is a plan view showing a configuration of an interface chip chip (IFDIC). In the chip, a plurality of interface cores (IFDC0 to IFDC7) capable of operating in parallel, a circuit commonly provided for a plurality of DRAM cores such as a transmission / reception circuit and a power generation circuit (hereinafter referred to as a common circuit (COMC)). ) And a bus (BUS) is wired between them. Here, by providing the power supply generation circuit in common, it is possible to design a circuit with a small area.

Here, an example in which 8 interface cores of 2 rows × 4 columns are arranged is shown. In the interface core, a command / address input terminal (CAIP) and a data input / output terminal (DQIP) are arranged on the second side located on the chip center side. With this arrangement, the command / address input terminals and the data input / output terminals can be concentrated in the center of the chip. For this reason, even when the shapes of the DRAM chip and the interface chip are relatively different, it is easy to stack the command / address input terminals and the data input / output terminals together.

FIG. 20 shows a configuration example inside the memory bank (BANK) in the DRAM core of FIG. A memory array (ARY) arranged in a plurality of arrays is arranged, and a sense amplifier array (SAA), a sub word driver array (SWDA), and a cross area (XP) are arranged around the memory array (ARY). In addition, a column decoder (YDEC) and a main amplifier column are arranged on the outer periphery of the memory bank (BANK) in parallel with the sense amplifier column, and a row decoder (XDEC) and an array control circuit (ACC) in parallel with the sub word driver column. Is placed.

FIG. 21 is a plan view showing an example of a detailed arrangement relationship between the sense amplifier row and the sub word driver row in the DRAM core of FIG. The sense amplifiers (SA) in the sense amplifier array (SAA) are alternately arranged on the left and right with respect to the memory array (ARY), and are commonly connected to the bit line pairs (BLT / BLB) in the left and right memory arrays. Similarly, the sub word drivers (SWD) in the sub word driver array (SWDA) are alternately arranged above and below the memory array and commonly connected to the word lines (WL) in the upper and lower memory arrays. By arranging in this way, the pitch between the sense amplifiers in the sense amplifier row can be increased to twice the pitch between the bit lines in the memory array, and between the sub word drivers in the sub word driver row. Can be increased to twice the pitch between the word lines in the memory array, so that miniaturization is facilitated. A local I / O line (LIO) is arranged in the sense amplifier row, and the local I / O line is connected to the main I / O line (MIO) via the switch (SW) in the cross area (XP). .

FIG. 22 is a circuit diagram showing an example of the configuration of the memory array in the DRAM core of FIG. The memory array (ARY) is composed of a plurality of memory cells (MC). Each memory cell is a DRAM memory cell, and is composed of one MOS transistor (memory cell transistor) and one capacitor (Cs). One of the source and the drain of the memory cell transistor is connected to the bit line (BLT) or the reference bit line (BLB), the other of the source and the drain is connected to the storage node (SN), and the gate is the word line (WL). It is connected to the.

One terminal of the capacitor (Cs) is connected to the storage node SN, and the other terminal is connected to the common plate (PL). The bit line and the reference bit line function as a bit line pair (complementary bit line) and are connected to the same sense amplifier. The sense amplifier rows are alternately arranged on the left and right with respect to the memory array, are connected in common to the bit line pairs in the left and right memory arrays, and are shared by both. Accordingly, in each sense amplifier row, adjacent sense amplifiers are arranged with a space corresponding to one bit line pair. By adopting such an arrangement, the pitch between the sense amplifiers is relaxed, so that the layout becomes easy and miniaturization becomes possible. In this figure, an open bit line type array is used, and memory cells are arranged at the intersections of all word lines and bit lines. This has the effect of reducing the memory cell size.

FIG. 23 is a circuit diagram showing an example of a sense amplifier in the DRAM core of FIG. The sense amplifier (SA) includes a precharge circuit (PCC), a cross couple amplifier (CC), and a read / write port (IOP). The precharge circuit equalizes the paired bit lines (BLT / BLB) when the bit line precharge signal (BLEQ) is activated, and precharges the bit line precharge level (VBLR). Usually, the bit line voltage (VDL) is set to the same level as the power supply voltage (VCC) from the outside of the chip or a level obtained by stepping down the same. The bit line precharge level is set to this midpoint (VDL / 2). In the cross-coupled amplifier (CC), after a minute read signal from the memory cell is generated on the bit line, the P-side common source line (CSP) is set to the bit line voltage and the N-side common source line (CSN) is set to the ground potential. This circuit is driven to (VSS), amplifies the higher voltage of complementary bit lines to VDL, amplifies the lower voltage to VSS, and latches the amplified voltage. The read / write port (IOP) is a circuit that connects the local I / O line (LIOT / B) and the bit line pair when the column selection line (YS) is activated. The local I / O line is held at the precharge level during standby in order to prevent current consumption in the non-selected sense amplifier array.

FIG. 24 is a circuit diagram showing an example of the configuration of the sub-word driver string in the DRAM core of FIG. The sub word driver array (SWDA) is composed of a plurality of sub word drivers (SWD). As shown in FIG. 21, the sub word driver column is arranged around the memory array. The sub word driver drives the word lines (WL) in the memory arrays arranged above and below. Further, since the sub word driver columns are alternately arranged with respect to the memory array, every other word line in the memory array is connected to the upper and lower sub word drivers.

The sub word driver is composed of two N channel MOS transistors and one P channel MOS transistor. One N-channel MOS transistor has a gate connected to the main word line (MWLB), a drain connected to the word line, and a source connected to the voltage VKK. The other N-channel MOS transistor has a gate connected to a complementary sub word driver select line (FXB), a drain connected to a word line (WL), and a source connected to a voltage VKK. Here, VKK is a standby word line voltage, which is generated by a voltage generation circuit (VGC) and is a negative voltage lower than the ground potential (VSS).

In the P-channel MOS transistor, the main word line is connected to the gate, the word line is connected to the drain, and the sub word driver selection line (FX) is connected to the source. Four sets of sub word driver selection lines (FX0 to FX4) are wired on one sub word driver column, and one of the four sub word drivers selected by one main word line is selected to be one The word line is activated.

FIG. 25 is a circuit diagram showing an example of a cross area configuration in the DRAM core of FIG. The cross area (XP) includes a first local I / O line precharge circuit (LEQ1), a second local I / O line precharge circuit (LEQ2), a read / write gate (RGC), and a CS line driver ( CSD), CS line precharge circuit (SEQ), BLEQ signal driver (EQD), and FX line driver (FXD) are arranged.

The first local I / O line precharge circuit (LEQ1) precharges the local I / O line (LIO / LIOB) to VDL / 2 when the complementary precharge signal (BLEQB) is active. The second local I / O line precharge circuit (LEQ2) precharges the local I / O line (LIO / LIOB) with the peripheral circuit voltage (VCL) when the read equalize signal (REQB) is active. The read / write gate (RGC) is a circuit that connects a local I / O line (LIO / LIOB) and a main I / O line (MIO / MIOB) when a gate signal (TG / TGB) is activated. is there.

When the N-side sense amplifier enable signal (SAN) is active, the CS line driver (CSD) drives the N-side common source line (CSN) to the ground voltage (VSS), and the P-side sense amplifier enable signal (SAP1B). ) Is a circuit that drives the P-side common source to the power supply voltage (VSS level) when in the active state. The CS line precharge circuit (SEQ) is a circuit that precharges the P-side and N-side common source lines to VDL / 2 when a complementary precharge signal is activated. The BLEQ signal driver (EQD) receives a complementary signal (BLEQB) of the precharge signal (BLEQ) and outputs an inverted signal thereof. The FX line driver (FXD) receives the complementary sub word driver selection line (FXB) and outputs the inverted signal to the sub word driver line (FX).

FIG. 26 is a diagram showing a state where two DRAM modules (DRAMMOD0, 1) of the present invention and a CPU chip (CPUIC) are connected to an optical bus (OPIO). The difference from FIG. 3 is that when each memory controller block (MCB) transmits and receives data to and from the corresponding DRAM chip on each DRAM module, optical signals having different wavelengths are used for the respective DRAM modules. This is the point of performing multiplex transmission / reception.

For example, if a memory access requested from a certain CPU core is received by a memory controller core included in MCB0, this memory controller core uses an optical signal of wavelength λ0 to access DRAMIC0 on DRAMMOD0, and DRAMMOD1 When accessing the above DRAMIC0, an optical signal having a wavelength λ1 is used. Optical signals having wavelengths of λ0 and λ1 are multiplexed on the optical waveguide constituting the optical bus, and transmission and reception can be performed without interfering with each other at the same time. In this way, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.

FIG. 27 shows a cross-sectional view of an optical interface memory bus in which a memory module using an optical interface of the present invention and a CPU chip are connected by an optical waveguide. The difference from FIG. 7 is that the optical coupler / filter (COUP & FLT) at the bottom of each DRAM module receives an optical signal of a specific wavelength from an optical waveguide from an optical signal having a plurality of wavelengths (λ0, λ1) input from the CPU. It is a point that can be branched to a module and led to a module. In the DRAM module 0, the length of the optical coupler / filter is L0, and the distance from the optical waveguide is D0, so that only the optical signal having the wavelength λ0 is branched. In the DRAM module 1, the length of the optical coupler / filter is L1, and the distance from the optical waveguide is D1, so that only the optical signal having the wavelength λ1 is branched. By doing so, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so that the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.

FIG. 28 shows the configuration of the interface core (IFCC) on the CPU side interface chip (IFCIC) when performing wavelength multiplexing communication. The operation of the circuit blocks of the optical interfaces (OPIF2, OPIF3) and clock recovery circuits (CDR2, CDR3) is the same as that shown in FIG. As described above, the command address signal (CAI) of the electrical signals from CPU core 0 and CPU core 1 is converted into optical signals of wavelengths λ0 and λ1 by the clock recovery circuit (CDR3) and the optical interface (OPIF3), respectively. Then, they are multiplexed by a multiplexer (MIXW) and output by one optical interface terminal (CAP).

As for the write data, the write data of the electrical signals from the memory controller core 0 and the memory controller core 1 is the wavelength λ0, λ1 by the clock recovery circuit (CDR2) and the optical interface (OPIF2), respectively, as (DQIP) indicated earlier Are multiplexed by a multiplexer (MIXW), and output by one optical interface terminal (DQP). As for the read data, the read data input to one optical interface terminal (DQP) is divided into optical signals of wavelengths λ0 and λ1 by a demultiplexer (DIVW), and the optical interface (OPIF2) and clock recovery circuit ( The signals are converted into parallel electrical signals by the CDR 2) and input to the memory controller core 0 and the memory controller 1.

In this way, one memory controller core can simultaneously access the DRAM cores on a plurality of DRAM modules, so the data transfer speed can be increased without increasing the number of optical waveguides. It becomes possible.

As described above, the invention described in this embodiment is based on the data rate of the signal line per line using an optical interface in a memory module in which a plurality of multi-core DRAM chips are arranged. Can be improved to several tens of Gbps, and even when tens of signal lines are input / output from the memory module, stable data transmission is possible, which contributes to an improvement in system performance.

8 / 10BDEC: 8 / 10B decoder, 8 / 10BENC: 8 / 10B encoder, A: address, ACC: array control circuit, ACT: activate command, ADD: address signal, AMP: amplifier circuit, AR: non-reflective coating processing, ARY: memory array, AX: row address, AY: column address, BA: bank address, BANK: memory bank, BASE: printed circuit board, BC: bias circuit, BL, BLT, BLB: bit line, LEQ: bit line precharge Signal, BUS: bus, CA: command address optical signal, CAI: command address signal, CAP: command address optical terminal, CAIP: command address terminal, CAIS: command address serial data, CASB: column address strobe signal , CAS : Command address serial terminal, CBUS: Core bus, CC: Cross-coupled amplifier, CDC: Command decoder, CDR: Clock recovery circuit, CK: DRAM clock, CKA: Command address clock, CKC: CPU clock, CKD: Data clock, CKP: Clock terminal, COMC: Common circuit, CONT: Control unit, CNTL: Control circuit, COUP: Optical coupler, CPUIC: CPU chip, CPUC: CPU core, CSB: Chip selection signal, CSD: CS line driver, CSN: N side common source line, CSP: P side common source line, Cs: capacitor, DIV: frequency divider, DIVW: duplexer, DIS: serial input data, DM: data mask, DMUX: demultiplexer, DOS: Serial output data, DQ: Optical signal, DQI: data signal, DQIP: data terminal, DQP: data optical terminal, DRAMIC: DRAM chip, DRAMIC: DRAM core, DRAMMOD: DRAM module, DSP: serial input data terminal, QSP: serial output data terminal, EQD : BLEQ signal driver, FUSE: fuse, FX: sub-word driver selection line, FXD: FX line driver, IBC: input circuit, IBUS: internal bus, IBUSC: intra-chip bus control circuit, IFCIC: CPU side interface chip, IFCC: CPU Side interface core, IFDIC: DRAM side interface chip, IFDC: DRAM side interface core, IFD-EIC: electrical interface chip, IFD-EC: electrical interface core, IFD-OIC: Optical interface chip, IFD-OC: Optical interface core, LD: Laser, LIO, LIOT, LIOB: Local IO line, LTC: Latch circuit, MC: Memory cell, MCB: Memory controller block, MCC: Memory controller Core, MEM: DRAM core, MIO, MIOT, MIOB: main IO line, MIXW: multiplexer, ML: mirror structure, MOD: modulator, MUX: multiplexer, OBC: output circuit, OPIF: optical interface circuit, OPIO: Optical bus, PCC: Precharge circuit, PD: Photo detector, RASB: Row address strobe signal, READ: Read command, RESETB: Reset signal, R / W AMP: Read / write circuit, SA: Sense amplifier, SAA: Sense amplifier Column, S EQ: CS line precharge circuit, SHR: sense amplifier separation signal, SN: storage node, SUB: board substrate, SWD: subword driver, SWDA: subword driver string, TIA: transimpedance amplifier, TSVC: input / output circuit for through via , VIA: Through-via, VSP: Power supply pad, WEB: Write enable, WG: Optical waveguide, WL: Word line, WRITE: Write command, XDEC: Row decoder, XP: Cross area, YDEC: Column decoder, YS: Column selection line.

Claims

A first information storage unit having a plurality of first memory cells;
A second information storage unit having a plurality of second memory cells;
A first interface unit provided corresponding to the first information storage unit, to which a first command / address optical signal for accessing the plurality of first memory cells is input;
A second interface unit provided corresponding to the second information storage unit, to which a second command / address optical signal for accessing the plurality of second memory cells is input, and
The first interface unit includes a first clock recovery circuit for extracting a first address clock from the first command / address optical signal, and from the first command / address optical signal according to the first address clock. Outputting the extracted first command and first address as an electrical signal to the first information storage unit;
The second interface unit includes a second clock recovery circuit for extracting a second address clock from the second command / address optical signal, and from the second command / address optical signal according to the second address clock. A semiconductor memory device, wherein the extracted second command and second address are output to the second information storage unit as electrical signals.
In claim 1,
The semiconductor memory device, wherein the first information storage unit and the second information storage unit are formed on the same chip.
In claim 2,
The first information storage unit operates with a clock obtained by multiplying the first address clock,
The second information storage unit operates with a clock obtained by multiplying the second address clock,
The semiconductor memory device, wherein the first information storage unit and the second information storage unit can operate independently.
In claim 3,
The first interface unit receives a first write data optical signal to be stored in the first information storage unit and outputs a first read data optical signal read from the first information storage unit. ,
The first interface unit converts the first write data optical signal into an electric signal, performs serial / parallel conversion, and stores the first information in a bus width larger than the bus width of the first write data optical signal. Output to
The first interface unit has a bus width larger than the bus width of the first read data optical signal, and the data read from the first information storage unit is converted into an optical signal after parallel-serial conversion, A semiconductor memory device that outputs the first read data optical signal.
In claim 4,
A first optical interface circuit connected to the first clock recovery circuit; and a second light that receives the first write data optical signal and outputs the first read data optical signal. An interface circuit; and a third clock recovery circuit connected to the second optical interface circuit,
The first optical interface circuit converts the first command / address optical signal into a first current signal, converts the first current signal into a first voltage signal, and outputs first command / address serial data. A first transimpedance amplifier,
The first clock recovery circuit includes a first PLL circuit that receives the first command / address serial data and generates the first address clock, and a first demultiplexer that parallelizes the first command / address serial data. Have
The second optical interface circuit converts the first ride data optical signal into a second current signal, converts the second current signal into a second voltage signal, and converts the first write serial data into the second voltage signal. A second transimpedance amplifier to be generated, and a first optical modulator that generates the first read data optical signal by modulating light output from the laser in accordance with data read from the first information storage unit. Have
The third clock recovery circuit receives the first write serial data, generates a first data clock, a second PLL circuit, a second demultiplexer that parallelizes the first write serial data, and the first information storage. A semiconductor memory device comprising: a first multiplexer that serializes data read from the first unit and outputs the data to the first optical modulator.
In claim 5,
The first interface unit is formed on a different chip from the first information storage unit,
The semiconductor memory device, wherein the second interface unit is formed on a different chip from the second information storage unit.
In claim 6,
The first optical interface circuit is formed on a different chip from the first clock recovery circuit;
The semiconductor memory device, wherein the second optical interface circuit is formed on a different chip from the third clock recovery circuit.
In claim 5,
The first information storage unit and the first and third clock recovery circuits are formed on the same chip,
The semiconductor memory device, wherein the first and second optical interface circuits are formed on a chip different from the first information storage unit.
In claim 1,
The first interface unit is connected to the first clock recovery circuit, converts a first command / address optical signal into an electrical signal, and an input first write data optical signal as an electrical signal. A second optical interface circuit that converts data input as an electrical signal into a first read data optical signal and outputs the first read data optical signal, and is connected to the second optical interface circuit, A third clock recovery circuit for extracting a first data clock from the electrical signal converted from the first write data optical signal;
The first and second optical interface circuits are formed on a different chip from the first information storage unit,
The semiconductor memory device, wherein the chip provided with the first information storage unit and the chip provided with the first and second optical interface circuits are stacked in a vertical direction with respect to the substrate.
In claim 9,
The chip provided with the first and second optical interface circuits and the chip provided with the first information storage unit are connected by a through electrode penetrating the chip provided with the information storage unit. A semiconductor memory device.
An information processing unit;
A memory control having a first interface unit to which a first read data optical signal is input from the outside and a second interface unit to which a second read data optical signal is input from the outside, and is connected to the information processing unit And comprising
The first interface unit has a first clock recovery circuit for extracting a first data clock from the first read data optical signal, and is extracted from the first read data optical signal according to the first data clock. Output the first read data as an electrical signal,
The second interface unit includes a second clock recovery circuit for extracting a second data clock from the second read data optical signal, and is extracted from the second read data optical signal according to the second data clock. An information processing apparatus using the second read data as an electrical signal.
In claim 11,
The information processing unit includes a first CPU and a second CPU,
The memory control unit operates in accordance with an instruction from the first CPU, operates in accordance with an instruction from the first CPU and the second CPU, and has a second interface unit. An information processing apparatus comprising: 2 memory control cores.
In claim 12,
The information processing apparatus, wherein the first memory control core and the second memory control core are operable with independent clocks.
In claim 13,
The first interface unit outputs a first command / address optical signal to the outside of the information processing apparatus, and outputs a first write data optical signal to the outside of the information processing apparatus,
The second interface unit outputs a second command / address optical signal to the outside of the information processing apparatus, and outputs a second write data optical signal to the outside of the information processing apparatus,
The first interface unit performs serial / parallel conversion on the first read data extracted by converting the first read data optical signal into an electrical signal, and is larger than a bus width of the first read data optical signal. The first read data is output to the inside of the information processing apparatus with a bus width, and the first command address input as an electric signal to the first interface unit is converted into an optical signal after parallel-serial conversion. The first write data output as the first command / address optical signal and converted into an optical signal after parallel-serial conversion of the first write data input as the electric signal to the first interface unit, and the first write data light Output as a signal,
The second interface unit performs serial / parallel conversion on the second read data extracted by converting the second read data optical signal into an electrical signal, and is larger than a bus width of the second read data optical signal. The second read data is output to the inside of the information processing device with a bus width, and the second command address input as an electric signal to the second interface unit is converted into an optical signal after parallel-serial conversion. The second write data that is output as the second command / address optical signal and input to the second interface unit as an electric signal is converted from the second write data to the optical signal after parallel / serial conversion. An information processing apparatus that outputs the signal as a signal.
In claim 14,
The first interface unit further includes a first PLL circuit, and generates the first command / address optical signal and the first write data optical signal according to a first clock generated from the first PLL circuit,
The second interface unit further includes a second PLL circuit, and generates the second command / address optical signal and the second write data optical signal in accordance with a second clock generated from the second PLL circuit. An information processing apparatus characterized by the above.
An information processing unit;
A first memory module having a first information storage unit and a second information storage unit;
A second memory module having a third information storage unit and a fourth information storage unit;
A first optical waveguide for transmitting a first command / address optical signal and a first data optical signal between the information processing unit and the first and third information storage units;
A second optical waveguide for transmitting a second command / address optical signal and a second data optical signal between the information processing unit and the second and fourth information storage units;
The information processing apparatus, wherein the first optical waveguide and the second optical waveguide can be transmitted independently.
In claim 16,
The first optical waveguide includes a first optical coupler disposed in parallel to the first optical waveguide directly below the first memory module, and parallel to the first optical waveguide directly below the second memory module. A second optical coupler disposed; a first mirror structure having a surface inclined by 45 degrees with respect to a traveling direction of light immediately below the information processing unit; and a first mirror structure provided at an end opposite to the first mirror structure. 1 non-reflective coating part,
The first optical coupler has a second mirror structure in which optical signals transmitted through the first optical waveguide are coupled at a constant rate, and one end thereof has a surface inclined by 45 degrees with respect to the light traveling direction. Have
The second optical coupler has a third mirror structure in which optical signals transmitted through the first optical waveguide are coupled at a constant rate, and one end thereof has a surface inclined by 45 degrees with respect to the light traveling direction. An information processing apparatus comprising:
In claim 16,
The information processing unit and the first information storage unit transmit and receive the first command / address optical signal and the first data optical signal using an optical signal having a first wavelength,
The information processing unit and the third information storage unit transmit and receive the first command / address optical signal and the first data optical signal using an optical signal having a second wavelength different from the first wavelength,
The information processing apparatus superimposes and outputs the first command / address optical signal having the first wavelength and the first command / address optical signal having the second wavelength. .
In claim 18,
The first optical waveguide is provided immediately below the first memory module, and serves as a first optical coupler that selectively couples the first command / address optical signal and the first data optical signal of the first wavelength. A filter, and a second optical coupler / filter provided immediately below the second memory module, which selectively combines the first command / address optical signal and the first data optical signal of the second wavelength. An information processing apparatus comprising: