WO2012031546A1

WO2012031546A1 - Mos device and fabricating method thereof

Info

Publication number: WO2012031546A1
Application number: PCT/CN2011/079359
Authority: WO
Inventors: Le Wang
Original assignee: Csmc Technologies Fab1 Co., Ltd; Csmc Technologies Fab2 Co., Ltd.
Priority date: 2010-09-07
Filing date: 2011-09-06
Publication date: 2012-03-15
Also published as: CN102403335A

Abstract

AMOS device and a fabricating method thereof are provided. The fabricating method of the MOS device includes the steps of growing an implanted oxide layer on a substrate (11), forming a well (13) in the substrate (11) by lithography and an ion implantation process, removing the implanted oxide layer, then depositing an epitaxial layer (15) on the surface of the substrate (11) to form a channel region, growing a gate oxide (17) on the epitaxial layer (15), depositing a poly-silicon layer on the gate oxide (17), and then etching the poly-silicon layer to form a gate (19), and implanting ions into the epitaxial layer (15) and the well (13) to form a source (21) and a drain (23) on opposite lateral sides of the gate (19). By using a deposition process to form the epitaxial layer for the channel region, the doping concentration and thickness of the channel region are uniform, and the threshold voltage is stable.

Description

MOS DEVICE AND FABRICATING METHOD THEREOF

BACKGROUND

Field of the Invention

The present invention relates generally to a MOS device and a fabricating method thereof.

Description of the Related Art

The technology of retrograde doping in the channel regions of MOS devices is widely used in current integrated circuit (IC) fabrication processing. The main features of such retrograde processes is the lateral doping concentration, along the plane of the semiconductor surface is uniform, while the vertical doping concentration perpendicular to the surface is non-uniform. Thus, a MOS device formed by retrograde doping technology can achieve high surface drift mobility, thereby increasing the MOS device's drive current. Further, the higher doping below the channel due to retrograde doping can reduce leakage current in the cut-off state of a MOS device; thereby short-channel effects of the MOS device are inhibited.

However, in a traditional retrograde doping process, the channel region of the MOS device is formed by the processes of ion implantation and diffusion, so the concentration of the channel region is prone to change during subsequent thermal processing. Thus, the doping concentration and thickness of the channel region is hard to control.

BRIEF SUMMARY

The present invention relates generally to a MOS device and a fabricating method thereof. More specifically, some embodiments of the present invention relate to a MOS device structure and method of fabrication with better control of the doping concentration and thickness of the channel region.

According to one embodiment of the present invention, a MOS device, includes a substrate, a well formed in the substrate, and a source and a drain disposed in the well. A channel region is formed between the source and the drain, and the channel region is doped substantially uniformly.

According to one specific embodiment, the channel region is adapted to be formed by depositing an epitaxial layer on the well, and the thickness of the epitaxial layer is substantially uniform.

According to another specific embodiment, the thickness of the epitaxial layer is in the range of 10 to 100 nm, the doping concentration of the epitaxial layer is in the range of 1x10¹³ to 8x10¹⁴ /cm³, the MOS device includes a gate oxide formed on the epitaxial layer and a gate formed on the gate oxide, and the thickness of the gate is in the range of 2500 to 3500 Ǻ.

According to one embodiment of the present invention, a method of fabricating a MOS device, includes growing an implanted oxide layer on a substrate, forming a well in the substrate by a lithography and a ion implantation process, removing the implanted oxide layer, then depositing an epitaxial layer on the surface of the substrate. The method of fabricating a MOS device, further includes growing a gate oxide on the epitaxial layer, depositing a poly-silicon layer on the gate oxide, and then etching the poly-silicon layer to form a gate, and implanting ions into the epitaxial layer and the well to form a source and a drain. The source and the drain are disposed on opposite lateral sides of the gate. A channel region is formed in the deposited epitaxial layer between the source and drain.

According to one specific embodiment the doping concentration and thickness of the channel region are substantially uniform. According to another specific embodiment, the thickness of the implanted oxide layer is in the range of 250 to 350 Ǻ, the thickness of the epitaxial layer is in the range of 10 to 100 nm, and the doping concentration of the epitaxial layer is in the range of 1x10¹³ to 8x10¹⁴ /cm³.

According to another specific embodiment, the thickness of the gate is in the range of 2500 to 3500 Ǻ. According to another specific embodiment, the implantation energy of the implanting ion process is in the range of 70 to 90 keV. According to another specific embodiment, the implantation dose of the implanting ions process is in the range of 4x10¹² to 6x10¹² /cm². According to another specific embodiment, the epitaxial layer is deposited by a method of selective epitaxial growth.

A better understanding of the nature and advantages of the embodiments of the present invention may be gained with reference to the following detailed description and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG.1 is a simplified cross sectional view showing a MOS device structure, in accordance with an embodiment of the present invention;

FIG.2 is a simplified flow chart showing a method of fabricating a MOS device, in accordance with an embodiment of the present invention .

DETAILED DESCRIPTION

According to the embodiments of the present invention, a deposition process is used to form the epitaxial layer which contains the channel region of the MOS device. The doping concentration and thickness of the deposited epitaxial layer are uniform. Thus, the doping concentration in the channel region is substantially uniform and, as a result, less susceptible to change upon the application of subsequent thermal processing steps, ensuring stable and controllable MOS device threshold voltage. Further, other characteristics of the MOS device are more easily optimized than in traditionally formed devices.

FIG.1 is a simplified cross sectional view showing a MOS device structure, in accordance with an embodiment of the present invention, which includes a substrate 11, a well 13, an epitaxial layer 15, a gate oxide 17, a gate 19, a source 21, and a drain 23. Well 13 is formed in substrate 11. Epitaxial layer 15 is formed on or over both substrate 11 and well 13. Gate oxide 17 is formed on epitaxial layer 15. Gate 19 is formed on gate oxide 17. Source 21 and drain 23 are disposed in epitaxial layer 15 and optionally in well 13. Source 21 and drain 23 are disposed on opposite lateral sides of gate 19.

As an example, if the MOS device is a PMOS device, well 13 is an N-type well. Source 21 and drain 23 may be heavily doped using P-type dopants (P+), and the preferred P-type dopant may be formed using a BF₂ ion implant. Epitaxial layer 15 may be formed by a deposition process. Epitaxial layer 15 may be a lightly doped N-type epitaxial layer, and the doping concentration may be in the range of 1x10¹³ to 8x10¹⁴ /cm³. Epitaxial layer 15 is used for forming a channel region of the P-type MOS device . The preferred thickness of epitaxial layer 15 may be in the range of 10 to 100 nm. The doping concentration and/or thickness of epitaxial layer 15 may be uniform and may be adjusted to meet design requirements of the MOS device. The concentration and depth of well 13, source 21 and drain 23 may also be adjusted to meet design requirements of the MOS device.

The channel region is formed between the source and the drain and in the deposited epitaxial layer close to the gate oxide. Since epitaxial layer 17 is deposited on or over well 13, the doping from the well may be prevented from reaching the channel region, i.e., the channel region may be confined within the portion of the deposited epitaxial layer away from the well. Thus, the doping concentration and thickness of the channel region are determined by the uniform doping concentration of the deposited epitaxial layer and not the doping from the well. The resulting separate doping control of the well and the channel region, which are both of the same conductivity type, may be independently optimized to advantageously improve overall MOS device performance. Thus, the channel doping may be independently optimized for threshold voltage and drive current, while the well doping may be independently optimized for inhibiting short-channel effects or other device characteristics.

By using selective epitaxial growth to form epitaxial layer 15, the thickness and doping concentration of epitaxial layer 15 is easy to control, and the channel region formed with the epitaxial layer 15 is doped substantially uniformly. Thus, the doping concentration of the channel region does not change significantly during subsequent thermal processing, making the thickness and doping concentration of the channel region easy to control. In turn, the threshold voltage of the MOS device, which depends on the doping concentration in the channel region, is easy to control and good MOS threshold voltage control is highly desirable in IC manufacturing. During oxidation of the epitaxial layer, some doping redistribution may occur in the channel region but the resulting change in doping concentration is not substantial for thin gate oxidations, and the change is minor in comparison to the doping concentration changes in the channel resulting from using traditional MOS fabrication techniques such as retrograde wells, or other fabrication techniques where the channel doping is non-uniform.

In contrast, in traditional MOS devices, the source and drain are formed in a well, and the channel region is formed in the well by ion implantation and diffusion processes. Further, the doping concentration of the channel region is not uniform. Thus, the concentration of the channel region is prone to change during subsequent thermal processing, making the thickness and doping concentration of the channel region hard to control. Therefore, the threshold voltage and drive current of the MOS device is hard to control. Since the channel doping depends also on the well doping, the drive characteristics and short channel characteristics require compromise and are difficult to optimize for overall MOS performance.

FIG.2 is a simplified flow chart showing a method of fabricating a MOS device, in accordance with an embodiment of the present invention, which includes the following steps. An implanted oxide layer is grown 101 on substrate 11. The thickness of the implanted oxide layer is in the range of 250 to 350 Ǻ and preferably 300Ǻ. A well 13 is then formed 103 in substrate 11 by lithography and ion implantation process.

The channel area is formed 105 by the next sequence of steps. The implanted oxide layer is removed, then an epitaxial layer 15 is deposited on the surface of substrate 11 to form the basis of what will become the channel region. The thickness of epitaxial layer 15 may be in the range of 10 to 100 nm. The doping concentration of epitaxial layer 15 may be in the range of 1x10¹³ to 8x10¹⁴ /cm³. The doping of the epitaxial layer may be done in-situ with the deposition, resulting in uniform doping concentration as well as uniform thickness of the deposited epitaxial layer. The method of depositing or growing epitaxial layer 15 may be selective epitaxial growth, molecular beam epitaxy, LPCVD, or the like.

Then, gate oxide 17 is grown 107 on epitaxial layer 15. A poly-silicon layer is deposited on gate oxide 17, and then the poly-silicon layer is etched by using a lithography and etching process forming 109 gate 19. The thickness of the poly-silicon layer and gate 19 is in the range of 2500 to 3500 Ǻ and preferably 3000 Ǻ. Source 21 and drain 23 are formed 111 by implanting ions into epitaxial layer 15 and optionally into well 13, those ions being chosen to make the source and drain opposite in conductivity type to that of the epitaxial layer and the well. Source 21 and drain 23 are disposed on opposite lateral sides of the gate since the gate prevents penetration of the ions into the channel region. The source/drain ion implant may penetrate through the epitaxial layer and optionally penetrate into the well. The source and drain are thus disposed in the epitaxial layer and optionally in the well. The channel region is thus formed in the epitaxial layer between the source and drain and above the well. The source and drain implantation energy is in the range of 70 to 90 keV and preferably 80keV, and the implantation dose is in the range of 4x10¹² to 6x10¹² /cm² and preferably 5x10¹²/cm² of BF₂ ions for the PMOS device example.

The present disclosure may apply not only for PMOS devices as described in the above embodiments, but also for NMOS devices by changing the N well to a P well, changing the epitaxial layer conductivity type from N-type to P-type, and by changing the ion implant species to result in N-type instead of P-type source/drains.

Embodiments of the present invention provides an apparatus and a method for fabricating MOS devices. It will be apparent to those with skill in the art that modifications to the above methods and apparatuses may occur without deviating from the scope of the present invention. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims along with their full scope of equivalents.

Claims

A MOS device, comprising: a substrate; a well formed in the substrate; and a source and a drain disposed in the well, wherein a channel region is formed between the source and the drain, and the channel region is doped substantially uniformly.
The MOS device according to claim 1, wherein the channel region is adapted to be formed by depositing an epitaxial layer on the well, and the thickness of the epitaxial layer is substantially uniform.
The MOS device according to claim 2, wherein the thickness of the epitaxial layer is in the range of 10 to 100 nm, the doping concentration of the epitaxial layer is in the range of 1x10¹³ to 8x10¹⁴ /cm³; the MOS device includes a gate oxide formed on the epitaxial layer and a gate formed on the gate oxide, and the thickness of the gate is in the range of 2500 to 3500 Ǻ.
A method of fabricating a MOS device, comprising: growing an implanted oxide layer on a substrate; forming a well in the substrate by a lithography and a ion implantation process; removing the implanted oxide layer, then depositing an epitaxial layer on the surface of the substrate; growing a gate oxide on the epitaxial layer;

depositing a poly-silicon layer on the gate oxide, and then etching the poly-silicon layer to form a gate; and implanting ions into the epitaxial layer and the well to form a source and a drain, wherein the source and the drain are disposed on opposite lateral sides of the gate, wherein a channel region is formed in the deposited epitaxial layer between the source and drain.
The method of fabricating a MOS device according to claim 4, wherein the doping concentration and thickness of the channel region are substantially uniform.
The method of fabricating a MOS device according to claim 4, wherein the thickness of the implanted oxide layer is in the range of 250 to 350 Ǻ, the thickness of the epitaxial layer is in the range of 10 to 100 nm, and the doping concentration of the epitaxial layer is in the range of 1x10¹³ to 8x10¹⁴ /cm³.
The method of fabricating a MOS device according to claim 4, wherein the thickness of the gate is in the range of 2500 to 3500 Ǻ.
The method of fabricating a MOS device according to claim 4, wherein the implantation energy of the implanting ion process is in the range of 70 to 90 keV.
The method of fabricating a MOS device according to claim 4, wherein the implantation dose of the implanting ions process is in the range of 4x10¹² to 6x10¹² /cm².
The method of fabricating a MOS device according to claim 4, wherein the epitaxial layer is deposited by a method of selective epitaxial growth.