WO2012039850A3 - Method of improving mechanical properties of semiconductor interconnects with nanoparticles - Google Patents

Method of improving mechanical properties of semiconductor interconnects with nanoparticles Download PDF

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Publication number
WO2012039850A3
WO2012039850A3 PCT/US2011/047152 US2011047152W WO2012039850A3 WO 2012039850 A3 WO2012039850 A3 WO 2012039850A3 US 2011047152 W US2011047152 W US 2011047152W WO 2012039850 A3 WO2012039850 A3 WO 2012039850A3
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WO
WIPO (PCT)
Prior art keywords
cap
film
ulk
nanoparticles
mechanical properties
Prior art date
Application number
PCT/US2011/047152
Other languages
French (fr)
Other versions
WO2012039850A2 (en
Inventor
Junjing Bao
Naftali E. Lustig
Tien-Jen J. Cheng
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International Business Machines Corporation
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Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to GB1305611.4A priority Critical patent/GB2497485B/en
Priority to CN2011800432052A priority patent/CN103180933A/en
Priority to DE112011103146.7T priority patent/DE112011103146B4/en
Publication of WO2012039850A2 publication Critical patent/WO2012039850A2/en
Publication of WO2012039850A3 publication Critical patent/WO2012039850A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor

Abstract

In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics 100. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles 120 is inserted between the cap 130 and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.
PCT/US2011/047152 2010-09-20 2011-08-10 Method of improving mechanical properties of semiconductor interconnects with nanoparticles WO2012039850A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB1305611.4A GB2497485B (en) 2010-09-20 2011-08-10 Method of improving mechanical properties of semiconductor interconnects with nanoparticles
CN2011800432052A CN103180933A (en) 2010-09-20 2011-08-10 Method of improving mechanical properties of semiconductor interconnects with nanoparticles
DE112011103146.7T DE112011103146B4 (en) 2010-09-20 2011-08-10 Method for improving the mechanical properties of semiconductor interconnects with nanoparticles

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/885,596 2010-09-20
US12/885,596 US8129269B1 (en) 2010-09-20 2010-09-20 Method of improving mechanical properties of semiconductor interconnects with nanoparticles

Publications (2)

Publication Number Publication Date
WO2012039850A2 WO2012039850A2 (en) 2012-03-29
WO2012039850A3 true WO2012039850A3 (en) 2012-06-07

Family

ID=45757901

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/047152 WO2012039850A2 (en) 2010-09-20 2011-08-10 Method of improving mechanical properties of semiconductor interconnects with nanoparticles

Country Status (5)

Country Link
US (2) US8129269B1 (en)
CN (1) CN103180933A (en)
DE (1) DE112011103146B4 (en)
GB (1) GB2497485B (en)
WO (1) WO2012039850A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235304A1 (en) * 2011-03-18 2012-09-20 Globalfoundries Inc. Ultraviolet (uv)-reflecting film for beol processing
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US9367654B2 (en) * 2013-02-28 2016-06-14 Taiwan Semiconductor Manufacturing Company Limited Variation modeling
CN104112700B (en) * 2013-04-18 2017-03-29 中芯国际集成电路制造(上海)有限公司 A kind of method for improving rupture of line defect in metal interconnection process
CN104658967B (en) * 2013-11-21 2017-10-20 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method
US20150357236A1 (en) 2014-06-08 2015-12-10 International Business Machines Corporation Ultrathin Multilayer Metal Alloy Liner for Nano Cu Interconnects
KR102491577B1 (en) 2015-09-23 2023-01-25 삼성전자주식회사 Method of forming semiconductor device having dielectric layer and related system
US9768061B1 (en) * 2016-05-31 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k dielectric interconnect systems
US10211153B2 (en) 2016-08-30 2019-02-19 International Business Machines Corporation Low aspect ratio interconnect
EP3633431A1 (en) 2018-10-05 2020-04-08 Indigo Diabetes N.V. Weld protection for hermetic wafer-level sealing
US10679892B1 (en) * 2019-02-28 2020-06-09 International Business Machines Corporation Multi-buried ULK field in BEOL structure
CN110972403A (en) * 2019-12-04 2020-04-07 广东工业大学 Forming method of fine embedded circuit based on nano copper

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022412A1 (en) * 2004-08-02 2006-02-02 Clark Equipment Company Two component seal
EP1669647A1 (en) * 2004-12-08 2006-06-14 Kabushiki Kaisha Toyota Jidoshokki Method and device for sealing a bearing
WO2006081664A1 (en) * 2005-02-03 2006-08-10 Héroux-Devtek Inc. Alternative uplock release assembly

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930034B2 (en) * 2002-12-27 2005-08-16 International Business Machines Corporation Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US7166531B1 (en) * 2005-01-31 2007-01-23 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials
WO2008033227A2 (en) * 2006-09-11 2008-03-20 Applied Nano Works, Inc. Optically clear nanoparticle colloidal suspensions and method of making thereof
US7749892B2 (en) * 2006-11-29 2010-07-06 International Business Machines Corporation Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices
KR101329143B1 (en) 2007-01-10 2013-11-20 삼성전자주식회사 Ultraviolet barrier material with metal nanoparticle
WO2009102363A2 (en) * 2007-11-15 2009-08-20 Stc.Unm Ultra-thin microporous/hybrid materials
US20090258230A1 (en) 2008-04-11 2009-10-15 Kobo Products, Inc. Porous and/or hollow material containing uv attenuating nanoparticles, method of production and use

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022412A1 (en) * 2004-08-02 2006-02-02 Clark Equipment Company Two component seal
EP1669647A1 (en) * 2004-12-08 2006-06-14 Kabushiki Kaisha Toyota Jidoshokki Method and device for sealing a bearing
WO2006081664A1 (en) * 2005-02-03 2006-08-10 Héroux-Devtek Inc. Alternative uplock release assembly

Also Published As

Publication number Publication date
GB2497485B (en) 2014-12-24
US20120146224A1 (en) 2012-06-14
DE112011103146B4 (en) 2015-02-26
GB201305611D0 (en) 2013-05-15
US8129269B1 (en) 2012-03-06
US8384219B2 (en) 2013-02-26
DE112011103146T5 (en) 2013-07-25
WO2012039850A2 (en) 2012-03-29
US20120068315A1 (en) 2012-03-22
CN103180933A (en) 2013-06-26
GB2497485A (en) 2013-06-12

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