WO2012082223A3 - Non-volatile storage system with shared bit lines connected to single selection device - Google Patents

Non-volatile storage system with shared bit lines connected to single selection device Download PDF

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Publication number
WO2012082223A3
WO2012082223A3 PCT/US2011/056146 US2011056146W WO2012082223A3 WO 2012082223 A3 WO2012082223 A3 WO 2012082223A3 US 2011056146 W US2011056146 W US 2011056146W WO 2012082223 A3 WO2012082223 A3 WO 2012082223A3
Authority
WO
WIPO (PCT)
Prior art keywords
storage system
volatile storage
bit lines
selection device
lines connected
Prior art date
Application number
PCT/US2011/056146
Other languages
French (fr)
Other versions
WO2012082223A2 (en
Inventor
Nima Mokhlesi
Mohan V. Dunga
Masaaki Higashitani
Original Assignee
SanDisk Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk Technologies, Inc. filed Critical SanDisk Technologies, Inc.
Publication of WO2012082223A2 publication Critical patent/WO2012082223A2/en
Publication of WO2012082223A3 publication Critical patent/WO2012082223A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.
PCT/US2011/056146 2010-12-13 2011-10-13 Non-volatile storage system with shared bit lines connected to single selection device WO2012082223A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US42238510P 2010-12-13 2010-12-13
US61/422,385 2010-12-13
US13/107,686 US8837216B2 (en) 2010-12-13 2011-05-13 Non-volatile storage system with shared bit lines connected to a single selection device
US13/107,686 2011-05-13

Publications (2)

Publication Number Publication Date
WO2012082223A2 WO2012082223A2 (en) 2012-06-21
WO2012082223A3 true WO2012082223A3 (en) 2013-04-04

Family

ID=46199260

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/056146 WO2012082223A2 (en) 2010-12-13 2011-10-13 Non-volatile storage system with shared bit lines connected to single selection device

Country Status (3)

Country Link
US (1) US8837216B2 (en)
TW (1) TW201230042A (en)
WO (1) WO2012082223A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8455939B2 (en) * 2010-12-21 2013-06-04 Sandisk Technologies Inc. Stacked metal fin cell
US9076544B2 (en) 2011-11-18 2015-07-07 Sandisk Technologies Inc. Operation for non-volatile storage system with shared bit lines
KR101897826B1 (en) * 2012-01-30 2018-09-12 에스케이하이닉스 주식회사 Semiconductor memory device and method of operating the same
US8902659B2 (en) * 2012-03-26 2014-12-02 SanDisk Technologies, Inc. Shared-bit-line bit line setup scheme
KR20140100143A (en) 2013-02-05 2014-08-14 삼성전자주식회사 Programming and reading methods of nonvolatle memory device
US9349452B2 (en) * 2013-03-07 2016-05-24 Sandisk Technologies Inc. Hybrid non-volatile memory cells for shared bit line
US9165656B2 (en) 2013-03-11 2015-10-20 Sandisk Technologies Inc. Non-volatile storage with shared bit lines and flat memory cells
US8879331B2 (en) 2013-03-12 2014-11-04 Sandisk Technologies Inc. Shared bit line string architecture
TW201528439A (en) * 2013-10-07 2015-07-16 Conversant Intellectual Property Man Inc A cell array with a manufacturable select gate for a nonvolatile semiconductor memory device
US9021343B1 (en) * 2014-06-13 2015-04-28 Sandisk Technologies Inc. Parity scheme for a data storage device
US9721662B1 (en) 2016-01-13 2017-08-01 Sandisk Technologies Llc Non-volatile memory with efficient programming
US20210143275A1 (en) * 2019-11-11 2021-05-13 Integrated Silicon Solution Inc. Finfet stack gate memory and mehod of forming thereof

Citations (2)

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Publication number Priority date Publication date Assignee Title
US20080090351A1 (en) * 2006-10-17 2008-04-17 Nima Mokhlesi Fabricating non-volatile memory with dual voltage select gate structure
DE102007033017A1 (en) * 2007-05-15 2008-11-20 Qimonda Ag Integrated circuits, methods of manufacturing an integrated circuit, memory modules, computer systems

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JP3207592B2 (en) 1993-03-19 2001-09-10 株式会社東芝 Nonvolatile semiconductor memory device
US5555204A (en) 1993-06-29 1996-09-10 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
KR0169267B1 (en) 1993-09-21 1999-02-01 사토 후미오 Nonvolatile semiconductor memory device
US5903495A (en) 1996-03-18 1999-05-11 Kabushiki Kaisha Toshiba Semiconductor device and memory system
KR100190089B1 (en) 1996-08-30 1999-06-01 윤종용 Flash memory device and its operating method
US6091633A (en) 1999-08-09 2000-07-18 Sandisk Corporation Memory array architecture utilizing global bit lines shared by multiple cells
US6480422B1 (en) 2001-06-14 2002-11-12 Multi Level Memory Technology Contactless flash memory with shared buried diffusion bit line architecture
US6522580B2 (en) 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6927430B2 (en) 2001-06-28 2005-08-09 Sharp Laboratories Of America, Inc. Shared bit line cross-point memory array incorporating P/N junctions
US6456528B1 (en) 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
US6620683B1 (en) 2001-12-04 2003-09-16 Taiwan Semiconductor Manufacturing Company Twin-bit memory cell having shared word lines and shared bit-line contacts for electrically erasable and programmable read-only memory (EEPROM) and method of manufacturing the same
US6859397B2 (en) 2003-03-05 2005-02-22 Sandisk Corporation Source side self boosting technique for non-volatile memory
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US6917542B2 (en) 2003-07-29 2005-07-12 Sandisk Corporation Detecting over programmed memory
JP2005056989A (en) 2003-08-01 2005-03-03 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing the same
US7221588B2 (en) 2003-12-05 2007-05-22 Sandisk 3D Llc Memory array incorporating memory cells arranged in NAND strings
US7492640B2 (en) 2007-06-07 2009-02-17 Sandisk Corporation Sensing with bit-line lockout control in non-volatile memory
US7489553B2 (en) 2007-06-07 2009-02-10 Sandisk Corporation Non-volatile memory with improved sensing having bit-line lockout control
US20090302472A1 (en) 2008-06-05 2009-12-10 Samsung Electronics Co., Ltd. Non-volatile memory devices including shared bit lines and methods of fabricating the same
KR101462606B1 (en) * 2008-10-08 2014-11-19 삼성전자주식회사 Non-volatile memory device having shared bit lines

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080090351A1 (en) * 2006-10-17 2008-04-17 Nima Mokhlesi Fabricating non-volatile memory with dual voltage select gate structure
DE102007033017A1 (en) * 2007-05-15 2008-11-20 Qimonda Ag Integrated circuits, methods of manufacturing an integrated circuit, memory modules, computer systems

Also Published As

Publication number Publication date
WO2012082223A2 (en) 2012-06-21
US20120147676A1 (en) 2012-06-14
US8837216B2 (en) 2014-09-16
TW201230042A (en) 2012-07-16

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