WO2012170302A3 - Method for providing high etch rate - Google Patents

Method for providing high etch rate Download PDF

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Publication number
WO2012170302A3
WO2012170302A3 PCT/US2012/040523 US2012040523W WO2012170302A3 WO 2012170302 A3 WO2012170302 A3 WO 2012170302A3 US 2012040523 W US2012040523 W US 2012040523W WO 2012170302 A3 WO2012170302 A3 WO 2012170302A3
Authority
WO
WIPO (PCT)
Prior art keywords
deposition
phase
processing chamber
gas
plasma processing
Prior art date
Application number
PCT/US2012/040523
Other languages
French (fr)
Other versions
WO2012170302A2 (en
Inventor
Qing Xu
Camelia Rusu
Jaroslaw W. Winniczek
Frank Y. Lin
Alan J. Miller
Original Assignee
Lam Research Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/154,075 external-priority patent/US8440473B2/en
Application filed by Lam Research Corporation filed Critical Lam Research Corporation
Priority to KR1020147000351A priority Critical patent/KR101919641B1/en
Publication of WO2012170302A2 publication Critical patent/WO2012170302A2/en
Publication of WO2012170302A3 publication Critical patent/WO2012170302A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H01J37/32449—Gas control, e.g. control of the gas flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Abstract

A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.
PCT/US2012/040523 2011-06-06 2012-06-01 Method for providing high etch rate WO2012170302A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020147000351A KR101919641B1 (en) 2011-06-06 2012-06-01 Method for providing high etch rate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/154,075 US8440473B2 (en) 2011-06-06 2011-06-06 Use of spectrum to synchronize RF switching with gas switching during etch
US13/154,075 2011-06-06
US13/188,174 US8609548B2 (en) 2011-06-06 2011-07-21 Method for providing high etch rate
US13/188,174 2011-07-21

Publications (2)

Publication Number Publication Date
WO2012170302A2 WO2012170302A2 (en) 2012-12-13
WO2012170302A3 true WO2012170302A3 (en) 2013-02-07

Family

ID=47262000

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/040523 WO2012170302A2 (en) 2011-06-06 2012-06-01 Method for providing high etch rate

Country Status (4)

Country Link
US (1) US8609548B2 (en)
KR (1) KR101919641B1 (en)
TW (1) TWI552221B (en)
WO (1) WO2012170302A2 (en)

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JP6207947B2 (en) * 2013-09-24 2017-10-04 東京エレクトロン株式会社 Method for plasma processing a workpiece
KR102258099B1 (en) 2014-03-07 2021-05-28 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
US9484202B1 (en) * 2015-06-03 2016-11-01 Applied Materials, Inc. Apparatus and methods for spacer deposition and selective removal in an advanced patterning process
US9620356B1 (en) 2015-10-29 2017-04-11 Applied Materials, Inc. Process of selective epitaxial growth for void free gap fill
US10886136B2 (en) * 2019-01-31 2021-01-05 Tokyo Electron Limited Method for processing substrates
CN113767187A (en) 2019-04-19 2021-12-07 应用材料公司 Method of forming metal-containing materials

Citations (4)

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Publication number Priority date Publication date Assignee Title
KR19980033000A (en) * 1996-10-21 1998-07-25 조셉제이.스위니 Method for Processing Semiconductor Workpieces in a Plasma Reactor Chamber
US20070281479A1 (en) * 2006-06-02 2007-12-06 Applied Materials, Inc. Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon
US7306745B1 (en) * 1999-04-14 2007-12-11 Surface Technology Systems Plc Method and apparatus for stabilizing a plasma
US20090050603A1 (en) * 2007-08-20 2009-02-26 Lam Research Corporation Mask trimming with arl etch

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DE4241045C1 (en) 1992-12-05 1994-05-26 Bosch Gmbh Robert Process for anisotropic etching of silicon
EP0756318A1 (en) 1995-07-24 1997-01-29 International Business Machines Corporation Method for real-time in-situ monitoring of a trench formation process
EP0822582B1 (en) * 1996-08-01 2003-10-01 Surface Technology Systems Plc Method of etching substrates
GB9616225D0 (en) 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
US6716758B1 (en) 1999-08-25 2004-04-06 Micron Technology, Inc. Aspect ratio controlled etch selectivity using time modulated DC bias voltage
US6160621A (en) 1999-09-30 2000-12-12 Lam Research Corporation Method and apparatus for in-situ monitoring of plasma etch and deposition processes using a pulsed broadband light source
US6897155B2 (en) * 2002-08-14 2005-05-24 Applied Materials, Inc. Method for etching high-aspect-ratio features
US7531842B2 (en) * 2002-12-20 2009-05-12 Analog Devices, Inc. Method for etching a tapered bore in a silicon substrate, and a semiconductor wafer comprising the substrate
US20040157457A1 (en) 2003-02-12 2004-08-12 Songlin Xu Methods of using polymer films to form micro-structures
US7067432B2 (en) 2003-06-26 2006-06-27 Applied Materials, Inc. Methodology for in-situ and real-time chamber condition monitoring and process recovery during plasma processing
US7217951B2 (en) 2003-09-23 2007-05-15 Stc@Unm Detector with tunable spectral response
US7135410B2 (en) 2003-09-26 2006-11-14 Lam Research Corporation Etch with ramping
US6950178B2 (en) 2003-10-09 2005-09-27 Micron Technology, Inc. Method and system for monitoring plasma using optical emission spectroscopy
US20050112891A1 (en) * 2003-10-21 2005-05-26 David Johnson Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation
US7959819B2 (en) 2004-06-29 2011-06-14 Shouliang Lai Method and apparatus for reducing aspect ratio dependent etching in time division multiplexed etch processes
US20060000799A1 (en) 2004-06-30 2006-01-05 Hyun-Ho Doh Methods and apparatus for determining endpoint in a plasma processing system
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
US7537671B2 (en) 2006-09-29 2009-05-26 Tokyo Electron Limited Self-calibrating optical emission spectroscopy for plasma monitoring
KR20100065321A (en) 2007-08-07 2010-06-16 피포탈 시스템즈 코포레이션 Method and apparatus for identifying the chemical composition of a gas
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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980033000A (en) * 1996-10-21 1998-07-25 조셉제이.스위니 Method for Processing Semiconductor Workpieces in a Plasma Reactor Chamber
US7306745B1 (en) * 1999-04-14 2007-12-11 Surface Technology Systems Plc Method and apparatus for stabilizing a plasma
US20070281479A1 (en) * 2006-06-02 2007-12-06 Applied Materials, Inc. Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon
US20090050603A1 (en) * 2007-08-20 2009-02-26 Lam Research Corporation Mask trimming with arl etch

Also Published As

Publication number Publication date
KR101919641B1 (en) 2018-11-16
US8609548B2 (en) 2013-12-17
US20120309194A1 (en) 2012-12-06
TW201304001A (en) 2013-01-16
TWI552221B (en) 2016-10-01
WO2012170302A2 (en) 2012-12-13
KR20140036299A (en) 2014-03-25

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