WO2013005667A1 - METHOD FOR MANUFACTURING GaN SEMICONDUCTOR ELEMENT - Google Patents

METHOD FOR MANUFACTURING GaN SEMICONDUCTOR ELEMENT Download PDF

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WO2013005667A1
WO2013005667A1 PCT/JP2012/066677 JP2012066677W WO2013005667A1 WO 2013005667 A1 WO2013005667 A1 WO 2013005667A1 JP 2012066677 W JP2012066677 W JP 2012066677W WO 2013005667 A1 WO2013005667 A1 WO 2013005667A1
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gan
electrode
protective film
film
electrodes
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PCT/JP2012/066677
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French (fr)
Japanese (ja)
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藤田　耕一郎
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • the present invention relates to a method for manufacturing a GaN-based semiconductor element.
  • Patent Document 1 Japanese Patent Laid-Open No. 2008-306026 discloses a method for manufacturing a GaN-based FET (field effect transistor).
  • an electrode is formed on a GaN-based semiconductor layer, the electrode is heat-treated to form a source / drain electrode as an ohmic electrode, and the source / drain electrode and the GaN-based semiconductor layer are formed on the source / drain electrode.
  • An insulating film (silicon nitride film or the like) is formed, and this insulating film is heat-treated.
  • This current collapse is particularly prominent in a GaN-based semiconductor device, and is a phenomenon in which the on-resistance of a transistor in high-voltage operation is significantly higher than the on-resistance of the transistor in low-voltage operation. .
  • the present inventors formed a SiN insulating film for suppressing current collapse after forming the source / drain electrodes, and when heat treatment is performed in this state, the electrode metal becomes SiN. A problem has been discovered in which it diffuses into the insulating film and causes leakage current via the SiN insulating film.
  • an object of the present invention is to provide a method of manufacturing a GaN-based semiconductor element that can suppress the diffusion of electrode metal into the SiN insulating film, and can achieve both suppression of current collapse and reduction of leakage current.
  • the present invention was created based on the discovery of the phenomenon that the electrode metal diffuses into the silicon nitride film when heat-treating the silicon nitride film that suppresses current collapse with the electrode formed. It has been done.
  • the present inventors have formed a silicon nitride film and heat-treated, and then formed an electrode and heat-treated (ohmic annealing) to form an ohmic electrode. It has been found that it is effective in suppressing diffusion into the film, and that leakage current passing through the silicon nitride film can be reduced.
  • a protective film including a silicon nitride film or a protective film made of a silicon nitride film is formed on a GaN-based stacked body having a heterojunction, Heat treating the protective film, Etching at least a predetermined region of the protective film of the protective film and the GaN-based laminate to remove an ohmic electrode formation region of the GaN-based laminate, Forming an electrode containing Ti / Al or Hf / Al in the ohmic electrode formation region of the GaN-based laminate; The electrode is heat-treated to form an ohmic electrode.
  • a protective film including the silicon nitride film or a protective film made of a silicon nitride film is formed on the GaN-based stacked body, and the protection for suppressing the current collapse is performed.
  • an electrode is formed on the GaN-based laminate, and the electrode is heat treated to form an ohmic electrode.
  • the electrode metal is suppressed from diffusing into the protective film during the heat treatment of the electrode, It has been found that the leakage current passing through the protective film can be reduced.
  • the present invention it is possible to manufacture a GaN-based semiconductor element that can not only suppress current collapse by the protective film but also reduce the leakage current passing through the protective film.
  • “current collapse” is a problem particularly in GaN-based semiconductor devices, and the transistor resistance in high-voltage operation is lower than the on-resistance of the transistor in low-voltage operation. This is a phenomenon in which the on-resistance becomes extremely high.
  • the protective film is A lower layer silicon nitride film formed on the GaN-based laminate, An upper silicon nitride film formed on the lower silicon nitride film; An SiO 2 film or an Al 2 O 3 film formed on the upper silicon nitride film,
  • the upper silicon nitride film is a stoichiometric silicon nitride film.
  • the upper silicon nitride film is stoichiometry, and an SiO 2 film or an Al 2 O 3 film is formed on the upper silicon nitride film. It is possible to suppress the electrode metal from diffusing into the upper layer and the lower layer silicon nitride film of the protective film during the heat treatment, and to further reduce the leakage current passing through the protective film.
  • the stoichiometric silicon nitride film means that Si and N have a composition of 3: 4.
  • the temperature at which the electrode is heat-treated is lower than the temperature at which the protective film is heat-treated.
  • the electrode metal when the electrode is heat-treated, the electrode metal can be prevented from diffusing into the protective film, and the leakage current passing through the protective film can be further reduced.
  • an electrode metal is protected by forming an ohmic electrode after forming a protective film including the silicon nitride film or a protective film made of a silicon nitride film and performing heat treatment. Since diffusion to the film is suppressed and leakage current passing through the protective film can be reduced, a GaN-based semiconductor element capable of both suppressing current collapse and reducing leakage current can be manufactured.
  • (First embodiment) 1 to 5 are cross-sectional views sequentially showing steps of a method of manufacturing a GaN-based HFET (Hetero-junction Field Effect Transistor) according to the first embodiment of the present invention.
  • GaN-based HFET Hetero-junction Field Effect Transistor
  • an undoped AlGaN buffer layer 2, an undoped GaN channel layer 3, and an undoped AlGaN barrier layer 4 are sequentially formed on a Si substrate 1 by using MOCVD (metal organic chemical vapor deposition).
  • MOCVD metal organic chemical vapor deposition
  • the AlGaN buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a GaN-based laminate 5.
  • reference numeral 6 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 4 and the GaN channel layer 3.
  • a SiN protective film 7 which is a silicon nitride film is formed on the AlGaN barrier layer 4 by using a plasma CVD method.
  • the growth temperature of the SiN protective film 7 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C.
  • the thickness of the SiN protective film 7 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
  • the SiN protective film 7 having a silicon Si ratio larger than that of the stoichiometric silicon nitride film can be formed.
  • current collapse can be further suppressed as compared with a stoichiometric silicon nitride film.
  • a photoresist layer (not shown) is formed on the SiN protective film 7, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, dry etching is performed. Thereby, as shown in FIG. 3, openings 10 and 11 are formed in the SiN protective film 7 and recesses 12 and 13 reaching from the AlGaN barrier layer 4 to the GaN channel layer 3 are formed.
  • the recesses 12 and 13 form an ohmic electrode formation region.
  • the method of forming the recesses 12 and 13 is not limited to the above.
  • an AlGaN barrier is formed.
  • the recesses 12 and 13 may be formed by dry etching the layer 4 and the GaN channel layer 3.
  • the SiN protective film 7 is heat-treated.
  • This heat treatment was performed, for example, at 500 ° C. for 5 minutes in a nitrogen atmosphere.
  • the temperature of the heat treatment may be set in the range of 500 ° C. to 700 ° C. as an example.
  • a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including regions by the recesses 12 and 13 and the openings 10 and 11) is formed is formed on the photoresist.
  • Ti and Al are deposited in this order, and lift-off provides a source electrode and a drain electrode so as to fill the recesses 12 and 13 and the openings 10 and 11 and have a region overlapping the SiN protective film 7 as shown in FIG.
  • Ti / Al electrodes 15 and 16 are formed.
  • the Ti / Al electrodes 15 and 16 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated.
  • the electrodes 15 and 16 are heat-treated to form ohmic electrodes, and the source electrode 15 and the drain electrode 16 are formed.
  • the condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this.
  • the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
  • a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 7 is to be formed, thereby forming an opening 20.
  • TiN is sputtered over the entire surface so as to fill the opening 20, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • dry etching or wet etching is performed.
  • Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 18 is formed.
  • the undoped AlGaN barrier layer 4 is located immediately below the gate electrode 18, and the junction between the gate electrode 18 and the undoped AlGaN barrier layer 4 is a Schottky junction.
  • the SiN protective film 7 is formed on the GaN-based stacked body 5, and the SiN protective film 7 is heat-treated (for example, 5 ° C. at 500 ° C.).
  • the Ti / Al electrodes 15 and 16 are formed on the GaN-based laminate 5, and the Ti / Al electrodes 15 and 16 are heat-treated to form the source electrode 15 and the drain electrode 16 as ohmic electrodes.
  • the inventors formed the SiN protective film 7 and heat-treated, then formed the Ti / Al electrodes 15 and 16 and heat-treated (ohmic annealing) to form the source electrode 15 and the drain electrode 16 as ohmic electrodes.
  • the electrode metal can be prevented from diffusing into the SiN protective film 7 and the leakage current passing through the SiN protective film 7 can be reduced.
  • the manufacturing method of this embodiment it is possible to manufacture a GaN-based HFET that can simultaneously suppress the current collapse by the SiN protective film 7 and reduce the leakage current passing through the SiN protective film 7.
  • “current collapse” is particularly problematic in GaN-based semiconductor devices, and the on-resistance of a transistor in high-voltage operation is higher than the on-resistance of the transistor in low-voltage operation. It is a phenomenon that ends up.
  • FIG. 7 is a graph comparing the yield (%) of the GaN-based HFET fabricated according to the present embodiment and the yield (%) of the GaN-based HFET fabricated according to the comparative example.
  • the Ti / Al electrodes 15 and 16 are heat-treated (ohmic annealing).
  • the Ti / Al electrodes 15 and 16 are not heat-treated before the Ti / Al electrodes 15 and 16 shown in FIG. This heat treatment (onic annealing) is also used as the heat treatment of the SiN protective film 7.
  • the gate leakage current is measured with the gate voltage Vg set to ⁇ 10 (V), the drain voltage Vd and the source voltage Vs set to 0 (V), and the gate leakage current is 1 ⁇ 10 ⁇ 5 ( When it was within A), it was judged as acceptable, and when the gate leakage current exceeded 1 ⁇ 10 ⁇ 5 (A), it was judged as unacceptable.
  • the gate leakage current was measured at room temperature (25 ° C.). As shown in FIG. 7, the yield (%) of the GaN-based HFET fabricated in this embodiment is 100%, whereas the yield (%) of the GaN-based HFET fabricated in the comparative example is 40%. The yield improvement according to the present embodiment was apparent.
  • FIGS. 9 to 13 are cross-sectional views sequentially showing the steps of the method of manufacturing the GaN-based HFET which is the second embodiment of the present invention.
  • an undoped AlGaN buffer layer 72, an undoped GaN channel layer 73, and an undoped AlGaN barrier layer 74 are sequentially formed on a Si substrate 71 using MOCVD (metal organic chemical vapor deposition).
  • MOCVD metal organic chemical vapor deposition
  • the AlGaN buffer layer 72, the GaN channel layer 73, and the AlGaN barrier layer 74 constitute a GaN-based stacked body 75.
  • reference numeral 76 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 74 and the GaN channel layer 73.
  • the GaN-based laminate 75 produced in the second embodiment differs from the GaN-based laminate 5 produced in the first embodiment described above in that the thickness of the AlGaN barrier layer 74 is the same as that of the AlGaN of the first embodiment. It is thinner than the thickness of the barrier layer 4 (for example, 30 nm), for example, 10 nm. Thus, ohmic contacts can be made on electrodes 85 and 86 described later without forming the recesses 12 and 13 as in the first embodiment.
  • a SiN protective film 77 which is a silicon nitride film, is formed on the AlGaN barrier layer 74 by plasma CVD.
  • the growth temperature of the SiN protective film 77 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C.
  • the thickness of the SiN protective film 77 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
  • a photoresist layer (not shown) is formed on the SiN protective film 77, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, wet etching is performed. Thus, openings 70 and 71 are formed in the SiN protective film 77 as shown in FIG. The region of the AlGaN barrier layer 74 exposed in the openings 70 and 71 forms an ohmic electrode formation region.
  • the SiN protective film 77 is heat-treated.
  • the temperature of this heat treatment was, for example, 500 ° C. for 5 minutes. Note that the temperature of the heat treatment may be set in a range of 500 ° C. to 700 ° C. as an example.
  • a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including the exposed AlGaN barrier layer 74 region) is formed, and Ti is formed on the photoresist.
  • Al are sequentially deposited, and Ti / Al electrodes 85 and 86 are formed by lift-off so as to fill the openings 70 and 71 and to overlap the SiN protective film 77 as shown in FIG.
  • the Ti / Al electrodes 85 and 86 serve as a source electrode and a drain electrode.
  • the Ti / Al electrodes 85 and 86 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated.
  • the electrodes 85 and 86 are heat-treated to form ohmic electrodes, and the source electrode 85 and the drain electrode 86 are formed.
  • the condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this.
  • the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
  • a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 77 is to be formed, thereby forming an opening 90.
  • TiN is sputtered over the entire surface so as to fill the opening 90, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • dry etching or wet etching is performed.
  • Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 88 is formed.
  • An undoped AlGaN barrier layer 74 is located immediately below the gate electrode 88, and the junction between the gate electrode 88 and the undoped AlGaN barrier layer 74 is a Schottky junction.
  • the Si / N protective film 77 formed on the GaN-based stacked body 75 is modified by heat treatment, and then the Ti / Al electrodes 85, 86 are used. Is formed on the GaN-based laminate 75, and the Ti / Al electrode is heat-treated to form a source electrode 85 and a drain electrode 86 as ohmic electrodes.
  • the Ti / Al electrodes 85 and 86 are heat-treated (ohmic annealing) to form the source electrode 85 and the drain electrode 86 as ohmic electrodes.
  • the thickness of the AlGaN barrier layer 74 is made thinner than the thickness of the AlGaN barrier layer 4 of the first embodiment so that the source electrode 85 and the drain electrode 86 can be in ohmic contact.
  • the thickness of the AlGaN barrier layer 74 is equal to the thickness of the AlGaN barrier layer 4, the ohmic contact portion of the AlGaN barrier layer 74 is preliminarily doped with Si so as to be n-type, thereby enabling ohmic contact of the electrode. It is good.
  • the Si substrate is used as the substrate, but a sapphire substrate may be used.
  • a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as growing an AlGaN layer on the GaN substrate.
  • a buffer layer may be appropriately formed between the substrate and each layer.
  • a hetero improvement layer made of AlN may be formed between the GaN channel layers 3 and 73 and the AlGaN barrier layers 4 and 74.
  • a GaN cap layer may be formed on the AlGaN barrier layers 4 and 74.
  • the gate electrodes 18 and 88 were produced with TiN, you may produce with WN.
  • the gate electrodes 18 and 88 may be made of Pt / Au or Ni / Au.
  • the protective film that suppresses current collapse is the SiN protective film 7, 77 made of a single layer of silicon nitride film (SiN film).
  • the protective film that suppresses current collapse is A lower SiN film having a larger silicon Si ratio than a stoichiometric silicon nitride film and a stoichiometric upper SiN film may be used. In this case, it is possible to suppress the diffusion of the electrode metal by the stoichiometric upper SiN film and to suppress the current collapse by the lower SiN film having a large silicon Si ratio. Further, an SiO 2 film or an Al 2 O 3 film may be formed on the SiN protective films 7 and 77.
  • a protective film 50 in which a lower SiN film 51, an upper SiN film 52 that is stoichiometry, and a SiO 2 film 53 are sequentially stacked may be used as a protective film that suppresses current collapse.
  • the upper SiN film 52 is stoichiometric means that Si and N have a composition of 3: 4.
  • the protective film 50 since the upper SiN film 52 is stoichiometry and the SiO 2 film 53 is formed on the upper SiN film 52, the upper and lower SiN layers of the protective film 50 are heat-treated during the heat treatment of the electrode.
  • the diffusion of the electrode metal into the protective layers 52 and 51 can be suppressed, and the leakage current passing through the protective film 50 can be further reduced.
  • the lower SiN film 51 is a SiN protective film having a silicon Si ratio larger than that of the stoichiometric silicon nitride film, the current collapse can be suppressed as compared with the stoichiometric silicon nitride film.
  • a stoichiometric silicon nitride film may be used. In this case, the leakage current can be further reduced by suppressing the diffusion of the electrode metal.
  • an Al 2 O 3 film may be used instead of the SiO 2 film 53.
  • the heat treatment temperature of the SiN protective films 7 and 77 is set to 500 ° C.
  • the heat treatment temperature of the electrodes 15, 16, 85, and 86 is set to 500 ° C. It is desirable that the heat treatment temperature of the electrodes 15, 16, 85, 86 be lower than the heat treatment temperature of the SiN protective film 77.
  • the heat treatment temperature of the SiN protective film 77 is 500 ° C.
  • the heat treatment temperature of the electrodes 15, 16, 85, 86 be 450 ° C. lower than 500 ° C.
  • the source electrodes 15 and 85 and the drain electrodes 16 and 86 as the ohmic electrodes are Ti / Al electrodes in which a Ti layer and an Al layer are sequentially stacked.
  • a Ti / Al / TiN electrode in which an Al layer and a TiN layer are sequentially laminated may be used.
  • the source electrode and the drain electrode may be Hf / Al electrodes.
  • Ni / Au may be stacked on Ti / Al or Hf / Al, or Pt / Au may be stacked on Ti / Al or Hf / Al. It is good also as what laminated
  • the temperature conditions for the ohmic annealing of the electrodes 15, 16, 85, 86 are set to 500 ° C.
  • the contact resistance ( ⁇ mm) of the electrodes 15, 16, 85, 86 rapidly increases when the temperature of the ohmic annealing is set to 700 ° C. exceeding 600 ° C. Therefore, it is desirable that the ohmic annealing temperature of the electrodes 15, 16, 85, 86 is 600 ° C. or lower.
  • the Ti / Al electrodes 15 and 16 that become the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 7 and the recesses 12 and 13 and the openings 10 and 11 shown in FIG. Then, Ti, Al, and TiN are sequentially sputtered to fill the electrode, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and the drain electrode are to be formed by photolithography, and this resist pattern is used as a mask.
  • the Ti / Al / TiN electrodes 15 and 16 to be the source electrode and the drain electrode may be formed by performing dry etching or wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
  • the Ti / Al electrodes 85 and 86 to be the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 77 and the openings 70 and 71 shown in FIG. Ti, Al, TiN films are sequentially sputtered in order, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and drain electrode are to be formed by photolithography, and dry etching or etching is performed using this resist pattern as a mask.
  • the Ti / Al / TiN electrodes 85 and 86 to be the source electrode and the drain electrode may be formed by performing wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
  • the GaN-based semiconductor laminate in the manufacturing method of the present invention may include a GaN-based semiconductor layer represented by Al x In y Ga 1-xy N (x ⁇ 0, y ⁇ 0, 0 ⁇ x + y ⁇ 1). . That is, the GaN-based semiconductor laminate in the manufacturing method of the present invention may include AlGaN, GaN, InGaN, and the like.
  • the normally-on type HFET has been described.
  • the normally-off type can achieve the same effect.
  • the Schottky gate has been described, an insulated gate structure may be used.
  • the GaN-based semiconductor element manufactured by the present invention is not limited to the HFET of the above embodiment, but may be a field effect transistor having another configuration.

Abstract

In this method for manufacturing a GaN-based HFET, an SiN protection film (7) formed on a GaN laminated body (5) is modified by heat treatment, then, Ti-Al electrodes (15, 16) are formed on the GaN laminated body (5), and a source electrode (15) and a drain electrode (16) are formed as ohmic electrodes by heat-treating the Ti-Al electrodes (15, 16). After heat-treating the SiN protection film (7), the Ti-Al electrodes (15, 16) are heat-treated (ohmic annealed), and the source electrode (15) and the drain electrode (16) are formed as the ohmic electrodes, thereby suppressing diffusion of the electrode metal in the SiN protection film (7), and achieving both the current collapse suppression and leak current reduction.

Description

ＧａＮ系半導体素子の製造方法GaN-based semiconductor device manufacturing method
　この発明は、ＧａＮ系半導体素子の製造方法に関する。 The present invention relates to a method for manufacturing a GaN-based semiconductor element.
　従来、ＧａＮ系半導体素子の製造方法としては、特許文献１(特開２００８－３０６０２６号公報)にＧａＮ系ＦＥＴ(電界効果トランジスタ)の製造方法が開示されている。このＧａＮ系ＦＥＴの製造方法では、ＧａＮ系半導体層上に、電極を形成し、この電極を熱処理してオーミック電極としてのソース/ドレイン電極にし、このソース/ドレイン電極および上記ＧａＮ系半導体層上に絶縁膜(シリコン窒化膜等)を形成し、この絶縁膜を熱処理している。 Conventionally, as a method for manufacturing a GaN-based semiconductor element, Patent Document 1 (Japanese Patent Laid-Open No. 2008-306026) discloses a method for manufacturing a GaN-based FET (field effect transistor). In this GaN-based FET manufacturing method, an electrode is formed on a GaN-based semiconductor layer, the electrode is heat-treated to form a source / drain electrode as an ohmic electrode, and the source / drain electrode and the GaN-based semiconductor layer are formed on the source / drain electrode. An insulating film (silicon nitride film or the like) is formed, and this insulating film is heat-treated.
　上記ＧａＮ系ＦＥＴの製造方法では、ＧａＮ系半導体層の表面が上記絶縁膜に覆われた状態で熱処理を行うことによって、電流コラプスの抑制を図っている。 In the GaN-based FET manufacturing method, current collapse is suppressed by performing heat treatment in a state where the surface of the GaN-based semiconductor layer is covered with the insulating film.
　この電流コラプスとは、特に、ＧａＮ系半導体素子において顕著に表れるもので、低電圧動作でのトランジスタのオン抵抗と比べて、高電圧動作でのトランジスタのオン抵抗が著しく高くなってしまう現象である。 This current collapse is particularly prominent in a GaN-based semiconductor device, and is a phenomenon in which the on-resistance of a transistor in high-voltage operation is significantly higher than the on-resistance of the transistor in low-voltage operation. .
特開２００８－３０６０２６号公報JP 2008-306026 A
　ところで、本発明者らは、先述の従来例では、ソース/ドレイン電極を形成してから電流コラプスを抑制するためのＳｉＮ絶縁膜を形成し、この状態で熱処理を行なうと、電極メタルが上記ＳｉＮ絶縁膜に拡散して、上記ＳｉＮ絶縁膜を経由するリーク電流の原因になるという問題を発見した。 By the way, in the above-mentioned conventional example, the present inventors formed a SiN insulating film for suppressing current collapse after forming the source / drain electrodes, and when heat treatment is performed in this state, the electrode metal becomes SiN. A problem has been discovered in which it diffuses into the insulating film and causes leakage current via the SiN insulating film.
　従来は、電極が形成された状態で電流コラプスを抑制するＳｉＮ絶縁膜を熱処理する際にＳｉＮ絶縁膜に電極メタルが拡散するという現象が気づかれていなかった。本発明者が、この現象を初めて発見したのである。 Conventionally, when the SiN insulating film that suppresses current collapse is heat-treated in a state where the electrode is formed, the phenomenon that the electrode metal diffuses into the SiN insulating film has not been noticed. This inventor discovered this phenomenon for the first time.
　そこで、この発明の課題は、電極メタルがＳｉＮ絶縁膜に拡散することを抑制でき、電流コラプスの抑制とリーク電流の低減とを両立できるＧａＮ系半導体素子の製造方法を提供することにある。 Therefore, an object of the present invention is to provide a method of manufacturing a GaN-based semiconductor element that can suppress the diffusion of electrode metal into the SiN insulating film, and can achieve both suppression of current collapse and reduction of leakage current.
　本発明は、電極が形成された状態で電流コラプスを抑制するシリコン窒化膜を熱処理する際に上記シリコン窒化膜に電極メタルが拡散するという現象が本発明者らにより発見されたことに基づいて創出されたものである。 The present invention was created based on the discovery of the phenomenon that the electrode metal diffuses into the silicon nitride film when heat-treating the silicon nitride film that suppresses current collapse with the electrode formed. It has been done.
　本発明者らは、シリコン窒化膜を成膜して熱処理した後に、電極を形成して熱処理(オーミックアニール)し、オーミック電極を形成することが、熱処理の工程が増えるけれども、電極メタルがシリコン窒化膜へ拡散することを抑制するのに有効であり、上記シリコン窒化膜を経由するリーク電流を低減できることを見出した。 The present inventors have formed a silicon nitride film and heat-treated, and then formed an electrode and heat-treated (ohmic annealing) to form an ohmic electrode. It has been found that it is effective in suppressing diffusion into the film, and that leakage current passing through the silicon nitride film can be reduced.
　すなわち、この発明のＧａＮ系半導体素子の製造方法は、ヘテロ接合を有するＧａＮ系積層体上にシリコン窒化膜を含む保護膜またはシリコン窒化膜からなる保護膜を形成し、
　上記保護膜を熱処理し、
　上記保護膜および上記ＧａＮ系積層体のうちの少なくとも上記保護膜の予め定められた領域をエッチングで除去して上記ＧａＮ系積層体のオーミック電極形成領域を露出させ、
　上記ＧａＮ系積層体のオーミック電極形成領域にＴｉ/ＡｌまたはＨｆ/Ａｌを含む電極を形成し、
　上記電極を熱処理してオーミック電極にすることを特徴としている。 That is, in the method for manufacturing a GaN-based semiconductor element of the present invention, a protective film including a silicon nitride film or a protective film made of a silicon nitride film is formed on a GaN-based stacked body having a heterojunction,
Heat treating the protective film,
Etching at least a predetermined region of the protective film of the protective film and the GaN-based laminate to remove an ohmic electrode formation region of the GaN-based laminate,
Forming an electrode containing Ti / Al or Hf / Al in the ohmic electrode formation region of the GaN-based laminate;
The electrode is heat-treated to form an ohmic electrode.
　この発明のＧａＮ系半導体素子の製造方法によれば、上記ＧａＮ系積層体上に上記シリコン窒化膜を含む保護膜またはシリコン窒化膜からなる保護膜を形成し、この電流コラプスを抑制するための保護膜を熱処理により改質してから、電極をＧａＮ系積層体上に形成し、上記電極を熱処理してオーミック電極にする。 According to the method for manufacturing a GaN-based semiconductor device of the present invention, a protective film including the silicon nitride film or a protective film made of a silicon nitride film is formed on the GaN-based stacked body, and the protection for suppressing the current collapse is performed. After the film is modified by heat treatment, an electrode is formed on the GaN-based laminate, and the electrode is heat treated to form an ohmic electrode.
　このように、上記電流コラプスを抑制するための保護膜を成膜し熱処理してから、オーミック電極を形成することによって、上記電極の熱処理時に電極メタルが上記保護膜に拡散することが抑制され、上記保護膜を経由するリーク電流を低減できることが判明した。 Thus, by forming an ohmic electrode after forming and heat-treating a protective film for suppressing the current collapse, the electrode metal is suppressed from diffusing into the protective film during the heat treatment of the electrode, It has been found that the leakage current passing through the protective film can be reduced.
　よって、この発明によれば、上記保護膜によって電流コラプスを抑制できるだけでなく、上記保護膜を経由するリーク電流も低減できるＧａＮ系半導体素子を製造できる。ここで、再度述べると、「電流コラプス」とは、ＧａＮ系半導体素子において、特に、問題になっているもので、低電圧動作でのトランジスタのオン抵抗と比べて、高電圧動作でのトランジスタのオン抵抗が著しく高くなってしまう現象である。 Therefore, according to the present invention, it is possible to manufacture a GaN-based semiconductor element that can not only suppress current collapse by the protective film but also reduce the leakage current passing through the protective film. Here again, “current collapse” is a problem particularly in GaN-based semiconductor devices, and the transistor resistance in high-voltage operation is lower than the on-resistance of the transistor in low-voltage operation. This is a phenomenon in which the on-resistance becomes extremely high.
　また、一実施形態のＧａＮ系半導体素子の製造方法では、上記保護膜は、
　上記ＧａＮ系積層体上に形成された下層シリコン窒化膜と、
　上記下層シリコン窒化膜上に形成された上層シリコン窒化膜と、
　上記上層シリコン窒化膜上に形成されたＳｉＯ２膜またはＡｌ２Ｏ３膜と
を有し、
　上記上層シリコン窒化膜は、ストイキオメトリなシリコン窒化膜である。 In one embodiment of the method for manufacturing a GaN-based semiconductor device, the protective film is
A lower layer silicon nitride film formed on the GaN-based laminate,
An upper silicon nitride film formed on the lower silicon nitride film;
An SiO 2 film or an Al 2 O 3 film formed on the upper silicon nitride film,
The upper silicon nitride film is a stoichiometric silicon nitride film.
　この実施形態のＧａＮ系半導体素子の製造方法によれば、上層シリコン窒化膜がストイキオメトリであると共に上記上層シリコン窒化膜上にＳｉＯ２膜またはＡｌ２Ｏ３膜を形成したことで、上記電極の熱処理時に上記保護膜の上層および下層シリコン窒化膜へ電極メタルが拡散することを抑制でき、上記保護膜を経由するリーク電流をさらに低減できる。ここで、上記ストイキオメトリなシリコン窒化膜とは、ＳｉとＮが３：４の組成であることを意味している。 According to the method for manufacturing a GaN-based semiconductor device of this embodiment, the upper silicon nitride film is stoichiometry, and an SiO 2 film or an Al 2 O 3 film is formed on the upper silicon nitride film. It is possible to suppress the electrode metal from diffusing into the upper layer and the lower layer silicon nitride film of the protective film during the heat treatment, and to further reduce the leakage current passing through the protective film. Here, the stoichiometric silicon nitride film means that Si and N have a composition of 3: 4.
　また、一実施形態のＧａＮ系半導体素子の製造方法では、上記電極を熱処理する温度を、上記保護膜を熱処理する温度よりも低くした。 In addition, in the method for manufacturing a GaN-based semiconductor element according to one embodiment, the temperature at which the electrode is heat-treated is lower than the temperature at which the protective film is heat-treated.
　この実施形態のＧａＮ系半導体素子の製造方法によれば、上記電極を熱処理する際に、上記保護膜へ電極メタルが拡散することを抑制でき、上記保護膜を経由するリーク電流をさらに低減できる。 According to the method for manufacturing a GaN-based semiconductor element of this embodiment, when the electrode is heat-treated, the electrode metal can be prevented from diffusing into the protective film, and the leakage current passing through the protective film can be further reduced.
　この発明のＧａＮ系半導体素子の製造方法によれば、上記シリコン窒化膜を含む保護膜またはシリコン窒化膜からなる保護膜を成膜し熱処理した後に、オーミック電極を形成することによって、電極メタルが保護膜に拡散することが抑制され、上記保護膜を経由するリーク電流を低減できるので、電流コラプスの抑制とリーク電流の低減とを両立できるＧａＮ系半導体素子を製造できる。 According to the method for manufacturing a GaN-based semiconductor device of the present invention, an electrode metal is protected by forming an ohmic electrode after forming a protective film including the silicon nitride film or a protective film made of a silicon nitride film and performing heat treatment. Since diffusion to the film is suppressed and leakage current passing through the protective film can be reduced, a GaN-based semiconductor element capable of both suppressing current collapse and reducing leakage current can be manufactured.
この発明の第１実施形態のＧａＮ系半導体素子の製造方法の一工程を説明する図である。It is a figure explaining 1 process of the manufacturing method of the GaN-type semiconductor element of 1st Embodiment of this invention. 図１の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図２の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図３の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図４の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 上記ＧａＮ系半導体素子の保護膜の一例を示す断面図である。It is sectional drawing which shows an example of the protective film of the said GaN-type semiconductor element. 上記実施形態と比較例との歩留りの違いを示す図である。It is a figure which shows the difference in the yield of the said embodiment and a comparative example. オーミック電極のコンタクト抵抗とアニール温度との関係を示す図である。It is a figure which shows the relationship between the contact resistance of an ohmic electrode, and annealing temperature. この発明の第２実施形態のＧａＮ系半導体素子の製造方法の一工程を説明する図である。It is a figure explaining 1 process of the manufacturing method of the GaN-type semiconductor element of 2nd Embodiment of this invention. 図９の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図１０の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図１１の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG. 図１２の工程に続く工程を説明する図である。It is a figure explaining the process following the process of FIG.
　以下、この発明を図示の実施の形態により詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
　　(第１の実施の形態)
　図１～図５は、この発明の第１実施形態であるＧａＮ系ＨＦＥＴ(Hetero-junction Field Effect Transistor；ヘテロ接合電界効果トランジスタ)の製造方法の工程を順に示す断面図である。 (First embodiment)
1 to 5 are cross-sectional views sequentially showing steps of a method of manufacturing a GaN-based HFET (Hetero-junction Field Effect Transistor) according to the first embodiment of the present invention.
　まず、図１に示すように、Ｓｉ基板１上に、ＭＯＣＶＤ(有機金属気相成長)法を用いて、アンドープＡｌＧａＮバッファ層２、アンドープＧａＮチャネル層３、アンドープＡｌＧａＮバリア層４、を順に形成する。このＡｌＧａＮバッファ層２とＧａＮチャネル層３とＡｌＧａＮバリア層４がＧａＮ系積層体５を構成している。図１において、符号６は、ＡｌＧａＮバリア層４とＧａＮチャネル層３との界面に形成される２次元電子ガスを示している。 First, as shown in FIG. 1, an undoped AlGaN buffer layer 2, an undoped GaN channel layer 3, and an undoped AlGaN barrier layer 4 are sequentially formed on a Si substrate 1 by using MOCVD (metal organic chemical vapor deposition). . The AlGaN buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a GaN-based laminate 5. In FIG. 1, reference numeral 6 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 4 and the GaN channel layer 3.
　次に、図２に示すように、上記ＡｌＧａＮバリア層４上に、プラズマＣＶＤ法を用いて、シリコン窒化膜であるＳｉＮ保護膜７を形成する。このＳｉＮ保護膜７の成長温度は、一例として、２２５℃としたが、２００℃～４００℃の範囲で設定してもよい。また、上記ＳｉＮ保護膜７の膜厚は、一例として、１５０ｎｍとしたが、２０ｎｍ～２５０ｎｍの範囲で設定してもよい。 Next, as shown in FIG. 2, a SiN protective film 7 which is a silicon nitride film is formed on the AlGaN barrier layer 4 by using a plasma CVD method. The growth temperature of the SiN protective film 7 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C. The thickness of the SiN protective film 7 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
　また、一例として、上記プラズマＣＶＤ法によりＳｉＮ保護膜７を形成する際のガス流量比は、Ｎ２／ＮＨ３／ＳiＨ４＝３００ｓｃｃｍ／４０ｓｃｃｍ／３５ｓｃｃｍとした。これにより、ストイキオメトリなシリコン窒化膜よりもシリコンＳｉの比率の大きなＳｉＮ保護膜７を形成できる。このＳｉＮ保護膜７によれば、ストイキオメトリなシリコン窒化膜に比べて、電流コラプスをより抑制できる。また、例えば、ＳｉＮ保護膜７のＳｉとＮとの組成比Ｓｉ：Ｎ＝１.１～１．９：１にすると、Ｓｉ：Ｎ＝０.７５：１のストイキオメトリなシリコン窒化膜よりも電流コラプスの抑制に有効である。 As an example, the gas flow rate ratio when forming the SiN protective film 7 by the plasma CVD method was set to N 2 / NH 3 / SiH 4 = 300 sccm / 40 sccm / 35 sccm. Thereby, the SiN protective film 7 having a silicon Si ratio larger than that of the stoichiometric silicon nitride film can be formed. According to the SiN protective film 7, current collapse can be further suppressed as compared with a stoichiometric silicon nitride film. Further, for example, when the Si: N composition ratio Si: N of the SiN protective film 7 is set to 1.1 to 1.9: 1, the stoichiometric silicon nitride film of Si: N = 0.75: 1 is used. Is also effective in suppressing current collapse.
　次に、上記ＳｉＮ保護膜７上にフォトレジスト層(図示せず)を形成し、露光,現像することにより、上記フォトレジスト層に開口を形成し、上記開口を形成したフォトレジスト層をマスクとして、ドライエッチングを行なう。これにより、図３に示すように、上記ＳｉＮ保護膜７に開口１０,１１を形成すると共に上記ＡｌＧａＮバリア層４からＧａＮチャネル層３まで達するリセス１２,１３を形成する。このリセス１２,１３がオーミック電極形成領域をなす。なお、上記リセス１２,１３の形成方法は、上記に限らず、例えば、フォトレジスト層をマスクとして、上記開口１０,１１を形成する領域のＳｉＮ保護膜７をウェットエッチングで除去したのち、ＡｌＧａＮバリア層４およびＧａＮチャネル層３をドライエッチングすることにより、リセス１２,１３を形成してもよい。 Next, a photoresist layer (not shown) is formed on the SiN protective film 7, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, dry etching is performed. Thereby, as shown in FIG. 3, openings 10 and 11 are formed in the SiN protective film 7 and recesses 12 and 13 reaching from the AlGaN barrier layer 4 to the GaN channel layer 3 are formed. The recesses 12 and 13 form an ohmic electrode formation region. The method of forming the recesses 12 and 13 is not limited to the above. For example, after removing the SiN protective film 7 in the region for forming the openings 10 and 11 by wet etching using a photoresist layer as a mask, an AlGaN barrier is formed. The recesses 12 and 13 may be formed by dry etching the layer 4 and the GaN channel layer 3.
　次に、上記ＳｉＮ保護膜７を熱処理する。この熱処理は、例えば、窒素雰囲気で５００℃で５分間とした。また、上記熱処理の温度は、一例として、５００℃～７００℃の範囲で設定してもよい。 Next, the SiN protective film 7 is heat-treated. This heat treatment was performed, for example, at 500 ° C. for 5 minutes in a nitrogen atmosphere. The temperature of the heat treatment may be set in the range of 500 ° C. to 700 ° C. as an example.
　次に、フォトリソグラフィにより、ソース電極,ドレイン電極を形成すべき領域(リセス１２,１３と開口１０,１１による領域を含む)が開口したフォトレジスト(図示せず)を形成し、このフォトレジスト上にＴｉ,Ａｌを順に蒸着し、リフトオフにより、図４に示すように、リセス１２,１３と開口１０,１１を埋めると共にＳｉＮ保護膜７上に重なる領域を有するようにソース電極,ドレイン電極となるＴｉ/Ａｌ電極１５,１６を形成する。このＴｉ/Ａｌ電極１５,１６は、Ｔｉ層,Ａｌ層が順に積層された積層構造の電極である。次に、上記電極１５,１６を、熱処理してオーミック電極にし、ソース電極１５,ドレイン電極１６とする。この熱処理(オーミックアニール)の条件は、一例として５００℃で３０分としたが、上記熱処理の条件は、これに限らず、例えば、上記熱処理温度を、４００℃～６００℃の範囲内で設定してもよい。 Next, by photolithography, a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including regions by the recesses 12 and 13 and the openings 10 and 11) is formed is formed on the photoresist. Then, Ti and Al are deposited in this order, and lift-off provides a source electrode and a drain electrode so as to fill the recesses 12 and 13 and the openings 10 and 11 and have a region overlapping the SiN protective film 7 as shown in FIG. Ti / Al electrodes 15 and 16 are formed. The Ti / Al electrodes 15 and 16 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated. Next, the electrodes 15 and 16 are heat-treated to form ohmic electrodes, and the source electrode 15 and the drain electrode 16 are formed. The condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this. For example, the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
　次に、図５に示すように、フォトリソグラフィによりフォトレジストによるマスクを形成してエッチングすることで、上記ＳｉＮ保護膜７のゲート電極を形成すべき領域を除去して開口２０を形成する。その後、開口２０を埋めるように、ＴｉＮを全面スパッタし、フォトリソグラフィでゲート電極を形成すべき電極形成領域にレジストパターン(図示せず)を形成し、このレジストパターンをマスクとして、ドライエッチングまたはウエットエッチングを行なって、上記電極形成領域以外のＴｉＮ膜を除去して、ゲート電極１８となるＴｉＮ電極を形成する。ゲート電極１８の直下には、アンドープＡｌＧａＮバリア層４が位置しており、ゲート電極１８とアンドープＡｌＧａＮバリア層４との接合は、ショットキー接合となる。 Next, as shown in FIG. 5, a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 7 is to be formed, thereby forming an opening 20. Thereafter, TiN is sputtered over the entire surface so as to fill the opening 20, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography. Using this resist pattern as a mask, dry etching or wet etching is performed. Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 18 is formed. The undoped AlGaN barrier layer 4 is located immediately below the gate electrode 18, and the junction between the gate electrode 18 and the undoped AlGaN barrier layer 4 is a Schottky junction.
　このように、この第１実施形態のＧａＮ系ＨＦＥＴの製造方法によれば、上記ＧａＮ系積層体５上にＳｉＮ保護膜７を形成し、このＳｉＮ保護膜７を熱処理(例えば、５００℃で５分間)により改質してから、Ｔｉ/Ａｌ電極１５,１６をＧａＮ系積層体５上に形成し、上記Ｔｉ/Ａｌ電極１５,１６を熱処理してオーミック電極としてのソース電極１５,ドレイン電極１６とする。本発明者らは、ＳｉＮ保護膜７を成膜して熱処理した後に、上記Ｔｉ/Ａｌ電極１５,１６を形成し熱処理(オーミックアニール)して、オーミック電極としてソース電極１５,ドレイン電極１６を形成することによって、電極メタルがＳｉＮ保護膜７に拡散することを抑制できて、上記ＳｉＮ保護膜７を経由するリーク電流を低減できることを見出した。 Thus, according to the manufacturing method of the GaN-based HFET of the first embodiment, the SiN protective film 7 is formed on the GaN-based stacked body 5, and the SiN protective film 7 is heat-treated (for example, 5 ° C. at 500 ° C.). The Ti / Al electrodes 15 and 16 are formed on the GaN-based laminate 5, and the Ti / Al electrodes 15 and 16 are heat-treated to form the source electrode 15 and the drain electrode 16 as ohmic electrodes. And The inventors formed the SiN protective film 7 and heat-treated, then formed the Ti / Al electrodes 15 and 16 and heat-treated (ohmic annealing) to form the source electrode 15 and the drain electrode 16 as ohmic electrodes. As a result, it was found that the electrode metal can be prevented from diffusing into the SiN protective film 7 and the leakage current passing through the SiN protective film 7 can be reduced.
　したがって、この実施形態の製造方法によれば、上記ＳｉＮ保護膜７による電流コラプスの抑制と上記ＳｉＮ保護膜７を経由するリーク電流の低減とを両立できるＧａＮ系ＨＦＥＴを製造できる。ここで、「電流コラプス」とは、ＧａＮ系半導体素子において、特に、問題になっているもので、低電圧動作でのトランジスタのオン抵抗と比べて高電圧動作でのトランジスタのオン抵抗が高くなってしまう現象である。 Therefore, according to the manufacturing method of this embodiment, it is possible to manufacture a GaN-based HFET that can simultaneously suppress the current collapse by the SiN protective film 7 and reduce the leakage current passing through the SiN protective film 7. Here, “current collapse” is particularly problematic in GaN-based semiconductor devices, and the on-resistance of a transistor in high-voltage operation is higher than the on-resistance of the transistor in low-voltage operation. It is a phenomenon that ends up.
　図７は、本実施形態によって作製したＧａＮ系ＨＦＥＴの歩留り(％)と比較例によって作製したＧａＮ系ＨＦＥＴの歩留り(％)とを比較するグラフである。本実施形態では、上述の如く、ＳｉＮ保護膜７を形成し熱処理した後に、上記Ｔｉ/Ａｌ電極１５,１６を熱処理(オーミックアニール)するものである。これに対して、上記比較例では、図４に示すＴｉ/Ａｌ電極１５,１６をＧａＮ系積層体５上に形成する前にはＳｉＮ保護膜７を熱処理しないで、Ｔｉ/Ａｌ電極１５,１６の熱処理(オーニックアニール)を上記ＳｉＮ保護膜７の熱処理と兼用している。そして、上記歩留りを求めるために、本実施形態により１０個のサンプル(ＧａＮ系ＨＦＥＴ)を作製するとともに、上記比較例により１０個のサンプル(ＧａＮ系ＨＦＥＴ)を作製した。そして、各サンプルについて、ゲート電圧Ｖｇを－１０(Ｖ)とし、ドレイン電圧Ｖｄおよびソース電圧Ｖｓを０(Ｖ)として、ゲートリーク電流を計測して、このゲートリーク電流が１×１０－５(Ａ)以内である場合に合格と判定し、ゲートリーク電流が１×１０－５(Ａ)を超えたときに不合格と判定した。なお、このゲートリーク電流の測定は、常温(２５℃)にて行なった。図７に示すように、本実施形態で作製したＧａＮ系ＨＦＥＴの歩留り(％)は１００％であるのに対して、上記比較例で作製したＧａＮ系ＨＦＥＴの歩留り(％)は４０％であり、本実施形態による歩留りの向上が明らかであった。 FIG. 7 is a graph comparing the yield (%) of the GaN-based HFET fabricated according to the present embodiment and the yield (%) of the GaN-based HFET fabricated according to the comparative example. In the present embodiment, as described above, after the SiN protective film 7 is formed and heat-treated, the Ti / Al electrodes 15 and 16 are heat-treated (ohmic annealing). On the other hand, in the comparative example, the Ti / Al electrodes 15 and 16 are not heat-treated before the Ti / Al electrodes 15 and 16 shown in FIG. This heat treatment (onic annealing) is also used as the heat treatment of the SiN protective film 7. Then, in order to obtain the yield, ten samples (GaN-based HFET) were manufactured according to the present embodiment, and ten samples (GaN-based HFET) were manufactured according to the comparative example. For each sample, the gate leakage current is measured with the gate voltage Vg set to −10 (V), the drain voltage Vd and the source voltage Vs set to 0 (V), and the gate leakage current is 1 × 10 −5 ( When it was within A), it was judged as acceptable, and when the gate leakage current exceeded 1 × 10 −5 (A), it was judged as unacceptable. The gate leakage current was measured at room temperature (25 ° C.). As shown in FIG. 7, the yield (%) of the GaN-based HFET fabricated in this embodiment is 100%, whereas the yield (%) of the GaN-based HFET fabricated in the comparative example is 40%. The yield improvement according to the present embodiment was apparent.
　　(第２の実施の形態)
　次に、図９～図１３は、この発明の第２実施形態であるＧａＮ系ＨＦＥＴの製造方法の工程を順に示す断面図である。 (Second embodiment)
Next, FIGS. 9 to 13 are cross-sectional views sequentially showing the steps of the method of manufacturing the GaN-based HFET which is the second embodiment of the present invention.
　まず、図９に示すように、Ｓｉ基板７１上に、ＭＯＣＶＤ(有機金属気相成長)法を用いて、アンドープＡｌＧａＮバッファ層７２、アンドープＧａＮチャネル層７３、アンドープＡｌＧａＮバリア層７４、を順に形成する。このＡｌＧａＮバッファ層７２とＧａＮチャネル層７３とＡｌＧａＮバリア層７４がＧａＮ系積層体７５を構成している。図９において、符号７６は、ＡｌＧａＮバリア層７４とＧａＮチャネル層７３との界面に形成される２次元電子ガスを示している。 First, as shown in FIG. 9, an undoped AlGaN buffer layer 72, an undoped GaN channel layer 73, and an undoped AlGaN barrier layer 74 are sequentially formed on a Si substrate 71 using MOCVD (metal organic chemical vapor deposition). . The AlGaN buffer layer 72, the GaN channel layer 73, and the AlGaN barrier layer 74 constitute a GaN-based stacked body 75. In FIG. 9, reference numeral 76 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 74 and the GaN channel layer 73.
　この第２実施形態で作製するＧａＮ系積層体７５が、前述の第１実施形態で作製するＧａＮ系積層体５と異なる点は、上記ＡｌＧａＮバリア層７４の厚さを、第１実施形態のＡｌＧａＮバリア層４の厚さ(例えば３０ｎｍ)よりも薄く、例えば１０ｎｍとした点である。これにより、前述の第１実施形態のようなリセス１２,１３を形成することなく、後述する電極８５,８６をオーミックコンタクト可能にしている。 The GaN-based laminate 75 produced in the second embodiment differs from the GaN-based laminate 5 produced in the first embodiment described above in that the thickness of the AlGaN barrier layer 74 is the same as that of the AlGaN of the first embodiment. It is thinner than the thickness of the barrier layer 4 (for example, 30 nm), for example, 10 nm. Thus, ohmic contacts can be made on electrodes 85 and 86 described later without forming the recesses 12 and 13 as in the first embodiment.
　次に、図１０に示すように、上記ＡｌＧａＮバリア層７４上に、プラズマＣＶＤ法を用いて、シリコン窒化膜であるＳｉＮ保護膜７７を形成する。このＳｉＮ保護膜７７の成長温度は、一例として、２２５℃としたが、２００℃～４００℃の範囲で設定してもよい。また、上記ＳｉＮ保護膜７７の膜厚は、一例として、１５０ｎｍとしたが、２０ｎｍ～２５０ｎｍの範囲で設定してもよい。 Next, as shown in FIG. 10, a SiN protective film 77, which is a silicon nitride film, is formed on the AlGaN barrier layer 74 by plasma CVD. The growth temperature of the SiN protective film 77 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C. The thickness of the SiN protective film 77 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
　一例として、上記プラズマＣＶＤ法によりＳｉＮ保護膜７７を形成する際のガス流量比は、Ｎ２／ＮＨ３／ＳｉＨ４＝３００ｓｃｃｍ／４０ｓｃｃｍ／３５ｓｃｃｍとした。これにより、ストイキオメトリなシリコン窒化膜よりもシリコンＳｉの比率の大きなＳｉＮ保護膜７７を形成でき、電流コラプスの抑制効果を向上できる。 As an example, the gas flow rate ratio when forming the SiN protective film 77 by the plasma CVD method is set to N 2 / NH 3 / SiH 4 = 300 sccm / 40 sccm / 35 sccm. Thereby, the SiN protective film 77 having a silicon Si ratio larger than that of the stoichiometric silicon nitride film can be formed, and the current collapse suppressing effect can be improved.
　次に、上記ＳｉＮ保護膜７７上にフォトレジスト層(図示せず)を形成し、露光,現像することにより、上記フォトレジスト層に開口を形成し、上記開口を形成したフォトレジスト層をマスクとして、ウエットエッチングを行なう。これにより、図１１に示すように、上記ＳｉＮ保護膜７７に開口７０,７１を形成する。この開口７０,７１に露出したＡｌＧａＮバリア層７４の領域がオーミック電極形成領域をなす。 Next, a photoresist layer (not shown) is formed on the SiN protective film 77, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, wet etching is performed. Thus, openings 70 and 71 are formed in the SiN protective film 77 as shown in FIG. The region of the AlGaN barrier layer 74 exposed in the openings 70 and 71 forms an ohmic electrode formation region.
　次に、上記ＳｉＮ保護膜７７を熱処理する。この熱処理の温度は、例えば、５００℃で５分間とした。なお、上記熱処理の温度は、一例として、５００℃～７００℃の範囲で設定してもよい。 Next, the SiN protective film 77 is heat-treated. The temperature of this heat treatment was, for example, 500 ° C. for 5 minutes. Note that the temperature of the heat treatment may be set in a range of 500 ° C. to 700 ° C. as an example.
　次に、フォトリソグラフィにより、ソース電極,ドレイン電極を形成すべき領域(上記露出したＡｌＧａＮバリア層７４の領域を含む)が開口したフォトレジスト(図示せず)を形成し、このフォトレジスト上にＴｉ,Ａｌを順に蒸着し、リフトオフにより、図１２に示すように、開口７０,７１を埋めると共にＳｉＮ保護膜７７上に重なる領域を有するようにＴｉ/Ａｌ電極８５,８６を形成する。このＴｉ/Ａｌ電極８５,８６がソース電極,ドレイン電極となる。このＴｉ/Ａｌ電極８５,８６は、Ｔｉ層,Ａｌ層が順に積層された積層構造の電極である。次に、上記電極８５,８６を、熱処理してオーミック電極にし、ソース電極８５,ドレイン電極８６とする。この熱処理(オーミックアニール)の条件は、一例として５００℃で３０分としたが、上記熱処理の条件は、これに限らず、例えば、上記熱処理温度を、４００℃～６００℃の範囲内で設定してもよい。 Next, by photolithography, a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including the exposed AlGaN barrier layer 74 region) is formed, and Ti is formed on the photoresist. , Al are sequentially deposited, and Ti / Al electrodes 85 and 86 are formed by lift-off so as to fill the openings 70 and 71 and to overlap the SiN protective film 77 as shown in FIG. The Ti / Al electrodes 85 and 86 serve as a source electrode and a drain electrode. The Ti / Al electrodes 85 and 86 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated. Next, the electrodes 85 and 86 are heat-treated to form ohmic electrodes, and the source electrode 85 and the drain electrode 86 are formed. The condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this. For example, the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
　次に、図１３に示すように、フォトリソグラフィによりフォトレジストによるマスクを形成してエッチングすることで、上記ＳｉＮ保護膜７７のゲート電極を形成すべき領域を除去して開口９０を形成する。その後、開口９０を埋めるように、ＴｉＮを全面スパッタし、フォトリソグラフィでゲート電極を形成すべき電極形成領域にレジストパターン(図示せず)を形成し、このレジストパターンをマスクとして、ドライエッチングまたはウエットエッチングを行なって、上記電極形成領域以外のＴｉＮ膜を除去して、ゲート電極８８となるＴｉＮ電極を形成する。ゲート電極８８の直下には、アンドープＡｌＧａＮバリア層７４が位置しており、ゲート電極８８とアンドープＡｌＧａＮバリア層７４との接合は、ショットキー接合となる。 Next, as shown in FIG. 13, a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 77 is to be formed, thereby forming an opening 90. Thereafter, TiN is sputtered over the entire surface so as to fill the opening 90, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography. Using this resist pattern as a mask, dry etching or wet etching is performed. Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 88 is formed. An undoped AlGaN barrier layer 74 is located immediately below the gate electrode 88, and the junction between the gate electrode 88 and the undoped AlGaN barrier layer 74 is a Schottky junction.
　このように、この第２実施形態のＧａＮ系ＨＦＥＴの製造方法によれば、上記ＧａＮ系積層体７５上に形成したＳｉＮ保護膜７７を熱処理により改質してから、Ｔｉ/Ａｌ電極８５,８６をＧａＮ系積層体７５上に形成し、上記Ｔｉ/Ａｌ電極を熱処理してオーミック電極としてのソース電極８５,ドレイン電極８６とする。このように、ＳｉＮ保護膜７７を成膜して熱処理した後に、上記Ｔｉ/Ａｌ電極８５,８６を熱処理(オーミックアニール)し、オーミック電極としてのソース電極８５,ドレイン電極８６を形成する。これにより、上記Ｔｉ/Ａｌ電極８５,８６の熱処理時に電極メタルがＳｉＮ保護膜７７に拡散することを抑制できて、上記ＳｉＮ保護膜７７を経由するリーク電流を低減できる。よって、この第２実施形態によれば、上記熱処理したＳｉＮ保護膜７７による電流コラプスの抑制と上記ＳｉＮ保護膜７７を経由するリーク電流の低減とを両立できるＧａＮ系ＨＦＥＴを製造できる。 Thus, according to the GaN-based HFET manufacturing method of the second embodiment, the Si / N protective film 77 formed on the GaN-based stacked body 75 is modified by heat treatment, and then the Ti / Al electrodes 85, 86 are used. Is formed on the GaN-based laminate 75, and the Ti / Al electrode is heat-treated to form a source electrode 85 and a drain electrode 86 as ohmic electrodes. Thus, after forming the SiN protective film 77 and heat-treating, the Ti / Al electrodes 85 and 86 are heat-treated (ohmic annealing) to form the source electrode 85 and the drain electrode 86 as ohmic electrodes. Thereby, it is possible to prevent the electrode metal from diffusing into the SiN protective film 77 during the heat treatment of the Ti / Al electrodes 85 and 86, and to reduce the leakage current passing through the SiN protective film 77. Therefore, according to the second embodiment, it is possible to manufacture a GaN-based HFET that can achieve both suppression of current collapse by the heat-treated SiN protective film 77 and reduction of leakage current via the SiN protective film 77.
　なお、上記第２実施形態では、上記ＡｌＧａＮバリア層７４の厚さを第１実施形態のＡｌＧａＮバリア層４の厚さよりも薄くして、ソース電極８５,ドレイン電極８６をオーミックコンタクト可能としたが、上記ＡｌＧａＮバリア層７４の厚さをＡｌＧａＮバリア層４の厚さと同等とした場合には、ＡｌＧａＮバリア層７４のオーミックコンタクト部分に予めＳｉドープをしてｎ型化させることで電極のオーミックコンタクト可能をとしてもよい。 In the second embodiment, the thickness of the AlGaN barrier layer 74 is made thinner than the thickness of the AlGaN barrier layer 4 of the first embodiment so that the source electrode 85 and the drain electrode 86 can be in ohmic contact. When the thickness of the AlGaN barrier layer 74 is equal to the thickness of the AlGaN barrier layer 4, the ohmic contact portion of the AlGaN barrier layer 74 is preliminarily doped with Si so as to be n-type, thereby enabling ohmic contact of the electrode. It is good.
　また、上記第１,第２実施形態では、基板としてＳｉ基板を用いたが、サファイア基板を用いてもよい。また、上記ＧａＮ基板上にＡｌＧａＮ層を成長させる等のように、窒化物半導体からなる基板上に窒化物半導体層を成長させてもよい。また、適宜、バッファ層を基板と各層間に形成してもよい。また、ＧａＮチャネル層３,７３とＡｌＧａＮバリア層４,７４との間に、ＡｌＮで作製したヘテロ改善層を形成してもよい。また、上記ＡｌＧａＮバリア層４,７４上にＧａＮキャップ層を形成してもよい。また、上記実施形態では、ゲート電極１８,８８をＴｉＮで作製したが、ＷＮで作製してもよい。また、ゲート電極１８,８８をＰｔ/ＡｕやＮｉ/Ａｕで作製してもよい。 In the first and second embodiments, the Si substrate is used as the substrate, but a sapphire substrate may be used. Further, a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as growing an AlGaN layer on the GaN substrate. Further, a buffer layer may be appropriately formed between the substrate and each layer. A hetero improvement layer made of AlN may be formed between the GaN channel layers 3 and 73 and the AlGaN barrier layers 4 and 74. A GaN cap layer may be formed on the AlGaN barrier layers 4 and 74. Moreover, in the said embodiment, although the gate electrodes 18 and 88 were produced with TiN, you may produce with WN. The gate electrodes 18 and 88 may be made of Pt / Au or Ni / Au.
　また、上記第１,第２実施形態では、電流コラプスを抑制する保護膜をシリコン窒化膜(ＳｉＮ膜)の一層からなるＳｉＮ保護膜７,７７としたが、電流コラプスを抑制する保護膜を、ストイキオメトリなシリコン窒化膜よりもシリコンＳｉの比率の大きな下層ＳｉＮ膜とストイキオメトリな上層ＳｉＮ膜とで構成してもよい。この場合、ストイキオメトリな上層ＳｉＮ膜による電極メタルの拡散抑制と、シリコンＳｉの比率の大きな下層ＳｉＮ膜による電流コラプス抑制とを図れる。また、上記ＳｉＮ保護膜７,７７上にＳｉＯ２膜またはＡｌ２Ｏ３膜を形成してもよい。この場合、上記ＳｉＯ２膜またはＡｌ２Ｏ３膜によって上記電極の熱処理時にＳｉＮ保護膜７,７７へ電極メタルが拡散するのをさらに抑制でき、上記ＳｉＮ保護膜７,７７を経由してゲート電極１８,８８に流れるリーク電流をさらに低減できる。 In the first and second embodiments, the protective film that suppresses current collapse is the SiN protective film 7, 77 made of a single layer of silicon nitride film (SiN film). However, the protective film that suppresses current collapse is A lower SiN film having a larger silicon Si ratio than a stoichiometric silicon nitride film and a stoichiometric upper SiN film may be used. In this case, it is possible to suppress the diffusion of the electrode metal by the stoichiometric upper SiN film and to suppress the current collapse by the lower SiN film having a large silicon Si ratio. Further, an SiO 2 film or an Al 2 O 3 film may be formed on the SiN protective films 7 and 77. In this case, it is possible to further suppress the diffusion of the electrode metal to the SiN protective films 7 and 77 during the heat treatment of the electrode by the SiO 2 film or the Al 2 O 3 film, and the gate electrode via the SiN protective films 7 and 77. The leakage current flowing through 18, 88 can be further reduced.
　また、図６に示すように、下層ＳｉＮ膜５１とストイキオメトリである上層ＳｉＮ膜５２とＳｉＯ２膜５３とを順に積層した保護膜５０を電流コラプスを抑制する保護膜としてもよい。ここで、上記上層ＳｉＮ膜５２がストイキオメトリであるとは、ＳｉとＮが３：４の組成であることを意味している。上記保護膜５０によれば、上層ＳｉＮ膜５２がストイキオメトリであると共に上記上層ＳｉＮ膜５２上にＳｉＯ２膜５３を形成したことで、上記電極の熱処理時に上記保護膜５０の上層および下層ＳｉＮ保護層５２,５１へ電極メタルが拡散することを抑制でき、上記保護膜５０を経由するリーク電流をさらに低減できる。なお、上記下層ＳｉＮ膜５１は、ストイキオメトリなシリコン窒化膜よりもシリコンＳｉの比率の大きなＳｉＮ保護膜とすることで、ストイキオメトリなシリコン窒化膜に比べて電流コラプスの抑制を図れるが、上層ＳｉＮ膜５２と同様にストイキオメトリなシリコン窒化膜としてもよい。この場合、電極メタルの拡散抑制によるさらなるリーク電流低減を図れる。また、上記ＳｉＯ２膜５３の替わりにＡｌ２Ｏ３膜としてもよい。 Further, as shown in FIG. 6, a protective film 50 in which a lower SiN film 51, an upper SiN film 52 that is stoichiometry, and a SiO 2 film 53 are sequentially stacked may be used as a protective film that suppresses current collapse. Here, that the upper SiN film 52 is stoichiometric means that Si and N have a composition of 3: 4. According to the protective film 50, since the upper SiN film 52 is stoichiometry and the SiO 2 film 53 is formed on the upper SiN film 52, the upper and lower SiN layers of the protective film 50 are heat-treated during the heat treatment of the electrode. The diffusion of the electrode metal into the protective layers 52 and 51 can be suppressed, and the leakage current passing through the protective film 50 can be further reduced. Although the lower SiN film 51 is a SiN protective film having a silicon Si ratio larger than that of the stoichiometric silicon nitride film, the current collapse can be suppressed as compared with the stoichiometric silicon nitride film. Similar to the upper SiN film 52, a stoichiometric silicon nitride film may be used. In this case, the leakage current can be further reduced by suppressing the diffusion of the electrode metal. Further, instead of the SiO 2 film 53, an Al 2 O 3 film may be used.
　また、上記第１,第２実施形態では、一例として、上記ＳｉＮ保護膜７,７７の熱処理温度を５００℃とするとともに、電極１５,１６,８５,８６の熱処理温度を５００℃としたが、電極１５,１６,８５,８６の熱処理温度をＳｉＮ保護膜７７の熱処理温度よりも低くすることが望ましい。例えば、上記ＳｉＮ保護膜７７の熱処理温度が５００℃である場合、電極１５,１６,８５,８６の熱処理温度を５００℃よりも低い４５０℃とすることが望ましい。これにより、上記電極１５,１６,８５,８６を熱処理する際に、上記ＳｉＮ保護膜７,７７へ電極メタルが拡散することを抑制でき、上記ＳｉＮ保護膜７,７７を経由してゲート電極１８,８８に流れるリーク電流をさらに低減できる。 In the first and second embodiments, as an example, the heat treatment temperature of the SiN protective films 7 and 77 is set to 500 ° C., and the heat treatment temperature of the electrodes 15, 16, 85, and 86 is set to 500 ° C. It is desirable that the heat treatment temperature of the electrodes 15, 16, 85, 86 be lower than the heat treatment temperature of the SiN protective film 77. For example, when the heat treatment temperature of the SiN protective film 77 is 500 ° C., it is desirable that the heat treatment temperature of the electrodes 15, 16, 85, 86 be 450 ° C. lower than 500 ° C. Thereby, when the electrodes 15, 16, 85, 86 are heat-treated, the electrode metal can be prevented from diffusing into the SiN protective films 7, 77, and the gate electrode 18 passes through the SiN protective films 7, 77. , 88 can be further reduced.
　また、上記第１,第２実施形態では、上記オーミック電極としてのソース電極１５,８５、ドレイン電極１６,８６を、Ｔｉ層,Ａｌ層が順に積層されたＴｉ/Ａｌ電極としたが、Ｔｉ層,Ａｌ層,ＴｉＮ層が順に積層されたＴｉ/Ａｌ/ＴｉＮ電極としてもよい。また、上記Ａｌ層の代わりにＡｌＳｉ層やＡｌＣｕ層を用いてもよい。また、ソース電極,ドレイン電極としては、Ｈｆ/Ａｌ電極としてもよい。また、ソース電極,ドレイン電極としては、Ｔｉ/ＡｌまたはＨｆ/Ａｌ上にＮｉ/Ａｕを積層したものとしてもよく、Ｔｉ/ＡｌまたはＨｆ/Ａｌ上にＰｔ/Ａｕを積層したものとしてもよく、Ｔｉ/ＡｌまたはＨｆ/Ａｌ上にＡｕを積層したものとしてもよい。 In the first and second embodiments, the source electrodes 15 and 85 and the drain electrodes 16 and 86 as the ohmic electrodes are Ti / Al electrodes in which a Ti layer and an Al layer are sequentially stacked. A Ti / Al / TiN electrode in which an Al layer and a TiN layer are sequentially laminated may be used. Moreover, you may use an AlSi layer and an AlCu layer instead of the said Al layer. The source electrode and the drain electrode may be Hf / Al electrodes. Further, as the source electrode and the drain electrode, Ni / Au may be stacked on Ti / Al or Hf / Al, or Pt / Au may be stacked on Ti / Al or Hf / Al. It is good also as what laminated | stacked Au on Ti / Al or Hf / Al.
　また、上記第１,第２実施形態では、一例として、上記電極１５,１６,８５,８６のオーミックアニールの温度条件を、５００℃としたが、図８に示すように、上記電極１５,１６,８５,８６のオーミックアニールの温度が６００℃を超える７００℃にした場合、電極１５,１６,８５,８６のコンタクト抵抗(Ωｍｍ)が急増する。このため、上記電極１５,１６,８５,８６のオーミックアニールの温度は６００℃以下にすることが望ましい。例えば、上記オーミックアニールの温度を、４００℃～６００℃の範囲内で設定することが望ましい。 In the first and second embodiments, as an example, the temperature conditions for the ohmic annealing of the electrodes 15, 16, 85, 86 are set to 500 ° C. However, as shown in FIG. , 85, 86, the contact resistance (Ωmm) of the electrodes 15, 16, 85, 86 rapidly increases when the temperature of the ohmic annealing is set to 700 ° C. exceeding 600 ° C. Therefore, it is desirable that the ohmic annealing temperature of the electrodes 15, 16, 85, 86 is 600 ° C. or lower. For example, it is desirable to set the ohmic annealing temperature within a range of 400 ° C. to 600 ° C.
　また、上記第１実施形態では、リフトオフにより、ソース電極,ドレイン電極となるＴｉ/Ａｌ電極１５,１６を形成したが、図３に示すＳｉＮ保護膜７上およびリセス１２,１３と開口１０,１１を埋めるように、Ｔｉ,Ａｌ,ＴｉＮを順に全面スパッタし、フォトリソグラフィで上記ソース電極,ドレイン電極を形成すべき電極形成領域にレジストパターン(図示せず)を形成し、このレジストパターンをマスクとして、ドライエッチングまたはウエットエッチングを行なって、上記電極形成領域以外のＴｉ,Ａｌ,ＴｉＮ膜を除去して、ソース電極,ドレイン電極となるＴｉ/Ａｌ/ＴｉＮ電極１５,１６を形成してもよい。 In the first embodiment, the Ti / Al electrodes 15 and 16 that become the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 7 and the recesses 12 and 13 and the openings 10 and 11 shown in FIG. Then, Ti, Al, and TiN are sequentially sputtered to fill the electrode, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and the drain electrode are to be formed by photolithography, and this resist pattern is used as a mask. The Ti / Al / TiN electrodes 15 and 16 to be the source electrode and the drain electrode may be formed by performing dry etching or wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
　また、上記第２実施形態では、リフトオフにより、ソース電極,ドレイン電極となるＴｉ/Ａｌ電極８５,８６を形成したが、図１１に示すＳｉＮ保護膜７７上および開口７０,７１を埋めるように、Ｔｉ,Ａｌ,ＴｉＮ膜を順に全面スパッタし、フォトリソグラフィで上記ソース電極,ドレイン電極を形成すべき電極形成領域にレジストパターン(図示せず)を形成し、このレジストパターンをマスクとして、ドライエッチングまたはウエットエッチングを行なって、上記電極形成領域以外のＴｉ,Ａｌ,ＴｉＮ膜を除去して、ソース電極,ドレイン電極となるＴｉ/Ａｌ/ＴｉＮ電極８５,８６を形成してもよい。 In the second embodiment, the Ti / Al electrodes 85 and 86 to be the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 77 and the openings 70 and 71 shown in FIG. Ti, Al, TiN films are sequentially sputtered in order, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and drain electrode are to be formed by photolithography, and dry etching or etching is performed using this resist pattern as a mask. The Ti / Al / TiN electrodes 85 and 86 to be the source electrode and the drain electrode may be formed by performing wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
　この発明の製造方法におけるＧａＮ系半導体積層体は、ＡlxＩnyＧa1-x-yＮ(ｘ≧０、ｙ≧０、０≦ｘ＋ｙ＜１)で表されるＧａＮ系半導体層を含むものでもよい。すなわち、この発明の製造方法におけるＧａＮ系半導体積層体は、ＡｌＧａＮ、ＧａＮ、ＩｎＧａＮ等を含むものとしてもよい。 The GaN-based semiconductor laminate in the manufacturing method of the present invention may include a GaN-based semiconductor layer represented by Al x In y Ga 1-xy N (x ≧ 0, y ≧ 0, 0 ≦ x + y <1). . That is, the GaN-based semiconductor laminate in the manufacturing method of the present invention may include AlGaN, GaN, InGaN, and the like.
　また、上記実施形態では、ノーマリオンタイプのＨＦＥＴについて説明したがノーマリオフタイプでも同様の効果が得られる。また、ショットキーゲートで説明したが絶縁ゲート構造でも構わない。また、この発明で製造するＧａＮ系半導体素子は、上記実施形態のＨＦＥＴに限らず、他の構成の電界効果トランジスタであってもよい。 In the above embodiment, the normally-on type HFET has been described. However, the normally-off type can achieve the same effect. Moreover, although the Schottky gate has been described, an insulated gate structure may be used. Further, the GaN-based semiconductor element manufactured by the present invention is not limited to the HFET of the above embodiment, but may be a field effect transistor having another configuration.
　この発明の具体的な実施の形態について説明したが、この発明は上記実施形態に限定されるものではなく、この発明の範囲内で種々変更して実施することができる。 Although specific embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention.
　１,７１　Ｓｉ基板
　２,７２　アンドープＡｌＧａＮバッファ層
　３,７３　ＧａＮチャネル層
　４,７４　ＡｌＧａＮバリア層
　５,７５　ＧａＮ系積層体
　６,７６　２次元電子ガス
　７,７７　ＳｉＮ保護膜
　１０,１１,７０,７１　開口
　１２,１３　リセス
　１５,８５　Ｔｉ/Ａｌ電極(ソース電極)
　１６,８６　Ｔｉ/Ａｌ電極(ドレイン電極)
　１８,８８　ゲート電極
　２０,９０　開口
　５０　保護膜
　５１　下層ＳｉＮ膜
　５２　上層ＳｉＮ膜
　５３　ＳｉＯ２膜 1,71 Si substrate 2,72 Undoped AlGaN buffer layer 3,73 GaN channel layer 4,74 AlGaN barrier layer 5,75 GaN-based laminate 6,76 Two- dimensional electron gas 7,77 SiN protective film 10,11,70, 71 opening 12,13 recess 15,85 Ti / Al electrode (source electrode)
16,86 Ti / Al electrode (drain electrode)
18,88 Gate electrode 20,90 Opening 50 Protective film 51 Lower SiN film 52 Upper SiN film 53 SiO 2 film

Claims (3)

  1. 　ヘテロ接合を有するＧａＮ系積層体(５,７５)上にシリコン窒化膜(５１,５２,５３)を含む保護膜(５０)またはシリコン窒化膜からなる保護膜(７,７７)を形成し、
    　上記保護膜(７,７７)を熱処理し、
    　上記保護膜(７,７７)および上記ＧａＮ系積層体(５,７５)のうちの少なくとも上記保護膜(７,７７)の予め定められた領域をエッチングで除去して上記ＧａＮ系積層体(５,７５)のオーミック電極形成領域を露出させ、
    　上記ＧａＮ系積層体(５,７５)のオーミック電極形成領域にＴｉ/ＡｌまたはＨｆ/Ａｌを含む電極(１５,１６,８５,８６)を形成し、
    　上記電極(１５,１６,８５,８６)を熱処理してオーミック電極(１５,１６,８５,８６)にすることを特徴とするＧａＮ系半導体素子の製造方法。     A protective film (50) including a silicon nitride film (51, 52, 53) or a protective film (7, 77) made of a silicon nitride film is formed on a GaN-based laminate (5, 75) having a heterojunction,
    Heat-treating the protective film (7,77),
    Of the protective film (7, 77) and the GaN-based laminate (5, 75), at least a predetermined region of the protective film (7, 77) is removed by etching to remove the GaN-based laminate (5 , 75) is exposed,
    Forming electrodes (15, 16, 85, 86) containing Ti / Al or Hf / Al in the ohmic electrode forming region of the GaN-based laminate (5, 75);
    A method of manufacturing a GaN-based semiconductor device, wherein the electrode (15, 16, 85, 86) is heat-treated to form an ohmic electrode (15, 16, 85, 86).
  2. 　請求項１に記載のＧａＮ系半導体素子の製造方法において、
    　上記保護膜(５０)は、
    　上記ＧａＮ系積層体(５,７５)上に形成された下層シリコン窒化膜(５１)と、
    　上記下層シリコン窒化膜(５１)上に形成された上層シリコン窒化膜(５２)と、
    　上記上層シリコン窒化膜(５２)上に形成されたＳｉＯ２膜(５３)またはＡｌ２Ｏ３膜と
    を有し、
    　上記上層シリコン窒化膜(５２)は、ストイキオメトリなシリコン窒化膜であることを特徴とするＧａＮ系半導体素子の製造方法。     In the manufacturing method of the GaN-type semiconductor element of Claim 1,
    The protective film (50)
    A lower silicon nitride film (51) formed on the GaN-based laminate (5, 75);
    An upper silicon nitride film (52) formed on the lower silicon nitride film (51);
    An SiO 2 film (53) or an Al 2 O 3 film formed on the upper silicon nitride film (52),
    The method for manufacturing a GaN-based semiconductor device, wherein the upper silicon nitride film (52) is a stoichiometric silicon nitride film.
  3. 　請求項１または２に記載のＧａＮ系半導体素子の製造方法において、
    　上記電極(１５,１６,８５,８６)を熱処理する温度を、上記保護膜(７,７７)を熱処理する温度よりも低くしたことを特徴とするＧａＮ系半導体素子の製造方法。     In the manufacturing method of the GaN-type semiconductor element of Claim 1 or 2,
    A method for producing a GaN-based semiconductor device, wherein a temperature for heat-treating the electrodes (15, 16, 85, 86) is lower than a temperature for heat-treating the protective film (7, 77).
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