WO2013187267A1

WO2013187267A1 - Microstructure and method of manufacturing the same

Info

Publication number: WO2013187267A1
Application number: PCT/JP2013/065301
Authority: WO
Inventors: Takahisa Kato
Original assignee: Canon Kabushiki Kaisha
Priority date: 2012-06-14
Filing date: 2013-05-27
Publication date: 2013-12-19
Also published as: JP2013255974A; TW201401441A

Abstract

Provided is a method of manufacturing a microstructure, including: a preparing step of preparing a silicon substrate having a first surface and a second surface; a first step of forming a hole in the first surface; a second step of forming, in the hole, a film formed of a material which has selectivity for an etchant to form an etching region, the region having side portions and a bottom portion surrounded by the film; a third step of forming, on the first surface, a first layer which is a multilayer film including an insulating layer and a metal layer stacked therein, at least one of the insulating layer and the metal layer being patterned, in a state where a position of the pattern and a position of the etching region are adjusted; a fourth step of forming a first opening which pierces the first layer; and a fifth step of introducing the etchant through the first opening to remove the etching region.

Description

DESCRIPTION

Title of Invention :

MICROSTRUCTURE AND METHOD OF MANUFACTURING THE

SAME

Technical Field

[0001] The present invention belongs to the technical field of Micro-Electro-Mechanical Systems (MEMS), and relates to a microstructure using a semiconductor manufacturing technology and a method of manufacturing the same.

Background Art

[0002] A microstructure using the semiconductor manufacturing technology can enhance the drive speed and improve the detection accuracy by integrating a drive circuit and a detection circuit on the same substrate. A device is known in which a circuit is manufactured by a CMOS manufacturing technology and a multilayer wiring

structure that is used for electric connection of the CMOS circuit and that is formed of an insulating layer and a metal layer is a microstructure (NPL 1 and NPL 2). In such a device, a releasing step of etching out and removing a part of a substrate having the multilayer wiring structure is an important manufacturing step.

[0003] The releasing step enables the microstructure to be

movable with respect to the substrate (see, for example, PTL 1) or a through hole to be formed (see, for example, PTL 2) .

Citation List

Patent Literature

[0004] PTL 1: US Patent No. 6,458,615

PTL 2: US Patent No. 6,936,524

Non Patent Literature

[0005] NPL 1: Proceedings of the IEEE Sensors Conference (IEEE Sensors Ό5) PP 125-1282005

NPL 2: Proceeding of SPIE Vol. 7637 76371Z-8

Summary of Invention Technical Problem

[ 0006] However, methods of manufacturing a conventional

microstructure have the following problems.

[0007] hen a multilayer wiring structure is formed to be

movable by a releasing step of etching out and removing a part of a substrate having the multilayer wiring structure formed of an insulating layer and a metal layer, isotropic etching or anisotropic etching is used. In the case of isotropic etching, an opening through which an etchant can be introduced is provided in the multilayer wiring structure, and the substrate on the lower side of the multilayer wiring structure is etched. In this way, an air gap is formed between the

multilayer wiring structure and the substrate, and thus, the multilayer wiring structure can be formed to be movable or can be thermally insulated. However, the size of a region to be removed is controlled by the etching time, and thus, it is difficult to improve the processing accuracy. Further, it is difficult to shape the region to be removed in an arbitrary shape other than a circle.

[0008]On the other hand, in a method using anisotropic

etching, a part of the substrate can be removed by anisotropic dry etching from a surface opposite to the multilayer wiring structure. In the removed region, the multilayer wiring structure becomes movable. The region which becomes movable is a region which is a bottom of a portion etched by the thickness of the substrate. Generally, as the distance from an etching mask surface becomes larger, the shape accuracy tends to become lower, and thus, the processing accuracy of the region to be movable becomes lower. Further, the alignment between the multilayer wiring structure and the etching region be etched is required to be

performed on both surfaces of the substrate, and thus, it is also difficult to improve the alignment accuracy. [0009] In the case of forming a through hole in a substrate having a multilayer wiring structure, similar problems arise.

[0010] A through hole can be formed by forming an opening in the multilayer wiring structure and by carrying out anisotropic dry etching of the substrate with the opening being used as the etching mask. However, as the diameter of the through hole to be formed becomes smaller with respect to the multilayer wiring structure (that is, as the aspect ratio of the etching mask becomes higher) , straight traveling of an etchant which reaches the substrate is prevented to lower the

processing accuracy. Further, it is difficult to improve the alignment accuracy between the multilayer wiring structure and the through hole.

[ 0011 ] Further, conventionally, in a deflector array in which deflectors for deflecting charged particles are

arranged in an array using the multilayer wiring structure, a through hole for permitting charged particles to pass therethrough without being blocked is formed in the substrate. In order to shape a beam which enters the respective deflectors, an aperture array of arranged openings is used. As the pitches in the array and the diameter of the beam become smaller, the necessary alignment accuracy between the deflector array and the aperture array becomes higher, which causes the fabrication to be difficult.

[0012] The present invention has been made in view of the

problems described above, and it is an object of the present invention to provide a microstructure in which, when a part of a substrate having a multilayer wiring structure formed of an insulating layer and a metal layer is etched out, a region in a shape other than a circle can be easily removed and high processing accuracy is obtained, and a method of manufacturing the microstructure . Solution to Problem

[0013] According to an exemplary embodiment of the present

invention, there is provided a method of manufacturing a microstructure, including:

a preparing step of preparing a silicon substrate having a first surface and a second surface which is a surface opposite to the first surface;

a first step of forming a hole in the first surface of the silicon substrate;

a second step of forming, in the hole, a film formed of a material which has selectivity for an etchant, at which an etching region with side portions and a bottom portion surrounded by the film is to be formed;

a third step of forming, on the first surface of the silicon substrate, a first layer which is a multilayer film including an insulating layer and a metal layer stacked therein, at least one of the insulating layer and the metal layer being patterned, in a state where a position of the pattern and a position of the etching region are adjusted;

a fourth step of forming a first opening which pierces the first layer; and

a fifth step of introducing the etchant through the first opening to remove the etching region.

[ 0014 ] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. Advantageous Effects of Invention

[ 0015 ] According to the present invention, it is possible to realize the microstructure in which, when a part of the substrate having the multilayer wiring structure formed of the insulating layer and the metal layer is etched out, a region in a shape other than a circle can be easily removed and which can improve the processing accuracy, and the method of manufacturing the

microstructure. [ 0016] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. Brief Description of Drawings

[0017] FIGS. 1A and IB are sectional views of microstructures according to Example 1 of the present invention.

FIGS. 2A and 2B are top views of the microstructures according to Example 1 of the present invention.

FIGS. 3A, 3B, and 3C are flow charts for illustrating methods of manufacturing the microstructure according to embodiments of the present invention.

FIGS. 4A, 4B, 4C, 4D, and 4E are sectional views for illustrating a method of manufacturing the

microstructure according to Example 1 of the present invention.

FIGS. 5A, 5B, and 5C are sectional views for

illustrating the method of manufacturing the

microstructure according to Example 1 of the present invention .

FIGS. 6A, 6B, and 6C are sectional views for

illustrating another method of manufacturing the microstructure according to Example 1 of the present invention .

FIGS. 7A and 7B are top views for comparison of methods of manufacturing an etching region in the methods of manufacturing the microstructures according to Example 1 of the present invention.

FIGS. 8A and 8B are a top view and a sectional view of a microstructure according to Example 2 of the present invention .

FIGS. 9A, 9B, 9C, 9D, and 9E are sectional views for illustrating a method of manufacturing the

microstructure according to Example 2 of the present invention .

FIGS. 10A, 10B, and IOC are sectional views for

illustrating the method of manufacturing the microstructure according to Example 2 of the present invention .

FIGS. 11A and 11B are sectional views for illustrating exemplary structures of charged particle optical

systems according to Example 3 of the present invention. FIGS. 12A and 12B are top views for illustrating the exemplary structure of the charged particle optical systems according to Example 3 of the present invention. FIGS. 13A, 13B, 13C, 13D, and 13E are sectional views for illustrating a method of manufacturing the charged particle optical system according to Example 3 of the present invention.

FIGS. 14A, 14B, and 14C are sectional views for

illustrating the method of manufacturing the charged particle optical system according to Example 3 of the present invention.

Description of Embodiments

[0018 ] Methods of manufacturing a microstructure according to this embodiment have three flows illustrated in FIGS. 3A to 3C.

[0019] First, the flow illustrated in FIG. 3A is described.

[0020] In a substrate preparing step, a silicon substrate

having first and second surfaces which are in parallel with each other is prepared.

[0021] ith regard to the first and second surfaces, a surface on which an integrated circuit formed of the silicon substrate and used for manufacturing a semiconductor is to be formed can be the first surface, and the opposite surface can be the second surface.

[0022] Then, a hole forming step (first step) is carried out.

In this step, a hole in a shape according to the

contour of a region which is removed later (hereinafter referred to as etching region) is formed in the silicon substrate from the first surface side.

[0023] The hole can be formed by dry etching of the silicon

substrate using an etching mask formed by lithography. [ 0024 ] Further, when a depth is a dimension in the direction of the normal to the first surface, the depth of the hole is substantially the same as the depth of the etching region.

[0025] Then, an oxide film forming step (second step) is

carried out.

[0026] In this step, a film formed of a material which has

selectivity for an etchant is formed in the etching region at least on an inner wall surface of the hole. This film is an oxide film such as a silicon oxide film. The oxide film can be formed by thermal oxidation, chemical vapor deposition (CVD) , or sputtering.

[0027] This step defines the shape of both of side portions

and a bottom portion of the etching region with the material which has selectivity for an etchant.

[ 0028 ] Further , in this step, an alignment mark for adjusting . the positional relationship with a pattern in the subsequent first layer forming step is also formed.

[0029] Then, the first layer described above forming step

(third step) is carried out.

[0030] A first layer is a multilayer film in which an

insulating layer and a metal layer are stacked. At least any one of the insulating layer and the metal layer is patterned.

[0031] The first layer can be realized as a multilayer wiring layer used for interlayer wiring of an integrated circuit .

[0032] The first layer is formed under a state in which the

'position thereof is adjusted with respect to the

alignment mark formed in the oxide film forming step. The insulating layer which forms the first layer can be formed of a material selected from the group consisting of silicon oxide, carbon, and nitrogen. Typically, the insulating layer is formed of silicon oxide. On the other hand, the metal layer can be formed of a metal selected from a group consisting of copper, aluminum, tungsten, titanium, and tantalum.

[0033] Further, in this step, a CMOS circuit portion for

controlling the microstructure, detecting a signal, or computing can also be formed on the substrate.

[0034] Then, a first opening forming step (fourth step) is

carried out.

[0035] A first opening is a through hole which pierces the

first layer. The first opening is held in contact with the etching region on the first surface.

[0036] With regard to the size relationship between the cross- sectional areas of the first opening and the etching region on the first surface, the cross-sectional area of the etching region includes the cross-sectional area of the first opening.

[ 0037 ] Typically, the first opening can be formed by forming an etching mask on an outermost surface of the first layer, or forming in advance the metal layer in the first layer in the shape of the etching mask and then carrying out dry etching of the insulating layer.

[0038] As an etching gas used in the dry etching, for example, a gas such as CHF₃ or CF₄ can be used.

[0039] Then, a releasing step (fifth step) is carried out.

[0040] The etchant is introduced through the first opening, and the etching region is etched out. The introduced etchant does not etch the oxide film and the insulating layer, and thus, the etching stops at the oxide film.

[0041] Therefore, the etching region can be etched out into the shape in which the side portions and the bottom portion are defined in advance. Such etching can be realized by isotropic dry etching using a gas such as XeF₂ or SF₆.

[0042] Further, according to the manufacturing method of this embodiment, a sacrificial structure formed of a metal layer can be formed in the first layer forming step at a first opening forming portion.

[0043] Then, by, removing the sacrificial structure in the first opening forming step, the first opening can be formed.

[0044] The metal layer at the first opening forming portion is continuously formed over a range from the outermost surface of the first layer to the first surface.

[0045] In this case, the metal layer is formed of aluminum,

copper, or tungsten, and thus, the etching can be carried out using the following typical etchants.

[0046] When the metal layer is formed of aluminum, a liquid

mixture of phosphoric acid, nitric acid, and acetic acid can be used, when the metal layer is formed of copper, an aqueous solution of iron (III) chloride and hydrochloric acid can be used, and, when the metal layer is formed of tungsten, hydrogen peroxide water can be used, for example.

[0047] All of these etchants hardly etch the insulating layer which forms the first layer, and thus, only the metal layer can be removed to form the first opening.

[0048] This has the following effects.

[0049] First, the accuracy of the position at which the first opening and the etching region are brought into contact with each other on the first surface can be enhanced. When etching from the etching mask on the outermost surface of the first layer through the first opening is carried out, a tilt error, an opening diameter error, and the like are caused in the etching, and thus, an error develops in shapes of the cross section and the position between the etching mask and the first surface.

[0050] On the other hand, when the first opening is obtained by removing the metal layer formed in the first layer, the position at which the first opening and the etching region are connected on the first surface is determined according to the processing accuracy when a metal via is formed in the insulating layer in the lowermost layer of the first layer. This is sufficiently thinner compared with the thickness of the first layer, and thus, the tilt error, the opening diameter error, and the like caused in the etching can be reduced.

[0051] Secondly, even when the aspect ratio of the first

opening (In this case, the aspect ratio is defined as a ratio between a representative dimension such as the width in cross section of the first opening on the first surface and the thickness of the first layer.

When the ratio is large, the cross-sectional area is small and the thickness is large.) becomes larger, the first opening can be formed with high accuracy.

[0052] When etching from the etching mask on the outermost

surface of the first layer through the first opening is carried out, side etching may occur to increase the dimensions of the opening. Therefore, as the aspect ratio becomes higher, the difficulty in the processing increases. On the other hand, by forming the metal layer in advance, even when the aspect ratio becomes higher, the first opening can be formed.

[0053] his becomes an important problem when the first layer is at a thickness of several tens of micrometers and the etching region is at a width of several micrometers. By forming the first opening by etching the metal layer as described above, the releasing step can be carried out with high accuracy even when the dimension of the etching region is as described above.

[ 0054 ] Further , even when the thickness of the first layer or the size in cross section of the etching region is changed, and the cross section, the depth, and the number of the first openings to be formed are changed accordingly, the manufacturing conditions in the first opening forming step are applicable to a wide range of design values with hardly any change.

[ 0055 ] Further, according to the manufacturing method of the present invention, the substrate preparing step can be a step of preparing a silicon on insulator substrate (SOI substrate) . [0056] An SOI substrate is formed of a first silicon layer including the first surface, a second silicon layer including the second surface, and an embedded oxide film sandwiched between the first and second silicon layers .

[0057] In this case, the hole formed in the hole forming step is formed so as to pierce the first silicon layer but not to pierce the embedded oxide film. This enables the bottom of the hole to be defined by silicon oxide which has selectivity for the etchant used to etch out the etching region.

[0058] Further, the hole is formed with the embedded oxide film being used as an etching stop. Therefore, the influence of variations in etching rate and in etching start point when the hole is formed can be lowered. Therefore, the dimension in the thickness direction of the etching region can be defined with high accuracy.

[ 0059] Further , variations in thickness of the etching region in the substrate can be reduced. Further, variations in depth of the hole can be separated as variations in thickness of the first silicon layer in the SOI substrate, and thus, error factors can be separated among the respective steps. Therefore, development of production control and of the manufacturing method can be parallelized or simplified.

[0060] Further, the bottom of the hole can be made flat. This can increase a portion having a uniform thickness. For example, when an air gap is provided between the substrate and the first layer in the releasing step, both variations in dimensions in one air gap and variations in dimensions in the substrate can be reduced.

[0061] Further, when the first silicon layer is prepared to have a desired thickness, the manufacturing method can carry out the etching processing in the releasing step with high accuracy with regard to an etching region the thickness of which is as large as several hundreds of micrometers and with regard to an etching region the thickness of which is as small as 1 μπι or less.

[0062] Further, according to the manufacturing method of this embodiment, in the hole forming step, the hole can be formed so as to have a width along the contour of the etching region toward the first silicon layer of the SOI substrate.

[0063] In this case, the hole is not formed in the etching region, and the first silicon layer remains in the etching region. Then, in the oxide film forming step, the formed hole is filled with the oxide film.

[0064] The oxide film can be filled using any one of thermal oxidation, CVD, sputtering, application, baking, and a combination thereof.

[0065]After the filling, the first surface is planarized.

This planarization can be carried out using chemical mechanical polishing (hereinafter referred to as CMP) . In this case, in the hole forming step, a protective film can be formed on the first surface of the silicon substrate before the hole is formed so that, in the planarizing step, no defect is caused in the silicon substrate .

[ 0066] Further, such a protective film can be used as a

reference position of the planarization to enhance the accuracy of the planarizing step. The protective film can be realized as a silicon oxide film, a silicon nitride film, or a combination thereof. After the planarization, the hole is filled with silicon oxide, and the etching region is surrounded by the oxide film.

[0067] In this way, the side portions of the etching region can be surrounded by silicon oxide which is filled into the hole, and the bottom portion of the etching region can be covered with the embedded oxide film.

[0068] Filling the hole with the silicon oxide film in this way has the following effects. [0069] First, the shape and the area of the etching region can be changed without changing the width of the hole.

Therefore, even if the design of the etching region is changed, change in processing conditions in the hole forming step and in the oxide film forming step is small, and thus the manufacturing method is adaptable to a wide processible range. In particular, even when the etching region becomes larger, the region of the hole does not become so large, and thus, etching error factors in the dry etching such as heating and

insufficient removal of a by-product of the etching due to the excessively large etching region can be reduced.

[0070] Further, by causing the width of the hole to be as

constant as possible, change in. etching rate with respect to the width of the etching mask can be reduced, and thus, variations in depth of the hole in the

silicon substrate can also be reduced. Further, the flat silicon substrate surface remains in the etching region and the area of the hole to be planarized is small, and thus, even if a planarization error occurs in the planarizing step, the flatness of the entire silicon substrate can be maintained at a high level.

[0071] Further, according to the manufacturing method of this embodiment, in the hole forming step, a hole which is not in a shape along the contour but in a shape similar to that of the etching region can be formed. Then, in the oxide film forming step, the silicon oxide film is formed on the inner wall of the hole.

[0072] In this case, the silicon oxide film can be formed

using any one of thermal oxidation, CVD, sputtering, application, baking, and a combination thereof. After that, a filling material is filled. As the filling material, silicon can be used. Silicon can be filled into the hole using epitaxy, CVD, sputtering, or the like.

[0073] Further, any one of amorphous silicon and polycrystalline silicon can be used. After that, the first surface is planarized. This planarization can be carried out using CMP. Further, similarly to the above description, a protective film for the CMP step can be provided in the hole forming step.

[0074] After the planarization, the hole is filled with the filling material, and the shape of the filling material becomes the shape of the etching region. The silicon oxide film is formed on the interface between the filling material and the silicon substrate.

[0075] Oxidizing the inner wall of the hole and then filling the hole with the filling material in this way has the following effects. First, even when the ratio between the cross-sectional area on the first surface and the depth of the etching region (Hereinafter referred to as the aspect ratio of the etching region. As the aspect ratio becomes higher, the etching region becomes smaller and deeper.) becomes higher, the etching region can be formed with high accuracy.

[0076] This is because, compared with a case where the hole is formed so as to have the width along the contour of the etching region as described above, the aspect ratio of the hole to be formed can be kept low.

[0077] hen the aspect ratio of the hole is high, straight

traveling of an etchant such as ions or radicals tends to be lost, and thus, processing with high accuracy becomes difficult. By keeping the aspect ratio of the holes low, the processing accuracy can be improved.

[0078] In particular, in a microstructure in which the silicon oxide film is removed after the releasing step and the remaining silicon structure is used, when the hole is formed along the contour, the width of the hole is the dimension of the silicon structure.

[0079] Therefore, when the aspect ratio of the etching region becomes higher, the aspect ratio of the hole becomes extremely higher, and thus, the processing accuracy is lowered. By forming the hole having the same shape as that of the etching region, oxidizing the inner wall thereof, and then, filling the hole with the filling material, such a problem can be solved.

[0080] Further, by using silicon as the filling material, the filling material can have satisfactory etching

selectivity with respect to the insulating layer and the metal layer of the first layer and the silicon oxide film. When silicon is removed, by selecting an etchant such as XeF₂, the filling material can be

removed without etching out the insulating layer, the metal layer, and the silicon oxide film. In particular, when a CMOS circuit portion which functions as a

circuit is formed in the first layer forming step, the filling material can be a material which is compatible with the CMOS step.

[0081] Further, according to the manufacturing method of this embodiment, the CMOS circuit portion which functions as a circuit can be formed in the first layer forming step.

[0082] In this case, as the first layer, the multilayer wiring layer of the CMOS circuit portion can be used. The microstructure and the circuit can be integrated on the silicon substrate. The circuit can perform drive control and detect a signal with regard to the

microstructure. Such integration improves the

impedance characteristics, and thus, higher speed and higher sensitivity can be realized.

[0083] Further, a combination with a serial-parallel

conversion circuit, an active matrix element, and the like reduces the number of wirings for connection to the outside, and thus, a large-scale array can be formed .

[0084] Further, a system including a module for controlling

the microstructure with combination of a logic circuit and a memory can be formed on the substrate to further reduce the size and the cost. [0085] Next, the flow illustrated in FIG. 3B is described.

[0086] The flow illustrated in FIG. 3B is different from that illustrated in FIG. 3A in that, after the releasing step, an insulating layer removing step (sixth step) is carried out. In the insulating layer removing step, a part of the insulating layer of the first layer is etched out to widen the region of the first opening.

[0087] In this case, the etching mask can be formed on the outermost surface of the first layer by

photolithography, or the metal layer in the first layer can be formed into the shape of the etching mask in advance and used as the etching mask.

[0088] The insulating layer can be etched by dry etching using a gas similar to the above-mentioned dry etching.

Further, the silicon oxide film which defines the etching region can be removed together with the

widening of the first opening.

[0089] In this case, simultaneously with removing the silicon oxide film using hydrofluoric acid or buffered

hydrofluoric acid, the size of the first opening can be increased. By increasing the size of the first opening after the releasing step, the releasing step with high accuracy according to the present invention can be carried out, and still, portions of the first layer except for the etching region can be processed into an arbitrary shape.

[0090] In particular, by forming in advance the metal layer in the first layer into the shape of the etching mask, a fine microstructure can be manufactured with high accuracy under a state of being satisfactorily aligned with the etching region. Further, the silicon oxide film can be removed at the same time, and thus, the number of steps can be reduced.

[0091] Further, the process flow illustrated in FIG. 3C is described .

[0092] The flow illustrated in FIG. 3C is different from that illustrated in FIG. 3A in that, after the first layer forming step, a second opening forming step (seventh step) is carried out and then the process proceeds to the first opening forming step. The substrate

preparing step is a step of preparing an SOI substrate formed of a first silicon layer including the first surface, a second silicon layer including the second surface, and an embedded oxide film sandwiched between the first and second silicon layers.

[0093] In the second opening forming step, a second opening which pierces the second silicon layer from the second surface side is formed. In this case, the through hole can be formed in the second silicon layer at a

thickness of several hundreds of micrometers to several tens of micrometers typically using silicon deep dry etching .

[ 0094 ] Forming the second opening before the first opening forming step and the releasing step in this way has the following effects.

[0095] First, the fine microstructure formed in the first

layer can be prevented from being broken in the second opening forming step.

[0096] The first layer and the second opening are on opposite sides, and thus, in the second opening forming step, the first layer is a surface in contact with a wafer chuck and the like. The microstructure is not shaped in the second opening forming step, thus, breakage of the microstructure by being brought into contact with the wafer chuck or a holder can be prevented by using a simple protective film or the like.

[ 0097 ] Secondly, a portion between the metal layer and the insulating layer and the CMOS circuit portion in the first layer may be broken or may deteriorate in

performance under the influence of a cleaning step, an etching step, or the like in the manufacturing steps. Thus, by carrying out the step of forming the opening in the first layer and the step of removing the substrate as late as possible in the entire steps, such damage during the manufacturing steps can be reduced. Therefore, the microstructure of the present invention can be formed with high yield.

[ 0098 ] Further, a support layer can be formed on the second opening in this step. The support layer acts as a reinforcement of a portion which has been thinned by the formation of the second opening, and as a

prevention against going around of an etchant to the second surface side of the substrate during the etching in the subsequent releasing step or insulating layer removing step.

[0099] As the support layer, depending on the etching

selectivity in the subsequent releasing step, and depending on the size of the second opening, a metal, an organic substance such as a resist or a resin, an oxide, an inorganic dielectric, or the like can be selected.

[0100] In the case of a metal, a film can be formed of gold, aluminum, copper, tungsten, chromium, molybdenum, or the like by vapor deposition, sputtering, or CVD.

[0101] In the case of an organic substance, a film can be

formed of a photoresist, parylene, a polyimide, or the like by spin coating, vapor deposition, CVD, or the like. In particular, in the case of a metal, heat conduction from the rear surface of the etching

improves in the first opening forming step, and thus, the etching rate distribution and side etching can be reduced .

[0102] In particular, for molybdenum, there is an etchant

which has high selectivity with respect to copper and aluminum that are popularly used for the silicon oxide film and the first layer, and thus, when the protective film is finally removed, the protective film can be removed without etching these materials. 1

Example 1

[0103] FIGS. 1A and IB and FIGS. 2A and 2B are sectional views and top views, respectively, of membrane structure sensors which are microstructures of this example.

[0104] As illustrated in FIG. 1A, the membrane structure

sensor includes a microstructure 7 having a membrane structure which is provided on a silicon substrate 1 having a first surface 2 and a second surface 3 via an air gap 9.

[0105] Top views of sections taken along the lines A-A and B-B of FIG. 1A correspond to FIGS. 2A and 2B, respectively.

[0106] Note that, unless otherwise specified, the dimension in the direction of the normal to the first surface 2 is hereinafter referred to as the thickness or the depth.

[0107] A capacitor functions under a state in which the

microstructure 7 and the silicon substrate 1 act as electrodes through the intermediation of the air gap 9.

[0108] When bias voltage is applied to the microstructure 7

and the silicon substrate 1, vibrations and

displacement of the microstructure 7 can be detected, as change in capacitance of the capacitor by a detection circuit (not shown) .

[0109] Therefore, when the microstructure 7 is displaced by

pressure of the atmosphere, the microstructure 7 can function as a pressure sensor, and, when the

microstructure 7 is vibrated by sound in the atmosphere or a surrounding medium, the microstructure 7 can function as a microphone. In particular, the air gap 9 is held at a lower pressure than that of the atmosphere, and ohmic attenuation which accompanies vibrations of the microstructure 7 can be reduced.

[ 0110 ] Further, the microstructure 7 has a membrane structure which is formed by forming a part of a first layer 4 that is a stacked structure of metal layers 5 and insulating layers 6 so as to have a mesh structure as illustrated in FIG. 1A and FIG. 2A, and then applying a coating 8.

[0111] The metal layers 5 are formed of copper, while the

insulating layers 6 are formed of silicon oxide.

Further, as the coating 8, a vapor deposited polymer or an inorganic dielectric film formed by CVD can be used. In this example, the coating 8 is a silicon nitride film formed by plasma CVD.

[ 0112 ] Further, the air gap 9 is space formed after the

coating 8 is applied to a region whose upper portion, side portions, and bottom portion are surrounded by a surface of the first layer 4 on the first surface 2 side and an oxide film 10 or an embedded oxide film layer 21.

[0113]As illustrated in FIGS. 1A and IB and FIGS. 2A and 2B, the microstructure 7 and the air gap 9 are in the shape of a rectangle as seen from above. The air gap 9 is in the shape of a square of 230 μπι><230 μιτι.

[0114] Therefore, the movable membrane structure of the

microstructure 7 is also 230 μπ\^χ230 μπι. Further, with regard to the thickness of the microstructure 7, the total thickness of the metal layer 5, the insulating layer 6, and the coating 8 is 1.2 μπι. Among the layers, the metal layer 5 is at a thickness of about 0.2 μιη.

Further, the thickness of the air gap 9 is 1 μπι.

[0115] Next, a method of manufacturing the microstructure 7 of this example is described with reference to FIGS. 4A to 4E and FIGS. 5A to 5C.

[0116] First, as illustrated in FIG. 4A, the silicon substrate 1 having the first surface 2 and the second surface 3 is prepared.

[0117] Then, as illustrated in FIG. 4B, a pad layer 12 and a protective film 13 are formed. In this example, the pad layer 12 is formed by thermal oxidation of the silicon substrate 1, and, as the protective film 13, a silicon nitride film is formed thereon by CVD.

[0118] Then, the protective film 13, the pad layer 12, and the 1

silicon substrate 1 are sequentially etched into the shape of a pattern formed by photolithography. Then, a hole 11 is formed on the first surface 2 side of the silicon substrate 1. In this example, as illustrated in FIG. 4B, the hole 11 is formed as a recess which does not pierce the silicon substrate 1.

[0119] Then, as illustrated in FIG. 4C, portions of the

silicon substrate 1 which are inner wall surfaces of the hole 11 are thermally oxidized.

[0120] In this step, the oxide film 10 is formed on side

portions and a bottom portion of the hole 11. In this case, the bottom portion of the hole 11 is a surface which is in parallel with the first surface 2 of the inner walls of the hole 11, and the side portions of the hole 11 are side walls which define a cross- sectional shape taken along a surface in parallel with the first surface 2 (hereinafter simply referred to as cross-sectional shape) . Therefore, as indicated by a broken line in FIG. 4C, an etching region 14 which is defined by the oxide film 10 is formed.

[0121] Then, as illustrated in FIG. 4D, as a filling material 15, a polysilicon film is formed by CVD.

[0122] The filling material 15 is formed in the hole and on the protective film 13. After that, planarization is performed by chemical mechanical polishing, to thereby remove portions of polysilicon other than that which fills the hole.

[0123] The protective film 13 functions as a stop layer in this polishing processing, and at the same time, functions as a protective film which prevents breakage and a defect of the silicon substrate 1 in the

polishing step.

[0124] After the planarizing processing, the protective film

13 and the pad layer 12 are removed to form the filling material 15 surrounded by the oxide film 10 as

illustrated in FIG. 4D. [0125] Then, as illustrated in FIG. 4E, the first layer 4 in which the metal layers 5 and the insulating layers 6 are alternately stacked is formed on the first surface 2.

[0126] The metal layers are formed of copper, and the

insulating layers are formed of silicon oxide. In this example, a multilayer wiring layer which is used in an ordinary CMOS step is used.

[0127] ith regard to the pattern of the metal layers 5, as illustrated in FIG. 4E, the lowermost layer thereof is in advance formed so as to have the mesh structure illustrated in FIG. 2A.

[0128] Further, the layout is designed so that the metal

layers 5 are not formed immediately above the mesh structure to allow etching of this portion. Further, the first layer 4 is formed while being aligned with reference to the alignment mark which is formed

simultaneously with the filling material 15 surrounded by the oxide film 10 in the above-mentioned steps illustrated in FIGS. 4A to 4D.

[0129] Therefore, as illustrated in the FIG. 4E, the center of the mesh structure and the center of the etching region 14 are coincident with each other with high accuracy.

[0130] Then, as illustrated in FIG. 5A, an etching mask 16 is formed on the uppermost surface of the first layer 4.

[0131] In this example, the etching mask 16 is a photoresist.

Then, as illustrated in FIG. 5A, dry etching is carried out using a gas which can etch out the insulating layers 6 to form a first opening 17. In this example, the gas is CHF₃.

[0132] In this case, the first opening 17 is formed with the metal layer 5 of the mesh structure illustrated in FIG. 2A being the etching mask. Therefore, the position of the first opening 17 and the position of the filling material 15 can be determined with high accuracy. The first opening 17 is a through hole which pierces the first layer 4 to reach the filling material 15.

[0133] hen, as illustrated in FIG. 5B, the filling material 15 is removed. The filling material 15 can be removed by introducing through the first opening 17 an etchant which can isotropically etch out the filling material 15.

[0134] In this example, in order to remove polysilicon which is the filling material 15, XeF₂ gas is introduced through the first opening 17.

[0135] In this way, the filling material 15 which is formed over an area that is larger than the area of the first opening 17 can be removed using the first opening 17.

[0136] The etching rate of silicon in XeF₂ gas is high, but silicon oxide is hardly etched by XeF₂ gas, and thus, the oxide film 10 is an etching stop in this step.

Therefore, the region defined by the oxide film 10 is removed to be the air gap 9. Then, as illustrated in FIG. 5C, a silicon nitride film is formed as the coating 8 by CVD.

[0137] In the way described above, the microstructure

illustrated in FIG. 1A can be manufactured.

[0138] In this example, without strictly controlling the step of removing the filling material 15, the silicon substrate 1 can be removed with high accuracy to form the movable membrane structure by the air gap 9.

[0139] First, by forming the hole 11 before the first layer 4 is formed, the processing accuracy of the etching region can be improved. In particular, the side portions and the bottom portion of the etching region 14 are surrounded by the oxide film 10, and thus, both the cross-sectional shape and the depth of the air gap 9 can be processed with high accuracy.

[0140] Secondly, by filling the filling material 15

(polysilicon) which has etching selectivity with respect to the metal layers 5, the insulating layers 6, and the oxide film 10, removal with high processing accuracy can be performed by the isotropic etching.

[0141] In particular, silicon has high etching selectivity with respect to the metal layers 5, the insulating layers 6, and the oxide film 10 when XeF₂ is used as an isotropic dry etchant. Further, silicon is a material which is compatible with the CMOS step, and thus, a fine microstructure can be formed using the multilayer wiring layer of the CMOS as the first layer 4.

[0142] Further, the step is a dry step, and thus, a phenomenon that portions of the microstructure stick to each other to be broken after the air gap 9 is formed is less liable to occur., and the yield in the manufacturing steps can be high.

[0143] Further, although isotropic etching is used, the region to be removed can be in an arbitrary shape other than a circle such as a rectangle or a polygon. Further, in the manufacturing method, change in forming position and size of the first opening 17 can be less liable to result in error in the etching region.

[0144 ] Further, the pattern formed in the first layer 4 can be formed in alignment with the filling material 15 as the etching region with high accuracy. The positional relationship between the microstructure 7 and the air gap 9 therefore can be accurate in the manufacture, and thus, variations in mechanical characteristics of the microstructure 7 can be reduced.

[0145] As the size of the air gap 9 increases, the membrane structure becomes larger to reduce the stiffness thereof. Further, when misalignment is caused between the center of the membrane structure and the center of the air gap 9, the mechanical position at which the membrane structure is grounded may be substantially misaligned or the membrane structure may not be

satisfactory fixed to lose the vibration energy of the membrane structure.

[0146] However, according to the manufacturing method of this example, when manufactured, the first layer 4 is aligned with respect to the etching region which is defined in advance, and thus, the positional

relationship between the microstructure 7 and the air gap 9 is satisfactory. Further, the oxide film 10 is formed both on the side portions and the bottom portion of the etching region 14. Therefore, both the cross- sectional shape and the depth of the air gap 9 which is formed between the microstructure 7 and the silicon substrate 1 can be processed with high accuracy.

[0147] ext, another method of manuf cturing the

microstructure 7 of this example is described with reference to FIG. IB and FIGS. 6A to 6C.

[0148] A microstructure illustrated in FIG. IB is formed of structural components which are substantially similar to those illustrated in FIG. 1A. However, the

microstructure illustrated in FIG. IB is different in that the substrate on which the microstructure 7 is formed is an SOI substrate including a first silicon layer 19, a second silicon layer 20, and the embedded oxide film layer 21. Further, the oxide film 10 is not formed on the bottom portion but is formed only on the side walls of the air gap 9. The embedded oxide film layer 21 of the SOI substrate is formed on the bottom portion of the air gap 9.

[0149] The structure is otherwise the same, and top views of sections taken along the lines A-A and B-B of FIG. IB are as illustrated in FIGS. 2A and 2B, respectively.

[0150] FIGS. 6A to 6C are sectional views of steps for

illustrating the method of manufacturing the

microstructure 7 illustrated in FIG. IB. FIGS. 6A to 6C particularly illustrate points different from those in the manufacturing method illustrated in FIGS. 4A to 4E and FIGS. 5A to 5C. FIGS. 6A to 6C with regard to the microstructure illustrated in FIG. IB correspond to FIGS. 4A to 4D. [0151] In the manufacturing method illustrated in FIGS. 6A to

6C, first, as illustrated in FIG. 6A, the SOI substrate, which includes the first silicon layer 19 including the first surface 2, the second silicon layer 20 including the second surface 3, and the embedded oxide film layer 21 located therebetween, is prepared.

[0152] hen, as illustrated in FIG. 6B, after the pad layer 12 and the protective film 13 are formed, the hole 11 is formed so as to pierce the first silicon layer 19. In this case, the hole 11 is dry etched with the embedded oxide film layer 21 being used as an etching stop layer.

[0153] The dry etching of the hole 11 can be carried out by

deep dry etching of silicon. Differently from the case illustrated in FIG. 4B, the hole 11 is not formed in an area which is to be the etching region 14 later, but is formed so as to have a width along the contour of the etching region 14.

[0154] Then, as illustrated in FIG. 6C, the hole 11 is filled with the oxide film 10.

[0155] In this example, the step of forming the oxide film 10 is carried out by forming a silicon oxide film by CVD.

[0156] After that, the silicon oxide film formed at portions other than in the hole 11 is removed and the remaining silicon oxide film is planarized using chemical

mechanical polishing. After the pad layer 12 and the protective film 13 are removed, a structure illustrated in FIG. 6C is obtained.

[0157] In this way, the structure in which both the side

portions and the bottom portion of the etching region 14 indicated by a broken line are surrounded by silicon oxide can be formed.

[0158] Next, for comparison of methods of manufacturing the

etching region in the manufacturing method illustrated in FIGS. 4A to 4E and the manufacturing method

illustrated in FIGS. 6A to 6C, top views along the first surface 2 of FIG. 4D and FIG. 6C each illustrating a state immediately before the formation of the first layer 4 are shown as FIGS. 7A and 7B, respectively. FIGS. 4A to 4E and FIGS. 6A to 6C are sectional views taken along the line D-D of FIG. 7A and the line E-E of FIG. IB, respectively.

[0159] In FIG. 7A, as the etching region 14, the filling

material 15 is formed.

[0160] On the other hand, in FIG. 7B, the oxide film 10 is formed so as to have a width along the contour of the etching region 14. The etching region 14 is a part of the silicon substrate 1. As described above, not forming the filling material 15 in the etching region 14 but forming the oxide film 10 along the contour of the etching region 14 also enables introduction of an etchant through the first opening 17 to form the air gap 9 with high accuracy.

[0161] In this case, there is no step of forming the filling material 15, and thus, the number of the manufacturing steps can be reduced.

[0162] Further, a part of the silicon substrate 1 which is a planarized surface in advance is to be the etching region 14, and thus, the planarizing step can be simplified .

[0163] Still further, even if the size of the etching region 14 is changed in various ways depending on the design, it is enough to change only the layout along the contour without changing the width of the hole 11.

[0164 ] herefore, the manufacturing steps can be applicable to various shapes of the etching region 14 almost without changing the process conditions of the hole 11 and the oxide film 10.

[0165] On the other hand, in the case where the filling

material 15 illustrated in FIG. 7A is the etching region 14, when the depth becomes large with respect to the size of the etching region 14 (that is, when the aspect ratio becomes high) , the processing accuracy can be improved and the degree of difficulty in processing can be reduced.

- [0166] hen comparison of the aspect ratio of the hole 11 is made between FIGS. 7A and 7B, the aspect ratio can be reduced in the structure illustrated in FIG. 7A.

[ 0167 ] Therefore, when the aspect ratio of the etching region 14 becomes higher, by using the filling material 15, the aspect ratio of the hole 11 can be lowered to obtain satisfactory processing. Typically, the aspect ratio is high when the aspect ratio is 3 or more.

[ 0168 ] Further, even when an ordinary silicon substrate 1 is used, the oxide film 10 can be formed for definition also in the depth direction of the etching region 14.

[ 0169 ] herefore , the air gap 9 which is between the

microstructure 7 and the silicon substrate 1 can be processed with high accuracy.

Example 2

[0170] As Example 2, an exemplary structure of a

microstructure in which cells are formed in an array is described with reference to FIGS. 8A and 8B.

[0171] Note that, like reference numerals are used to

designate members having like functions to those in Example 1 and description thereof is omitted.

[0172] The microstructure of this example is a microstructure in which cells 18 each of which is a unit indicated by a broken line in FIG. 8A are formed in an array. FIG. 8B is a sectional view of the cell 18.

[0173] Further, FIG. 8A is a top view of a section taken along the line 8A-8A of FIG. 8B. As illustrated in FIG. 8B, one cell 18 forms the microstructure 7 (membrane structure) which is. similar to that in Example 1 and which uses a part of the first layer 4.

[0174] The cell 18 of this example is different from the

microstructure 7 in Example 1 in that the cell 18 includes exhaust holes 22 which communicate with the air gap 9. Therefore, the air gap 9 is filled with the surrounding medium and the pressure therein is equal to that in the surroundings.

[0175] When displacement of the membrane structure changes the air gap 9, the medium which fills the air gap 9 can come in and go out through the exhaust holes 22.

[ 0176] herefore, ohmic attenuation which accompanies

vibrations of the membrane structure can be adjusted by the size and the number of the exhaust holes 22.

[0177] One cell 18 of this example is, similarly to the

microstructure of Example 1, in the shape of a

rectangle seen from above.

[0178] The air gap 9 is in the shape of a square of 230 μπι^χ230 μπι, and the movable membrane structure is also 230 μπ\^χ230 μπι.

[0179] In an area of 3 mm* 3 mm, 12x12 cells 18 are arranged.

All the cells arranged in the area of 3 mmx3 mm

electrically function as capacitors connected in parallel.

[0180] The total thickness of the membrane including the metal layers 5, the insulating layers 6, and the coating 8. is 1.2 μιη. Among the layers, the metal layer 5 is at a thickness of about 0.2 μπι.

[0181] Further, the thickness of the air gap 9 is 1 μπι.

Further, the diameter of the exhaust holes 22 is 30 μπι, and 4x4 exhaust holes 22 are formed in one cell 18 at a pitch of 60 μιτι.

[0182] By arranging the cells 18 in an array with one cell being the unit as described above, the characteristics of a frequency range detected by the cells 18 can be determined and the area which receives sound in the array region can be selected.

[0183] In order to use the cells 18 formed in an array in this way to form a sensor which satisfactorily functions, it is necessary that the mechanical characteristics of the respective cells 18 be the same.

[ 0184 ] Further, the efficiency of receiving sound can be improved more when the cells 18 are arranged more densely. Therefore, it is necessary to improve the positioning of the membrane structure formed in the first layer 4 and the air gap 9 and the processing accuracy of the air gap 9 to reduce the pitches of the cells 18.

[0185] According to the manufacturing method of the present invention, variations in size of the region of the movable membrane and variations in size of the air gap 9 can be reduced to reduce variations in mechanical characteristics of the cells 18 formed in an array.

[ 0186] Further, the accuracy of the positional relationship between the first layer 4 and the air gap 9 and the accuracy of the air gap 9 are high, and thus, the cells 18 can be densely arranged.

[0187] Next, a method of manufacturing the microstructure of this example is described with reference to FIGS. 9A to 9E and FIGS. 10A to IOC. The figures particularly illustrate sections of one cell 18.

[0188]As illustrated in FIG. 9A, the SOI substrate, which includes the first silicon layer 19 including the first surface 2, the second silicon layer 20 including the second surface 3, and the embedded oxide film layer 21 sandwiched therebetween, is prepared.

[0189] Then, as illustrated in FIG. 9B, the pad layer 12 and the protective film 13 are formed on the first surface, and after that, the holes 11 are formed so as to pierce the first silicon layer 19.

[0190] hen, as illustrated in FIG. 9C, the oxide film 10 is formed in the holes 11.

[0191] At this time, portions of the oxide film 10 other than those formed in the holes 11 are removed using chemical mechanical polishing to carry out planarization . The pad layer 12 and the protective film 13 are removed to form the etching region 14 having the side portions surrounded by the oxide film 10 and the bottom portion covered with the embedded oxide film layer is formed as illustrated in FIG. 9C.

[0192] Then, as illustrated in FIG. 9D, the first layer 4 in which the patterned metal layers 5 and insulating layers 6 are stacked is formed.

[0193] In the formation, the position of the pattern of the metal layers 5 and the insulating layers 6 and the position of the etching region are adjusted. Then, with reference to FIG. 9E, a resist film is formed as the etching mask 16 by photolithography and second openings 23 are formed.

[0194] The second openings 23 are to be the exhaust holes 22 later. In this step, the second openings 23 pierce the second silicon layer 20 by deep dry etching of silicon, and then reach the etching region 14 by etching of the embedded oxide film layer 21.

[0195] Between the step illustrated in FIG. 9D and the

formation of the second openings 23, the second silicon layer 20 can be ground from the second surface 3 side to be thinned. For example, the thickness of the second silicon layer 20 can be reduced to be 100 μιτι or less in this step. By thinning the second silicon layer 20 in this way, the etching time of the second openings 23 can be reduced.

[0196] After that, as illustrated in FIG. 10A, a support layer 24 is formed so as to fill the second openings 23.

[0197] In this case, a resist film can be used. Then, using the pattern of the metal layers 5, the insulating layers 6 are etched out to form the first opening 17. Then, as illustrated in FIG. 10B, an etchant is

introduced through the first opening 17 to remove the etching region 14 and to form the air gap 9.

[0198] In this case, dry etching can be carried out using XeF₂ as the etchant. Then, as illustrated in FIG. IOC, the support layer 24 is removed. In this case, the removal can be carried out by oxygen plasma ashing. [0199] Finally, a silicon nitride film is formed as the coating 8 by plasma CVD. In this way, the

microstructure illustrated in FIG. 8B can be

manufactured .

[0200] he method of manufacturing the microstructure of this example has the following effect. By defining the bottom portion of the etching region using the embedded oxide film layer 21 of the SOI substrate, the

uniformity in depth of the air gaps 9 in the cells 18 formed in an array can be enhanced.

[0201] In the step of forming the holes 11, the influence of variations in etching rate and in etching start point can be lowered, and variations in thickness of the first silicon layer 19 are satisfactorily controlled over the entire substrate, and thus, even when a large- scale array is formed, the uniformity in depth of the air gaps 9 is enhanced.

[ 0202 ] Further, error factors can be separated among the

respective steps, and thus, development of production control and the manufacturing method can be

parallelized or simplified.

[0203] Further, the cells 18 are densely arranged, and thus, the air gap 9 can be in a shape other than a circle such as a rectangle or a polygon. In that case, the ratio occupied by the air gap 9 increases, but, in the step of forming the holes 11, etching is carried out only along the contour. Therefore, increase in the etching rate distribution and insufficient etching due to the increased area to be removed in the step of forming the holes 11 can be reduced.

Example 3

[0204] As Example 3, an exemplary structure of a charged

particle optical system is described with reference to FIGS. 11A and 11B and FIGS. 12A and 12B. Note that, like reference numerals are used to designate members having like functions to those in Example 1 and description thereof is omitted.

[0205] he charged particle optical system of this example

includes a light source for generating multiple charged particle beams and a counter electrode array.

[0206] The counter electrode array includes an aperture

portion having multiple openings formed therein for shaping charged particle beams which pass therethrough by blocking at least a part of multiple charged

particle beams.

[0207] The counter electrode array also includes an electrode portion having multiple sets of counter electrodes formed therein for forming an electric field which acts on multiple charged particle beams in terms of charged particle optics.

[ 0208 ] Specifically, the counter electrode array is an

electrostatic deflector in which the shape of charged particle beams is determined by apertures 27 surrounded by broken lines and in which charged particle beams passing through the apertures 27 are deflected by counter electrodes 26A and 26B.

[0209] Top views of sections taken along the lines 12A-12A_^ 12B-12B of FIG . 11A correspond to FIGS. 12A and 12B, respectively. Further, a section taken along the line C-C of FIG. 12B corresponds to FIGS. 11A and 11B. In particular, FIGS. 11A and 11B are enlarged sectional views of a region surrounded by a broken line D in FIG. 12B.

[0210] FIG. 11B is a sectional view when the size of the

apertures 27 is particularly small. When an

electrostatic field is formed between the counter electrodes 26A and 26B, charged particle beams can be deflected in accordance with the magnitude of the electric field. The light source (not shown) for generating charged particle beams is located on the K side, and charged particle beams are caused to enter from the light source. [0211]As illustrated in FIG. 11A and FIGS. 12A and 12B, by blocking charged particle beams by the circular

apertures 27, charged particle beams which pass

therethrough are shaped.

[0212] After that, when the counter electrodes 26A and 26B are held at the same potential, charged particle beams travel in straight lines as indicated by an arrow L, and, when a potential difference is defined, deflection can be carried out as indicated by an arrow M. "Held at the same potential" as used herein means, for example, that both the counter electrodes 26A and 26B are set to the ground potential.

[0213] hen a potential difference is defined, the counter electrode 26A can be set to the ground potential and the counter electrode 26B can be set to a positive potential.

[0214]As illustrated in FIGS. 11A and 11B and FIGS. 12A and 12B, the apertures 27 are formed of through holes formed in the first silicon layer 19. By reducing the size of the apertures 27 as illustrated in FIG. 11B, the diameter of charged particle beams which pass therethrough can be reduced.

[0215] Similarly, by forming the apertures 27 into a shape other than a circle, or by forming multiple apertures 27, charged particle beams can be arbitrarily shaped accordingly.

[0216] On the other hand, the counter electrodes 26A and 26B are formed by patterning a part of the metal layers 5 included in the first layer 4 which is formed on the first surface. Therefore, the apertures 27 and the counter electrodes 26A and 26B are formed integrally in/on the same substrate.

[0217] As illustrated in FIGS. 12A and 12B, the counter

electrodes 26A and 26B and the apertures 27 are

arranged in an array. The counter electrode 26B is connected to a CMOS circuit portion 25 as a control circuit, which is formed on the same substrate.

[ 0218 ] Further , as illustrated in FIG. 12A, in the section

taken along the line 12A-12A of FIG. 11A, the metal layers 5 have slit-like openings corresponding to the lines of the apertures 27. Portions other than the slit-like openings are formed so as to cover the counter electrodes 26A and 26B from above.

[0219] The metal layers 5 function as a shield structure for preventing crosstalk between electrostatic fields formed by the counter electrodes 26A and 26B.

[0220] s described above, in the charged particle optical system of this example, the shield structure and the CMOS circuit portion 25 are also formed integrally on the same substrate.

[0221] The apertures 27 of this example have a diameter of 1 μηα and a thickness of 1.5 μιη. When regarding a shorter side as the width and a longer side as the length of the counter electrodes 26A and 26B in the top view of FIG. 12B, the counter electrodes 26A and 26B have a width of 1 μηα and a length of 2 μπι.

[0222] Further, when regarding the dimension in the direction of the normal to the first surface 2 in FIG. 11B as the height, the counter electrodes 26A and 26B have a height of 5 μπι, and the distance between the counter electrodes 26A and 26B is 1.5 μπι. Further, the pairs of the counter electrodes 26A and 26B are arranged at pitches of 4 μπι.

[0223] The charged particle optical system of this example has the following effects.

[0224] First, by integrally forming the apertures 27 and the counter electrodes 26A and 26B, compared with a case where the aperture portion and the counter electrode portion (that is, the deflector portion) are formed on separate substrates, fabrication can be eliminated to improve the alignment accuracy with each other.

[0225] In particular, by forming the through holes in the silicon substrate to form the apertures 27 and by using a part of the first layer 4 formed on the silicon substrate as the counter electrodes, the respective patterns can be aligned with each other with high accuracy using a semiconductor manufacturing technology in the manufacture.

[0226] This is particularly effective when, as in this example, the difference in size between the apertures 27 and the counter electrodes 26A and 26B is on the order of submicrometers , for example, when the difference

between the diameter of the apertures 27 and the

distance between the counter electrodes 26A and 26B is 0.5 μιη.

[0227] In particular, by using a multilayer wiring layer used in a CMOS manufacturing technology as the first layer 4, a fine structure can be manufactured in ordinary

process steps to improve the yield and to reduce the cost. Further, the CMOS circuit portion 25 can also be integrated on the same substrate.

[ 0228 ] Further , the apertures 27 and the counter electrodes

26A and 26B are formed in/on the same substrate, and thus, even if deformation occurs by heat generation caused by driving of the CMOS circuit portion 25 or entrance of charged particle beams through the

apertures 27, the apertures 27 and the counter

electrodes 26A and 26B integrally expand and contract. Therefore, relative positional misalignment

therebetween can be reduced.

[0229] When the apertures 27 and the counter electrodes 26A

and 26B are formed on separate substrates, if the temperatures of the respective substrates differ, difference is caused in expansion and constraction .

Therefore, the relative positions of the openings and the counter electrodes may be misaligned to cause charged particle beams which pass through the openings to be blocked by the counter electrodes. [0230] Further, when a large-scale array is formed and the footprint of an entire element becomes larger, the influence of the difference in expansion and

constraction becomes greater. However, by reducing the difference in expansion and constraction by formation of the apertures 27 and the counter electrodes 26A and 26B on the same substrate as in the present invention, a charged particle optical system without relative positional misalignment between the openings and the counter electrodes over the entire array can be

realized. Similarly, in order to reduce electric field leakage, it is desired that the size of the openings of the shield portion be as close to the diameter of the apertures 27 as possible.

[0231] However, when the difference in size between the shield portion and the apertures 27 becomes smaller, the influence of the relative positional misalignment due to alignment accuracy in a fabrication step and

difference in thermal expansion described above becomes greater .

[0232] In the charged particle optical system of this example, by integrally forming the shield portion on the same substrate, the alignment accuracy can be enhanced to reduce the relative positional misalignment due to thermal deformation.

[0233] Next, a method of manufacturing the microstructure of this example is described with reference to FIGS. 13A to 13E and FIGS. 14A to 14C.

[0234] First, as illustrated in FIG. 13A, the SOI substrate which includes the first silicon layer 19 including the first surface 2, the second silicon layer 20 including the second surface 3, and the embedded oxide film layer 21 therebetween is prepared.

[0235] Then, as illustrated in FIG. 13B, the pad layer 12 and the protective film 13 are formed, and after that, the holes 11 are formed so as to pierce the first silicon layer 19. In this case, the bottom portions of the holes 11 are the embedded oxide film layer 21.

[0236] Then, as illustrated in FIG. 13C, the oxide film 10 is formed on the side portions of the holes 11. Therefore, the side portions and the bottom portions of the holes 11 are surrounded by silicon oxide of the oxide film 10 and the embedded oxide film layer 21, respectively.

[0237] Then, as illustrated in FIG. 13D, polysilicon is formed in the holes 11 as the filling material 15. Portions of polysilicon other than those formed in the holes 11 undergo chemical mechanical polishing, and the pad layer 12 and the protective film 13 are removed.

[0238] Then, as illustrated in FIG. 13E, the first layer 4 is formed. The etching regions 14 are formed, whose bottom portions and side portions are surrounded by silicon oxide and which are formed of the filling material 15. In this case, as illustrated in FIG. 13E, the metal layers 5 and the insulating layers 6 in the first layer 4 are patterned in accordance with the microstructure . When these patterns and the etching regions 14 are formed, these patterns and the etching regions 14 are aligned with reference to alignment marks (not shown) on the first^' surface side in

lithography. Further, the metal layers 5 in regions indicated by broken lines are, in particular,

sacrificial structures 28. By removing the sacrificial structures 28 later, the first openings 17 in the shape of the sacrificial structures 28 can be formed in the insulating layers 6.

[0239] Further, as illustrated in FIG. 14A, the second opening 23 is formed in the second silicon layer 20 from the second surface 3. The second opening 23 in section is in the shape of a circle having a diameter of 100 pm. The second opening 23 pierces the second silicon layer 20 and stops at the embedded oxide film layer 21.

[0240] After that, as illustrated in FIG. 14A, the support layer 24 is formed in the second opening 23. In particular, the support layer 24 is required to cover . ... the bottom portion of the second opening 23 (that is, a surface of the embedded oxide film layer 21).

[0241] It is preferred that the material of the support layer be a material which has selectivity with respect to silicon oxide, and it is more preferred that the

material of the support layer be a material which has selectivity further with respect to the metal layers 5. In this case, the material is molybdenum which is formed by sputtering.

[0242] Further, between the step illustrated in FIG. 13E and the step of forming the second opening 23, the second silicon layer 20 can be thinned from the second surface 3 side.

[0243] For example, in the thinning step, the thickness of the second silicon layer 20 can be set to be about 100 μτ . In this case, the etching time of the second opening 23 can be reduced. Further, the aspect ratio of the second opening 23 can be lowered.

[0244] Further, by carrying out the thinning between the step illustrated in FIG. 13E and the step of forming the second opening 23, an SOI substrate having an ordinary thickness (about 500 to 700 μιη) can be used when the holes 11 and the first layer 4 are formed, which

require high processing accuracy and alignment accuracy.

[0245] hen, as illustrated in FIG. 14B, a resist film is

formed as the etching mask 16 on the uppermost surface of the first layer 4, and the sacrificial structures 28 are etched out.

[0246] Then, the first openings 17 are formed. The metal

layers are copper, and can be removed using an ordinary wet etchant for copper.

[0247] After that, XeF₂ gas is introduced through the first

openings 17 to remove the filling material 15 and to form the air gaps 9. In this case, the side portions are surrounded by the oxide film 10 and the bottom portions are covered with the embedded oxide film layer 21, and thus, the etching stops at these films.

[0248]After that, as illustrated in FIG. 14C, the pattern of the metal layers 5 which is exposed on the uppermost surface of the first layer 4 is used as the etching mask, and the first openings 17 are widened. At this time, as illustrated in FIGS. 12A and 12B, the first openings 17 become slit-like openings.

[0249] Finally, by using buffered hydrofluoric acid, the oxide film 10 and a part of the embedded oxide film layer 21 are removed. After that, molybdenum as the support layer 24 is removed using an aqueous solution of phosphorous acid, nitric acid, and acetic acid.

[0250] In that way, the charged particle optical system

including the apertures 27 and the counter electrodes 26A and 26B as illustrated in FIG. 11A can be

manufactured .

[0251] he method of manufacturing the charged particle

optical system of this example has the following effects .

[0252] First, by using the embedded oxide film layer 21 of the SOI substrate as the etching stop layer of the bottom portion and forming the filling material 15 in the holes 11, even a small region of the air gap 9 having a dimension of a section of several micrometers or less can be processed with high accuracy.

[0253] Further, even when the depth is large with respect to the cross-sectional area of the region to be removed, processing can be carried out with high accuracy. This is because the cross-sectional area of the hole 11 is substantially the same as that of the air gap 9, and thus, compared with a case where the hole 11 is formed in a region along the contour of the air gap 9, the aspect ratio of the holes 11 is low and the difficulty in processing can be reduced. [0254 ] Further, the thickness accuracy of the air gap 9 can be determined by the thickness accuracy of the first silicon layer 19. Therefore, in the step of forming the holes 11, the influence of variations in etching rate and etching start point can be lowered.

[0255] Further, error, factors can be separated among the

respective steps, and thus, development of production control and of the manufacturing method can be

parallelized or simplified.

[0256] ext, by forming the first openings 17 using the

sacrificial structures 28, the first openings 17 can be easily formed in the insulating layers 6 which has difficulty in high aspect ratio processing.

[0257] When the thickness of the first layer 4 becomes large or when the etching region is minute, it is necessary to form openings having a large depth with respect to the cross-sectional area of the openings (that is, the aspect ratio of the openings is high) as the first openings. In this case, the insulating layers 6 are mainly formed of silicon oxide, and it is more

difficult to form therein high aspect ratio openings compared with a case where high aspect ratio openings are formed in silicon.

[0258 ] Therefore, by designing so that, as in this example, the metal layers 5 are to be the sacrificial structures 28, the first openings 17 having a high aspect ratio can be formed in satisfactory alignment with the etching regions (filling material 15).

[ 0259] Further, even if the size and the formation density of the first openings 17 change, the etching conditions for forming the first openings 17 almost do not change. Therefore, the manufacturing steps are adaptable to various layouts.

[0260] Next, by forming the second opening 23 before the first openings 17 are formed, the microstructure and the CMOS circuit portion 25 formed in the first layer 4 can be _Λ„

prevented from being broken and from being deteriorated in the step _. of forming the second opening 23.

[0261] In the step of forming the second opening 23, the first layer 4 is sometimes immersed in a chemical solution or water during lithography or during dry etching, or, in the step, mechanical stress is applied to the first layer during handling.

[0262] In this case, if the first openings 17 are already

formed, the first openings 17 may be broken, or, dust may adhere to and block the openings .

[0263] Further, moisture may enter from portions between the metal layers 5 and the insulating layers 6 of the first layer 4 to corrode the metal layers 5 or to deteriorate the circuit characteristics of the CMOS circuit

portions 25.

[0264] Therefore, by forming the second opening 23 before the first openings 17 are formed as in this example, the risk of such breakage and deterioration can be reduced to improve the yield. Further, by forming the support layer 24 after the second opening 23 is formed, the mechanical strength of the thinned portion which includes only the first silicon layer 19 and the embedded oxide film layer 21 can be enhanced to prevent breakage in the manufacturing steps.

[ 0265 ] Further, in the step of etching out the filling

material 15, the second openings 23 can be prevented from being widened.

[0266] Further, by the step of, after removing the filling

material 15, removing the insulating layers 6 and widening the first openings 17, a microstructure in an arbitrary shape other than the shape of the first openings 17 can be formed in the first layer 4.

[0267] In this case, by the existence of the support layer 24, the dry etching in the removing step can be prevented from piercing the SOI substrate without bonding thereto a particular rear surface. [0268] If a through hole is formed in the dry etching, an etching gas goes around to the rear surface and a cooling gas goes around to the front surface side to cause breakage or abnormal etching.

[0269] herefore, by forming the support layer 24, the yield can be improved. Further, by using a metal as the support layer 24, a phenomenon in which a bottom portion is widened in dry etching (so-called notching) can be reduced to prevent malformation of the air gap 9 in the removing step, and thus, the air gap 9 can be formed with high accuracy. Further, in particular, by removing the insulating layers 6 with the metal layer 5 on the uppermost surface of the first layer 4 being used as the etching mask, the size of the first

openings 17 can be increased without lithography after the filling material 15 is etched out.

[0270] Unevenness is caused by the first openings 17, which makes it difficult to carry out lithography with regard to such a surface with high accuracy. By using a pattern of the metal layer 5 as in this example, the size of the first openings 17 can be increased with a satisfactory yield.

[0271] While the present invention has been described with reference to exemplary embodiments, it is to be

understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest

interpretation so as to encompass all such

modifications and equivalent structures and functions.

[0272] This application claims the benefit of Japanese Patent Application No. 2012-134484, filed June 14, 2012, which is hereby incorporated by reference herein in its entirety .

Reference Signs List

[0273] 1: silicon substrate

2: first surface : second surface

: first layer

: metal layer

: insulating layer

: microstructure

: coating

: air gap

0: oxide film

9: first silicon layer

0: second silicon layer1: embedded oxide film layer

Claims

[Claim 1] A method of manufacturing a microstructure, comprising:

a first step of forming a hole in the first surface of the silicon substrate;

a second step of forming, in the hole, a film comprising a material which has selectivity for an etchant, at which an etching region with side portions and a bottom portion surrounded by the film is to be formed;

a third step of forming, on the first surface of the silicon substrate, a first layer which comprises a multilayer film comprising an insulating layer and a metal layer stacked therein, at least one of the insulating layer and the metal layer being patterned, in a state where a position of the pattern and a position of the etching region are adjusted; a fourth step of forming a first opening which pierces the first layer; and

[Claim 2] The method of manufacturing a microstructure according to claim 1, wherein:

the third step comprises forming the metal layer and the insulating layer at a portion at which the first opening is to be formed; and

the fourth step comprises forming the first opening by removing a portion of the insulating layer at which the first opening is to be formed.

[Claim 3] The method of manufacturing a microstructure according to claim 1, wherein:

the third step comprises forming the metal layer at a portion at which the first opening is to be formed; and the fourth step comprises forming the first opening by removing a portion of the metal layer at which the

first opening is to be formed.

[Claim 4] The method of manufacturing a microstructure according to any one of claims 1 to 3, wherein:

the silicon substrate prepared in the preparing step comprises an SOI substrate comprising a first silicon layer including the first surface, a second silicon layer including the second surface, and an embedded oxide film layer sandwiched therebetween;

the hole formed in the first surface in the first step is formed in the first surface so as to pierce the first silicon layer but so as not to pierce the

embedded oxide film layer; and

the film which covers the bottom portion of the etching region in the second step comprises the embedded oxide film layer.

[Claim 5] The method of manufacturing a microstructure according to claim 4, further comprising a seventh step of forming a second opening which pierces the second silicon layer from the second surface side, the seventh step being performed between the third step and the fourth step.

[Claim 6] The method of manufacturing a microstructure according to any one of claims 1 to 5, wherein, in the second step, after the film is formed on wall surfaces of the hole, a filling material which is etchable by the etchant is filled into the hole, and the etching region is formed by the filled filling material.

[Claim 7] The method of manufacturing a microstructure according to claim 6, wherein the filling material comprises silicon .

[Claim 8] The method of manufacturing a microstructure according to claim 6, wherein the fifth step comprises widening the first opening by removing the filling material.

[Claim 9] The method of manufacturing a microstructure according to any one of claims 1 to 8, further comprising using the first layer formed on the first surface of the

silicon substrate in the third step to form a CMOS circuit portion which functions as a circuit.

[Claim 10]A charged particle optical system, comprising:

a light source for generating multiple charged particle beams; and

a counter electrode array, wherein:

the counter electrode array comprises:

an aperture portion including through holes which are multiple openings formed in a silicon substrate for shaping charged particle beams that pass therethrough by blocking at least a part of the multiple charged particle beams; and

an electrode portion having multiple sets of counter electrodes formed on the silicon substrate for forming an electric field which acts on the multiple charged particle beams in terms of charged particle optics, the electrode portion comprising a multilayer film of a metal and a dielectric; and

the aperture portion and the electrode portion are integrally formed.