WO2014028008A1 - Commande de pics de tension pour convertisseurs de puissance - Google Patents

Commande de pics de tension pour convertisseurs de puissance Download PDF

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Publication number
WO2014028008A1
WO2014028008A1 PCT/US2012/050867 US2012050867W WO2014028008A1 WO 2014028008 A1 WO2014028008 A1 WO 2014028008A1 US 2012050867 W US2012050867 W US 2012050867W WO 2014028008 A1 WO2014028008 A1 WO 2014028008A1
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WO
WIPO (PCT)
Prior art keywords
power
switching
power device
switching apparatus
transistors
Prior art date
Application number
PCT/US2012/050867
Other languages
English (en)
Inventor
Paolo Menegoli
Fabio Alessio Marino
Original Assignee
Paolo Menegoli
Fabio Alessio Marino
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Paolo Menegoli, Fabio Alessio Marino filed Critical Paolo Menegoli
Priority to PCT/US2012/050867 priority Critical patent/WO2014028008A1/fr
Publication of WO2014028008A1 publication Critical patent/WO2014028008A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention is in the field of integrated switching power circuits.
  • the present invention is further in the field of switching power converters.
  • the present invention further relates to the field of high frequency drivers of inductive loads.
  • the implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
  • the high frequency switching of the power converters is meant to reduce the size of the main output inductor and filter capacitors.
  • the transfer of energy that occurs at every transition becomes very critical affecting negatively the efficiency and reliability of the circuit.
  • the load current establishes the energy stored in the inductor before the turn off of the power device according to the equation:
  • the most common solution is to use a capacitor as shown in FIG.1.
  • the capacitor C2 is placed between the nodes 1 and 2.
  • the lumped parasitic inductors L2 and L3 include the inductance of the metal interconnections in the integrated circuit, of the connections of the integrated circuit to the external world (bonding wire, bumps or metallic pillars), and of the circuit board traces.
  • the combined inductances can typically be in the order of a few nH.
  • the nodes 1 and 2 characterize for simplicity the nodes of the integrated circuit power pads therefore C2 is placed between the positive and the negative integrated circuit power terminals when integrated.
  • the capacitor C2 is charged when the transistor Ml is turned off and provides current to the load and to the reverse recovery charge of the low side transistor M2 intrinsic body diode when Ml is turned back on. Therefore the capacitor C2 is charged with the excess energy present in L2 in one switching phase and is discharged in the opposite switching phase.
  • the value of the capacitor C2 is dependent on the power converter load current and it should be sized for the maximum load current and the maximum overvoltage that the transistor Ml can withstand without any failure.
  • the shoot-through current is also called cross-conduction current and it refers to the phenomenon that occurs when both power devices are conducting simultaneously for a very short time of the period. In such event the possible current in the power transistors is not controlled, it can be very high, it can damage or degrade the power devices and it represents extra power dissipated in the chip, adversely affecting the overall efficiency of the power converter.
  • the most common solution to prevent cross-conduction current is to utilize anti cross- conduction circuits in the driver circuit as shown in FIG.2.
  • the depicted circuit guarantees that, when a switching transition is requested, the first occurrence is the turning off of the transistor that was on. Only after the voltage change of the gate of the device turning off is sensed, the turning on of the other power device is allowed and commanded.
  • This circuit is very effective in assuring that the Vgs of the power devices are not above threshold simultaneously, but it introduces a propagation delay in the driver due to the number of logic gates that the driving signal has to travel through.
  • This driver propagation delay may not be acceptable in very high frequency power converters because the duty cycle in extreme conditions of Vout and Vin may impose to the control loop to react within very few ns.
  • Many other schemes are used in the industry, like the one described in Audi (US 7, 187,226). One of the most common means is the optimization of break before make timing. But all these schemes are either not safe enough to preventing cross-conduction current in the power devices or they introduce transition losses that affect the overall power converter efficiency.
  • the present invention describes an active clamp of the overvoltage spikes caused by the turning off of a power devices when parasitic interconnection inductances are present, while making use of the excess energy stored in the parasitic inductance, or a portion of it, to drive the gate of the transistor that is expected to turn on in the successive phase or while making use of the signal generated by the inductive "kick" to determine that the power device is in fact turning off.
  • circuit described in the present invention can be used in conjunction with the conventional methods described above, like the addition of a filter capacitor, being perfectly compatible and not necessarily in alternative to them.
  • the size of the filter capacitor can be substantially reduced.
  • the present invention in its preferred embodiment, shown in FIG.3, describes a transistor M3 with its source connected to the node 1, where the overvoltage spike generally occurs, its gate tied to the "low current” version of the input power source terminal through a parasitic inductor L4 and its drain connected to the gate of the low side drive M2.
  • the "low current” version of the input power source terminal is purposely distinct from its "high current” or “power” version, where the load current is flowing.
  • the present invention assumes the separation of the power path from the lower current path in the power distribution rails for the input power source. It is evident to anyone skilled in the art that many portions of the circuit may be connected to the lower current input power pad, even though they have not been represented in FIG.3 for clarity.
  • the parasitic inductance L4 is most likely of the same order of magnitude of the inductor L2 (maybe a bit larger), but the lack of large current flowing in it makes the voltage at the node 5 much more stable that the voltage at the node 1.
  • the drive signal coming from the pre-driver circuit 4 is purposely slower because when the load current is small a tiny propagation delay in the switching transitions is more acceptable, in fact, typically, the DCM occurs at lower switching frequencies (Pulse Frequency Modulation). In practical terms the signal coming from the circuit 4 provides a back up for fully turning on the power devices and for keeping them off when needed.
  • the transistor M4 similarly turns on when the device M2 is getting turned off.
  • continuous current mode high load current
  • the current in the main inductor LI is always positive and the node 2 experiences an overvoltage.
  • This overvoltage spike drives the gate voltage of the transistor M4 above its threshold voltage thus causing current to be drawn from the gate of the power transistor Ml, effectively charging its gate voltage to turn Ml on.
  • the overvoltage at the node 2 provides a signal indicating that the power device M2 is turning off and it is therefore safe to turn Ml on.
  • the energy stored in L3 is not utilized to charge the gate of Ml, but similarly it could be utilized by using a PMOS transistor to drive a signal internal to the driver circuit and not shown in FIG.3, as is clear to anyone skilled in the art. It should be noted that the transistors M3 and M4 should have an adequate size to reach high transconductance and allow large spikes of current to flow with minimum dissipation.
  • FIG.4 shows an example of an embodiment in which an extra transistor M5 is added to divert some of the energy present in L2 directly to the load when the power device Ml is turning off.
  • the thresholds and relative sizes of the transistor M3 and M4 may be different in order to give priority to one path or the other, dependent on the circumstances. For instance the body connections of the transistors M3 and M5 could be connected to different nodes to allow M5 to turn on at higher voltage than M3.
  • a capacitor in parallel to L7 can reduce this negative voltage spike but it is costly and it introduces a resonant circuit.
  • the present invention proposes the addition of the transistor M8 of FIG.5.
  • the transistor M8 turns on when the voltage at node 1 1 is negative enough to cause the VGS of M8 to be higher than its threshold.
  • the excess energy in L7 causes current to flow in M8 and, in its turn, it charges the gate of the transistor M7. Therefore, in analogous way to the case of the buck converter described above, the energy in the parasitic inductor L7 is utilized to obtain a very fast transition guaranteeing that M6 and M7 are not in on condition simultaneously even for a very short time.
  • FIG. l shows a general inductive buck switching power converter output stage topology with filter capacitor (prior art).
  • FIG.2 shows a schematic of the pre-driver circuit topology of a buck switching power converter with cross-conduction protection feature (prior art).
  • FIG.3 shows a schematic of the output stage of a buck power converter with voltage spike reduction and cross-conduction protection circuit according to the preferred embodiment of the present invention.
  • FIG.4 shows a schematic of the output stage of a buck power converter with voltage spike reduction and cross-conduction protection circuit according to another embodiment of the present invention.
  • FIG.5 shows a schematic of the output stage of a boost power converter with voltage glitch reduction and cross-conduction protection circuit according to a further embodiment of the present invention.
  • FIG.6 shows the simulated result of a transient, occurring at the high side power device turn off transition, for the circuit described in FIG.4 in various conditions.
  • FIG.7 shows the simulated result of a transient occurring at a switching transition of the power devices of a buck power converter whose output stage is shown in FIG.3.
  • FIG.3 is showing a schematic of the output stage of a buck power converter with voltage spike reduction and cross conduction protection circuit according to the preferred embodiment of the present invention.
  • FIG.3 describes a transistor M3 with its source connected to the node 1, where the overvoltage spike generally occurs, its gate tied to the "low current” version of the input power source terminal through a parasitic inductor L4 and its drain connected to the gate of the low side drive M2.
  • the "low current” version of the input power source terminal is purposely distinct from its "high current” or “power” version, where the load current is flowing.
  • the present invention assumes the separation of the power path from the lower current path in the power distribution rails for the input power source. It is evident to anyone skilled in the art that many portions of the circuit may be connected to the lower current input power pad, even though they have not been represented in FIG.3 for clarity.
  • the parasitic inductance L4 is most likely of the same order of magnitude of the inductor L2 (maybe a bit larger), but the lack of large current flowing in it makes the voltage at the node 5 much more stable that the voltage at the node 1.
  • the drive signal coming from the pre-driver circuit 4 is purposely slower because, when the load current is small, a tiny propagation delay in the switching transitions is more acceptable, in fact typically the DCM occurs at lower switching frequencies (Pulse Frequency Modulation). In practical terms the signal coming from the circuit 4 provides a back up for fully turning on the power devices and for keeping them off when needed.
  • the transistor M4 similarly turns on when the device M2 is being turned off.
  • continuous current mode high load current
  • the current in the main inductor LI is always positive and the node 2 experiences an overvoltage.
  • This overvoltage spike drives the gate voltage of the transistor M4 above its threshold voltage thus causing current to be drawn from the gate of the power transistor Ml, effectively charging its gate voltage to turn Ml on.
  • the overvoltage at the node 2 provides a signal indicating that the power device M2 is turning off and it is therefore safe to turn Ml on.
  • the energy stored in L3 is not utilized to charge the gate of Ml, but similarly it could be utilized by using a PMOS transistor to drive a signal internal to the driver circuit and not shown in FIG.3, as is clear to anyone skilled in the art. It should be noted that the transistors M3 and M4 should have an adequate size to reach high transconductance and allow large spikes of current to flow with minimum dissipation. B FIG.4
  • FIG.4 shows an example of an embodiment in which an extra transistor M5 is added to divert some of the energy present in L2 directly to the load when the power device Ml is turning off.
  • the thresholds and relative sizes of the transistor M3 and M4 may be different in order to give priority to one path or the other, dependent on the circumstances. For instance the body connections of the transistors M3 and M5 could be connected to different nodes to allow M5 to turn on at higher voltage than M3.
  • a capacitor in parallel to L7 can reduce this negative voltage spike but it is costly and it introduces a resonant circuit.
  • the present invention proposes the addition of the transistor M8 of FIG.5.
  • the transistor M8 turns on when the voltage at node 1 1 is negative enough to cause the VGS of M8 to be higher than its threshold.
  • the excess energy in L7 causes current to flow in M8 and, in its turn, it charges the gate of the transistor M7. Therefore, in analogous way to the case of the buck converter described above, the energy in the parasitic inductor L7 is utilized to obtain a very fast transition guaranteeing that M6 and M7 are not in on condition simultaneously even for a very short time.
  • FIG.6 shows the simulated result of a transient occurring at the high side power device turn off transition, for the circuit described in FIG.4, in various conditions.
  • the overvoltage occurring at the node 1 of FIG.1 is reported in four different cases.
  • the case of waveform 14 refers to the case when no clamp is present. It can be seen that the overvoltage can be very pronounced, reaching a voltage in excess of 1 IV. It should be mentioned that in all the shown cases the load was 1A, the switching frequency 20MHz, the parasitic inductance L2 at the node 1 of FIG.4 was 3nH.
  • the waveform 15 refers to the case where only the clamp M3 of FIG.4 is present. It can be noticed that in this case the overvoltage peak is reduced to about 8V.
  • the waveform 16 refers to the case where both clamps effects given by the transistors M3 and M5 of FIG.4 are present. In this case it can be seen that the overvoltage glitch amplitude is reduced further to about 6V. Furthermore also the successive ringing of the voltage is very much damped with respect to all the other cases.
  • waveform 17 refers to the case where no active clamp is added but only a
  • InF filter capacitor is introduced, as shown in the prior art of FIG.1. It can be highlighted that in this case the overvoltage spike amplitude is reduced approximately to the same value of the case of waveform 16, but the ringing is much more persistent. This graph demonstrates that adding active clamps can significantly attenuate the overvoltage and the successive voltage ringing of the node without using high value capacitors that occupy large silicon areas.
  • FIG.6 should be intended as qualitative to demonstrate the significant improvement offered by the proposed invention.
  • FIG.7 shows the simulated result of a transient occurring at switching transition of the power devices of a buck power converter whose output stage is shown in FIG.3.
  • the power converter output load is 1A
  • the parasitic inductances L2, L3, L4 and L5 with reference to FIG.3 are all 3nH.
  • the switching frequency is 20MHz.
  • the shown waveforms are focused on the turning off of the high side power device Ml and the successive turning on of the power device M2.
  • the waveform 18 represents the current flowing in the clamp transistor M3 when the transistor Ml is turned off. It can be noted that the current spike in correspondence of the overvoltage spike at node 1, can be quite high (in the shown simulation waveform about 900mA). That explains why the clamp transistors must have adequate size.
  • the waveform 19 reports the gate of the high side power transistor Ml which is brought high to turn the device off.
  • the waveforms 20 and 21 represent the current flowing in the two power devices at the transition point. The shown currents are respectively the source current of Ml and the drain current of M2. These two currents are shown together to verify that no cross-conduction current is present at the switching transition, in fact no high simultaneous and positive current is showing in the power devices.
  • the waveform 22 is the gate voltage of the low side power transistor M2. It can be noticed that the two gate voltages 19 and 22 are only a few hundred ps (pico-seconds) apart (more exactly 250ps), but as mentioned no shoot through current is observed.

Abstract

La présente invention porte sur un nouveau circuit de suppression de surtension inductif pour des convertisseurs de puissance. Des pics de tension de forte amplitude se produisent généralement dans des convertisseurs de puissance haute fréquence en présence de petites inductances parasites couplées aux rails de distribution de puissance, en correspondance aux transitions de commutation, particulièrement lorsque de forts courants de charge sont requis. La présente invention propose des circuits de calage actifs pour limiter l'amplitude de la surtension. De plus, l'énergie excédentaire dans les inductances parasites est utilisée pour fournir une énergie et/ou un signal pour déterminer quand activer le dispositif de puissance de phase ultérieure avec la transition la plus rapide possible sans s'exposer à des courants de conduction transversale dans l'étage de puissance du convertisseur, améliorant ainsi ses performances globales, et sa fiabilité de circuit en plus d'atteindre un rendement de conversion élevé.
PCT/US2012/050867 2012-08-15 2012-08-15 Commande de pics de tension pour convertisseurs de puissance WO2014028008A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/US2012/050867 WO2014028008A1 (fr) 2012-08-15 2012-08-15 Commande de pics de tension pour convertisseurs de puissance

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Application Number Priority Date Filing Date Title
PCT/US2012/050867 WO2014028008A1 (fr) 2012-08-15 2012-08-15 Commande de pics de tension pour convertisseurs de puissance

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11329548B2 (en) 2019-11-22 2022-05-10 Hamilton Sundstrand Corporation Voltage clamp circuit for use in power converter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958121A (en) * 1988-11-30 1990-09-18 Sgs-Thomson Microelectronics S.R.L. Protection of power converters from voltage spikes
RU2321945C2 (ru) * 2001-11-20 2008-04-10 Вюрт Электроник Айзос Гмбх Унд Ко. Кг Переключающее устройство для надежного переключения токовых цепей
US20090102541A1 (en) * 2006-05-29 2009-04-23 Koninklijke Philips Electronics N.V. Switching circuit arrangement
US8018694B1 (en) * 2007-02-16 2011-09-13 Fairchild Semiconductor Corporation Over-current protection for a power converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958121A (en) * 1988-11-30 1990-09-18 Sgs-Thomson Microelectronics S.R.L. Protection of power converters from voltage spikes
RU2321945C2 (ru) * 2001-11-20 2008-04-10 Вюрт Электроник Айзос Гмбх Унд Ко. Кг Переключающее устройство для надежного переключения токовых цепей
US20090102541A1 (en) * 2006-05-29 2009-04-23 Koninklijke Philips Electronics N.V. Switching circuit arrangement
US8018694B1 (en) * 2007-02-16 2011-09-13 Fairchild Semiconductor Corporation Over-current protection for a power converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11329548B2 (en) 2019-11-22 2022-05-10 Hamilton Sundstrand Corporation Voltage clamp circuit for use in power converter

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