WO2014138640A1 - Clock recovery circuit for multiple wire data signals - Google Patents
Clock recovery circuit for multiple wire data signals Download PDFInfo
- Publication number
- WO2014138640A1 WO2014138640A1 PCT/US2014/021958 US2014021958W WO2014138640A1 WO 2014138640 A1 WO2014138640 A1 WO 2014138640A1 US 2014021958 W US2014021958 W US 2014021958W WO 2014138640 A1 WO2014138640 A1 WO 2014138640A1
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- WO
- WIPO (PCT)
- Prior art keywords
- signal
- state transition
- instance
- comparison signal
- filtered version
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/493—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES14712537T ES2705045T3 (en) | 2013-03-07 | 2014-03-07 | Clock recovery circuit for multi-wire data signals |
EP14712537.1A EP2965459B1 (en) | 2013-03-07 | 2014-03-07 | Clock recovery circuit for multiple wire data signals |
KR1020157026568A KR102205823B1 (en) | 2013-03-07 | 2014-03-07 | Clock recovery circuit for multiple wire data signals |
JP2015561728A JP6461018B2 (en) | 2013-03-07 | 2014-03-07 | Change the state for each state period, and make data lane skew and data state transition glitches |
CN201480012389.XA CN105027490B (en) | 2013-03-07 | 2014-03-07 | Clock recovery circuitry for multiple line data-signals |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361774247P | 2013-03-07 | 2013-03-07 | |
US201361774408P | 2013-03-07 | 2013-03-07 | |
US61/774,247 | 2013-03-07 | ||
US61/774,408 | 2013-03-07 | ||
US201361778768P | 2013-03-13 | 2013-03-13 | |
US61/778,768 | 2013-03-13 | ||
US14/199,322 US9363071B2 (en) | 2013-03-07 | 2014-03-06 | Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches |
US14/199,322 | 2014-03-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014138640A1 true WO2014138640A1 (en) | 2014-09-12 |
Family
ID=51487808
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2014/021979 WO2014138644A1 (en) | 2013-03-07 | 2014-03-07 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
PCT/US2014/021958 WO2014138640A1 (en) | 2013-03-07 | 2014-03-07 | Clock recovery circuit for multiple wire data signals |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2014/021979 WO2014138644A1 (en) | 2013-03-07 | 2014-03-07 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
Country Status (8)
Country | Link |
---|---|
US (3) | US9337997B2 (en) |
EP (2) | EP2965459B1 (en) |
JP (2) | JP6461018B2 (en) |
KR (2) | KR20150121724A (en) |
CN (2) | CN105009535B (en) |
ES (1) | ES2705045T3 (en) |
HU (1) | HUE042572T2 (en) |
WO (2) | WO2014138644A1 (en) |
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US9178690B2 (en) * | 2013-10-03 | 2015-11-03 | Qualcomm Incorporated | N factorial dual data rate clock and data recovery |
US9337997B2 (en) | 2013-03-07 | 2016-05-10 | Qualcomm Incorporated | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
US9118457B2 (en) * | 2013-03-15 | 2015-08-25 | Qualcomm Incorporated | Multi-wire single-ended push-pull link with data symbol transition based clocking |
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US9735948B2 (en) | 2013-10-03 | 2017-08-15 | Qualcomm Incorporated | Multi-lane N-factorial (N!) and other multi-wire communication systems |
US9426082B2 (en) * | 2014-01-03 | 2016-08-23 | Qualcomm Incorporated | Low-voltage differential signaling or 2-wire differential link with symbol transition clocking |
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KR102223031B1 (en) * | 2019-03-20 | 2021-03-04 | 삼성전자주식회사 | Differential signal processing device using for advanced braid clock signaling |
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CN105027490B (en) | 2018-03-16 |
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EP2965482A1 (en) | 2016-01-13 |
CN105009535B (en) | 2018-05-18 |
EP2965459A1 (en) | 2016-01-13 |
US9673969B2 (en) | 2017-06-06 |
US20140254733A1 (en) | 2014-09-11 |
CN105009535A (en) | 2015-10-28 |
JP2016513920A (en) | 2016-05-16 |
CN105027490A (en) | 2015-11-04 |
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