WO2014144864A1 - Performance optimization of data transfer for soft information generation - Google Patents

Performance optimization of data transfer for soft information generation Download PDF

Info

Publication number
WO2014144864A1
WO2014144864A1 PCT/US2014/029453 US2014029453W WO2014144864A1 WO 2014144864 A1 WO2014144864 A1 WO 2014144864A1 US 2014029453 W US2014029453 W US 2014029453W WO 2014144864 A1 WO2014144864 A1 WO 2014144864A1
Authority
WO
WIPO (PCT)
Prior art keywords
data values
buffer
read operations
storage medium
read
Prior art date
Application number
PCT/US2014/029453
Other languages
French (fr)
Inventor
Jack Edward FRAYER
Aaron K. OLBRICH
Original Assignee
Sandisk Enterprise Ip Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Enterprise Ip Llc filed Critical Sandisk Enterprise Ip Llc
Priority to KR1020157024578A priority Critical patent/KR101982381B1/en
Priority to CN201480015991.9A priority patent/CN105264496B/en
Publication of WO2014144864A1 publication Critical patent/WO2014144864A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/068Hybrid storage device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3723Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using means or methods for the initialisation of the decoder
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3769Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using symbol combining, e.g. Chase combining of symbols received twice or more
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45Soft decoding, i.e. using symbol reliability information

Abstract

A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values.

Description

Performance Optimization of Data Transfer for Soft Information Generation
TECHNICAL FIELD
[0001] This disclosure relates to error control in memory systems, and in particular, to managing data that is used for soft information error control decoding.
BACKGROUND
[0002] Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell.
[0003] A drawback of increasing storage density is that the stored data is increasingly prone to being stored and/or read erroneously. An error control coding (ECC) engine is utilized to limit the number of uncorrectable errors that are introduced by electrical fluctuations, defects in the storage medium, operating conditions, device history, and/or write-read circuitry, etc. Additionally, for many error control codes, the decoding process can be improved by using soft information, which takes into account the associated probabilities of different interpretations of the results of one or more read operations. Hard information decoding generally means that an absolute decision is made as to whether a data value is one value or another. By contrast, soft information includes the probabilities that different interpretations of sensed electrical signals, corresponding to the results of one or more read operations, may be correct. By taking into consideration more information, soft information decoding often improves the error detection and correction capability of a particular error control code, and thus the data storage capacity of a system. However, the utilization of soft information decoding has a number of previously irresolvable drawbacks. For example, soft information decoding implementations tend to introduce undesirable delays (i.e., latencies), have relatively large semiconductor footprints, and are generally power and memory intensive. SUMMARY
[0004] Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. In one aspect, a single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. This facilitates timely production of hard and then soft information values representative of data stored in a storage medium.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various implementations, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.
[0006] Figure 1 is a diagram of an implementation of a data storage system, in accordance with some embodiments.
[0007] Figure 2 is a diagram of an implementation of a data storage system, including elements operable to produce soft information responsive to a command structure that facilitates timely production of hard and then soft information values from multiple read operations, in accordance with some embodiments.
[0008] Figure 3 is a diagram of an implementation of the soft information generation module included in Figure 2, in accordance with some embodiments.
[0009] Figure 4 is a flowchart representation of an implementation of a method of delivering read data as hard and then soft information values responsive to a command structure that facilitates timely production of hard and soft information from multiple read operations, in accordance with some embodiments.
[0010] Figure 5 is a flowchart representation of an implementation of a method of delivering read data as hard and then soft information values responsive to a command structure that facilitates timely production of hard and soft information from multiple read operations, in accordance with some embodiments.
[0011] In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.
DETAILED DESCRIPTION
[0012] As noted above, a drawback to employing soft information decoding is that previously available efforts tend to introduce undesirable delays (i.e., latencies), have relatively large semiconductor footprints, and are generally power and memory intensive. By contrast, the various implementations described herein provide a command structure and method of operation responsive to the command structure that facilitates timely production of hard and then soft information values representative of data stored in a storage medium.
[0013] Some implementations include a command structure that initiates a first read operation and then a sequence of one or more additional read operations from the same portion of memory as the first read operation. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values, and the first plurality of data values is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values.
Subsequent pluralities of data values are generated by the subsequent read operations until a terminating event occurs. In some implementations, so long as performance of the one or more additional read operations has not been terminated, in response to the completion of each of the one or more additional read operations, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. As used in the present disclosure, a hybrid plurality of data values is representative of a corresponding plurality of soft information values produced from two or more read operations from the same portion of memory.
[0014] More specifically, some implementations include a method for reading from a storage medium. In some implementations, the method includes receiving from a requesting device a control command of a first type. The method further includes responding to receiving the control command of the first type by (1) performing a first read operation, using a first reading signal value, to obtain a first plurality of data values from a portion of the storage medium, (2) after performing the first read operation, initiating performance of one or more additional read operations, each additional read operation using a respective reading signal value different from the first reading signal value to obtain a subsequent plurality of data values from the same portion of the storage medium as the first read operation, and (3) terminating performance of the one or more additional read operations upon the earlier of completion of a predefined number of the additional read operations and receiving a subsequent control command.
[0015] In some embodiments, the subsequent control command is of a type that causes termination of the one or more additional read operations.
[0016] In some embodiments, the method further includes storing the first plurality of data values in a buffer, transferring the first plurality of data values from the buffer to the requesting device, and initiating performance of a first additional read operation of the one or more additional read operations during a time period that overlaps with the transfer of the first plurality of data values from the buffer to the requesting device.
[0017] In some embodiments, the method further includes storing the first plurality of data values in a buffer, setting a status bit that is configured for reading by the requesting device, and initiating performance of a first additional read operation of the one or more additional read operations at a time period proximate to a time that the status bit is set.
[0018] In some embodiments, so long as performance of the one or more additional read operations has not been terminated, the method includes generating, in response to a completion of each of the one or more additional read operations, a respective hybrid plurality of data values by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values.
[0019] In some embodiments, the method further includes receiving from a requesting device a control command of a second type, wherein the second type differs from the first type by indicating a request for a single read of a respective portion of the storage medium. The method further includes responding to receiving the control command of the second type by (1) performing a single read operation to obtain data values from a portion of the storage medium, (2) storing the obtained data values in a buffer, and (3) transferring the obtained data values from the buffer to the requesting device.
[0020] In some embodiments, the one or more additional read operations is limited to a predefined number of read operations.
[0021] In some embodiments, initiating performance of one or more additional read operations occurs in response to a first condition. In some embodiments, the first condition includes receiving a message indicating that the first plurality of data values could not be decoded. In some embodiments, the first condition includes determining that a message, that indicates that the first plurality of data values can be decoded successfully, has not been received within a first duration. In some embodiments, the first condition includes determining that a message, that indicates that the first plurality of data values has been successfully decoded, has not been received within a first duration.
[0022] In some embodiments, the method further includes storing the first plurality of data values in a buffer, and transmitting a first message indicating that the first plurality of data values is available to be read from the buffer.
[0023] In some embodiments, the method further includes storing each respective hybrid plurality of data values in the buffer by overwriting any previously generated hybrid plurality of data values stored in the buffer, and transmitting a subsequent message indicating that a new hybrid plurality of data values is available to be read from the buffer each time a hybrid plurality of data values is newly stored in the buffer.
[0024] In some embodiments, generating each respective hybrid plurality of data values includes an exclusive-or (XOR) between each of the latest read of the one or more subsequent pluralities of data values and one of a previously generated hybrid plurality of data values and the first plurality of data values.
[0025] In another aspect, a device operable to read from a storage medium is configured to read data in accordance with any of the methods described above.
[0026] In some implementations, with respect to any of the methods described above, a device operable to read from a storage medium includes a storage medium and a controller configured to read data in accordance with any of the methods described above.
[0027] Numerous details are described herein in order to provide a thorough understanding of the example implementations illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.
[0028] Figure 1 is a diagram of an implementation of a data storage system 100, in accordance with some embodiments. While some example features are illustrated, various other features have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the example implementations disclosed herein. To that end, as a non- limiting example, data storage system 100 includes a memory controller 120, and a storage medium 130, and is used in conjunction with computer system 110. In some
implementations, storage medium 130 is a single flash memory device while in other implementations storage medium 130 includes a plurality of flash memory devices. In some implementations, storage medium 130 is NAND-type flash memory or NOR-type flash memory. Further, in some implementations memory controller 120 is a solid-state drive (SSD) controller. However, other types of storage media may be included in accordance with aspects of a wide variety of implementations.
[0029] Computer system 110 is coupled to memory controller 120 through data connections 101. However, in some implementations computer system 110 includes memory controller 120 as a component and/or a sub-system. Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device. Computer system 110 is sometimes called a host or host system. In some implementations, computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch screen display, a mouse, a track-pad, a digital camera and/or any number of supplemental devices to add functionality.
[0030] Storage medium 130 is coupled to memory controller 120 through connections
103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 130 and data values read from storage medium 130. In some implementations, however, memory controller 120 and storage medium 130 are included in the same device as components thereof. Furthermore, in some implementations memory controller 120 and storage medium 130 are embedded in a host device, such as a mobile device, tablet, other computer or computer controlled device. Storage medium 130 may include any number (i.e., one or more) of memory devices including, without limitation, non-volatile semiconductor memory devices, such as flash memory. For example, flash memory devices can be configured for enterprise storage suitable for applications such as cloud computing, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop and tablet computers.
[0031] Storage medium 130 is divided into a number of addressable and individually selectable blocks, such as selectable portion 131. In some implementations, the individually selectable blocks are the minimum size erasable units in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. Each block is usually further divided into a plurality of pages and/or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some implementations (e.g., using some types of flash memory), the smallest individually accessible unit of a data set, however, is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for reading data from the flash memory device.
[0032] For example, one block comprises any number of pages, for example, 64 pages, 128 pages, 256 pages, or another suitable number of pages. Blocks are typically grouped into a plurality of zones. Each block zone can be independently managed to some extent, which increases the degree of parallelism for parallel operations and simplifies management of storage medium 130.
[0033] As noted above, while data storage densities of non-volatile semiconductor memory devices are generally increasing, a drawback of increasing storage density is that the stored data is more prone to being stored and/or read erroneously. As described in greater detail below, error control coding can be utilized to limit the number of uncorrectable errors that are introduced by electrical fluctuations, defects in the storage medium, operating conditions, device history, write-read circuitry, etc., or a combination of these and various other factors.
[0034] In some implementations, memory controller 120 includes a management module 121, an input buffer 123, an output buffer 124, an error control module 125 and a storage medium interface (I/O) 128. Memory controller 120 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure more pertinent features of the example implementations disclosed herein, and that a different arrangement of features may be possible. Input and output buffers 123,124 provide an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 130 though connections 103. In some implementations, storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 130 (e.g., reading threshold voltages for NAND-type flash memory).
[0035] In some implementations, management module 121 includes one or more processing units (CPUs, also sometimes called processors) 122 configured to execute instructions in one or more programs (e.g., in management module 121). In some
implementations, the one or more CPUs 122 are shared by one or more components within, and in some cases, beyond the function of memory controller 120. Management module 121 is coupled to input buffer 123, output buffer 124 (connection not shown), error control module 125 and storage medium I/O 128 in order to coordinate the operation of these components.
[0036] Error control module 125 is coupled to storage medium I/O 128, input buffer
123 and output buffer 124. Error control module 125 is provided to limit the number of uncorrectable errors inadvertently introduced into data. In some embodiments, error control module 125 is executed in software by the one or more CPUs 122 of management module 121, and, in other embodiments, error control module 125 is implemented in whole or in part using special purpose circuitry to perform encoding and decoding functions. To that end, error control module 125 includes an encoder 126 and a decoder 127. Encoder 126 encodes data by applying an error control code to produce a codeword, which is subsequently stored in storage medium 130.
[0037] When the encoded data (e.g., one or more codewords) is read from storage medium 130, decoder 127 applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error control code. Those skilled in the art will appreciate that various error control codes have different error detection and correction capacities, and that particular codes are selected for various applications for reasons beyond the scope of this disclosure. As such, an exhaustive review of the various types of error control codes is not provided herein. Moreover, those skilled in the art will appreciate that each type or family of error control codes may have encoding and decoding algorithms that are particular to the type or family of error control codes. On the other hand some algorithms, such as the Viterbi algorithm, may be utilized at least to some extent in the decoding of a number of different types or families of error control codes. As such, for the sake of brevity, an exhaustive description of the various types of encoding and decoding algorithms generally available and known to those skilled in the art is not provided herein.
[0038] During a write operation, input buffer 123 receives data to be stored in storage medium 130 from computer system 110. The data held in input buffer 123 is made available to encoder 126, which encodes the data to produce one or more codewords. The one or more codewords are made available to storage medium I/O 128, which transfers the one or more codewords to storage medium 130 in a manner dependent on the type of storage medium being utilized.
[0039] A read operation is initiated when computer system (host) 110 sends one or more host read commands on control line 111 to memory controller 120 requesting data from storage medium 130. Memory controller 120 sends one or more read access commands to storage medium 130, via storage medium I/O 128, to obtain raw read data in accordance with memory locations (addresses) specified by the one or more host read commands. Storage medium I/O 128 provides the raw read data (e.g., comprising one or more codewords) to decoder 127. If the decoding is successful, the decoded data is provided to output buffer 124, where the decoded data is made available to computer system 110. In some implementations, if the decoding is not successful, memory controller 120 may resort to a number of remedial actions or provide an indication of an irresolvable error condition.
[0040] Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages. Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on). The magnitude of the charge, and the corresponding threshold voltage the charge creates, is used to represent one or more data values. In some implementations, during a read operation, a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.
[0041] The terms "cell voltage" and "memory cell voltage," in the context of flash memory cells, means the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current. Similarly, reading threshold voltages (sometimes also called reading signals and reading voltages) applied to a flash memory cells are gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage. In some im lementations, when a flash memory cell's transistor conducts current at a given reading threshold voltage, indicating that the cell voltage is less than the reading threshold voltage, the raw data value for that read operation is a "1" and otherwise the raw data value is a "0."
[0042] In some implementations, the memory cell voltage of a memory cell is read indirectly, by reading the memory cell using one or more reading threshold voltages. More specifically, each read operation produces a result that indicates whether the cell voltage of the memory cell is greater than or less than the reading threshold voltage used during that read operation. By reading the memory cell using multiple reading threshold voltages, the cell voltage can be determined more precisely than if the memory cell were read using only a single reading threshold voltage. Stated another way, the more read operations that are performed on a memory cell, each using a different reading threshold voltage, the more precisely the cell voltage of the memory cell is known.
[0043] Figure 2 is a diagram of an implementation of a data storage system 200, including elements operable to produce soft information responsive to a command structure that facilitates timely production of hard and then soft information values from multiple read operations. Data storage system 200 illustrated in Figure 2 is similar to and adapted from data storage system 100 illustrated in Figure 1. Elements common to each include common reference numbers, and only the differences between Figures 1 and 2 are described herein for the sake of brevity. Moreover, while certain specific features are illustrated, various other features have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the example implementations disclosed herein.
[0044] With reference to Figure 2, as a non-limiting example, storage medium 230 generally comprises a memory chip. Those skilled in the art will appreciate from the present disclosure that, in various other implementations, storage medium 230 includes various other types of memory devices, including two or more memory chips. Storage medium 230 includes a NAND flash cell array 231, a write buffer 232, a chip controller 236, read-write (R/W) access circuitry 237, a page buffer 235, and a multiplexer (MUX) 234.
[0045] Storage medium I/O 128 is coupled to storage medium 230 through connections 103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 130 and data values read from storage medium 230. More specifically, with continued reference to Figure 2, storage medium I/O 128 is coupled to deliver write data to write buffer 232, and also coupled to chip controller 236 to convey at least one of commands, metadata and representations of one or more reading signal values (e.g., reading threshold voltages). Chip controller 236 is coupled to provide control commands, including read and write commands, to R/W access circuitry 237. R/W access circuitry 237 is also coupled to receive (or retrieve) write data from write buffer 232.
[0046] R/W access circuitry 237 is also coupled to NAND flash cell array 231.
During a write operation, R W access circuitry 237 operates to write data from write buffer 232 into a selectable portion of NAND flash cell array 231, such as for example, selectable portion of flash array 231-1. During a read operation, R/W access circuitry 237 operates to read data stored in NAND flash cell array 231. Read data is copied into page buffer 235. Storage medium I/O 128 is also coupled to receive read data (as either hard or soft information values) through MUX 234. Data read from the NAND flash cell array 231 is stored in page buffer 235, and is made accessible to storage medium I/O 128 through MUX 234. Chip controller 236 provides a control signal to MUX 234 that allows the storage medium I/O 128 to access the read data in page buffer 235 through MUX 234. In turn, storage medium I/O 128 stores read data from buffer 235 in stage buffer 228.
[0047] Figure 3 is a diagram of an implementation of soft information generation module 229 included in Figure 2, in accordance with some embodiments. Again, as noted above, while certain specific features are illustrated, those skilled in the art will appreciate from the present disclosure that various other features have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the example implementations disclosed herein. To that end, as a non-limiting example, the soft information generation module 229 includes a soft information management controller 510, a characterization module 520, a calculation/adjustment module 530, and an output multiplex (MUX) 540. Soft information generation module 229 is coupled to decoder 127.
[0048] The soft information management controller 510 is coupled to each of the characterization module 520, calculation/adjustment module 530, and MUX 540 in order to coordinate the operation of soft information generation module 229. More specifically, in some implementations, soft information management controller 510 is connected to receive a read request and one or more storage medium characterization parameters on control and data lines 501 and 502, respectively. Soft information management controller 510 is also connected to provide characterization module 520 a selection control signal on control line 511, and to receive a selected characterization vector on data line 512. In some
implementations, soft information management controller 510 is further connected to provide reading threshold voltages to the storage medium I/O 128 via data line 514, and to receive raw read data from the storage medium I/O 128 on data line 515 by way of page buffer 235 (Figure 2) and multiplexer 234 (Figure 2). Soft information management controller 510 is also connected to provide sequences of soft information values to the calculation/adjustment module 530 and output MUX 540 via corresponding data lines 516 and 517, and a control signal to output MUX 540 via control line 503. Output MUX 540 is also connected to receive adjusted soft information values from calculation/adjustment module 530 on data line 531. Output MUX 540 is connected to selectively provide soft information values from one of conversion module 533 and calculation/adjustment module 530 on data line 541 depending on the control signal received on control line 503.
[0049] Characterization module 520 includes a collection of characterization vectors
521-1, 521-2, 521-3,... 521-n, that each store characterization data, such as soft information values for bit-tuples and read comparison signal values, associated with storage medium 130 for one or more storage medium characterization parameter values. In some
implementations, the characterization data stored in the characterization vectors 521 is statistically derived. Each combination of storage medium characterization parameter values represents a respective state of a storage medium that may be characterized in a device characterization process, and may exist for other devices produced by the same
manufacturing process
[0050] Soft information management controller 510 includes a selection module 531, an optional read controller 532, and a conversion module 533. Selection module 531 is configured to use the one or more storage medium characterization parameters values to select a characterization vector from the stored collection of characterization vectors 521-1, 521-2, 521-3,... 521-n in accordance with the current state of storage medium 130. The selection control signal includes one or more of storage medium characterization parameters values and/or an index key associated with a combination of one or more of storage medium characterization parameters values that enables characterization module 520 to select a characterization vector based on the one or more storage medium characterization parameters values associated with the current state of the storage medium 130. [0051] Optional read controller 532 is configured to read a portion of the storage medium 130 via storage medium I/O 128. In some implementations, read controller 532 is configured to provide storage medium I/O 128 with read comparison signal values for the read operation. In some implementations, read controller 532 selects one or more statistically determined read comparison signal values from a characterization vector selected based on the one or more storage medium characterization parameter values associated with the current state of storage medium 130.
[0052] Conversion module 533 is configured to generate a sequence of soft information values corresponding to raw hard-decision read data. The sequence of soft information values is generated, at least in part, by selecting a respective soft information value from the selected characterization vector for each bit-tuple of the raw hard-decision read data produced by a read operation using a corresponding reading threshold voltage value. More specifically, in some implementations, the conversion module 533 assigns at least one soft information value, in the form of a LLR, to each bit-tuple in the hard-decision read data to produce a corresponding sequence of LLRs yLLR = (y1, y2>> yn-i where n is the codeword length.
[0053] Calculation/adjustment module 530 is configured to optionally adjust soft information values in response to one or more characterization parameter values associated with a current state of the storage medium and/or previously detected error characterizations.
[0054] Figure 4 is a flowchart representation of an implementation of a method 400 of delivering read data as hard and then soft information values responsive to a command structure that facilitates timely production of hard and then soft information values from multiple read operations. In some implementations, method 400 is performed by a chip controller associated with a memory cell array, such as chip controller 236 (shown in Figure 2). Briefly, method 400 includes responding to receiving a control command of a first type by initiating a first read operation and then a sequence of one or more additional read operations from the same portion of memory as the first read operation. The additional read operations are terminable after a first plurality of data values is provided to the requesting device.
[0055] To that end, as represented by block 4-1, method 400 includes receiving from a requesting device a control command of a first type. As represented by block 4- la, the control command of the first type instructs a receiving device to initiate a first read operation and then a sequence of one or more additional read operations from the same portion of memory as the first read operation. In other words, the control command of the first type is a continuous read command. For example, with reference to Figures 2 and 4, chip controller 236 receives a continuous read command transmitted from storage medium I/O 128.
[0056] As represented by block 4-2, method 400 includes, responding to receiving the control command of the first type by performing a first read operation, using a first reading signal value (e.g., reading threshold voltage), to obtain a first plurality of data values from a portion of the storage medium. For example, with continued reference to Figures 2 and 4, chip controller 236 provides a first read command and a first reading threshold voltage to R/W access circuitry 237. R/W access circuitry 237 operates to read a first plurality of data from NAND flash cell array 231. First plurality of data values read from NAND flash cell array 231 is copied into page buffer 235.
[0057] As represented by block 4-3, after performing the first read operation, method
400 includes further responding to receiving the control command of the first type by initiating performance of one or more additional read operations, each additional read operation using a respective reading signal value different from the first reading signal value to obtain a subsequent plurality of data values from the same portion of the storage medium as the first read operation. For example, with continued reference to Figures 2 and 4, chip controller 236 iteratively provides subsequent read commands and respective subsequent reading threshold voltages to R/W access circuitry 237. In response to receiving each subsequent read command and the respective subsequent reading threshold voltage, R/W access circuitry 237 operates to read a respective subsequent plurality of data from NAND flash cell array 231. Each respective subsequent plurality of data values read from NAND flash cell array 231 is copied into page buffer 235.
[0058] Additionally, in some implementations, initiating performance of one or more additional read operations occurs in response to a first condition. In some implementations, the first condition includes receiving a message indicating that the first plurality of data values could not be decoded. In some implementations, the first condition includes determining that a message, that indicates that the first plurality of data values can be decoded successfully, has not been received within a first duration. In some
implementations, the first condition includes determining that a message, that indicates that the first plurality of data values has been successfully decoded, has not been received within a first duration. [0059] As represented by block 4-4, method 400 includes determining whether an iteration limit has been reached. In some implementations, the iteration limit defines a limit on the number of one or more additional read operations that are performed in response to the control command of the first type. As such, the one or more additional read operations is limited to a predefined number of read operations. If the iteration limit has been reached ("Yes" path from block 4-4), method 400 terminates. On the other hand, if the iteration limit has not been reached ("No" path from block 4-4), as represented by block 4-5, method 400 includes determining if another command has been received. If another command has been received ("Yes" path from block 4-5), method 400 terminates. On the other hand, if another command has not been received ("No" path from block 4-4), method 400 loops back to the portion of the method represented by block 4-3 so that subsequent read operations can be performed as described. In some implementations, the subsequent control command is of a type that causes termination of the one or more additional read operations. In some implementations, any subsequently received control command signals the termination of the one or more additional read operations.
[0060] In some implementations, as represented by the combination of blocks 4-4 and
4-5, method 400 includes terminating performance of the one or more additional read operations upon the earlier of completion of a predefined number of the additional read operations and receiving a subsequent control command. Moreover, in some
implementations, the portions of method 400 represented by blocks 4-4 and 4-5 occur in the opposite order, or simultaneously with respect to one another. In some implementations the portions of method 400 represented by blocks 4-4 and 4-5 also occur simultaneously with the portion of method 400 represented by block 4-3, thereby enabling the one or more additional read operations to be terminable at any time after the first plurality of data values is made available to the requesting device and/or module.
[0061] Figure 5 is a flowchart representation of an implementation of a method 500 of delivering read data as hard and then soft information values responsive to a command structure that facilitates timely production of hard and then soft information values from multiple read operations, in accordance with some implementations. In some
implementations, method 500 is performed by a chip controller associated with a memory cell array, such as chip controller 236 (shown in Figure 2). Briefly, method 500 includes responding to receiving a control command of a first type by initiating a first read operation and then a sequence of one or more additional read operations from the same portion of memory as the first read operation. The additional read operations are terminable after a first plurality of data values is provided to the requesting device.
[0062] To that end, as represented by block 5-1, method 500 includes receiving from a requesting device a control command of a first type. In other words, the control command of the first type is a continuous read command. For example, with reference to Figures 2 and 5, chip controller 236 receives a continuous read command transmitted from storage medium I/O 128.
[0063] As represented by block 5-2, method 500 includes, responding to receiving the control command of the first type by performing a first read operation, using a first reading signal value, to obtain a first plurality of data values from a portion of the storage medium. For example, with continued reference to Figures 2 and 5, chip controller 236 provides a first read command and a first reading threshold voltage to R/W access circuitry 237. R W access circuitry 237 operates to read a first plurality of data from NAND flash cell array 231. First plurality of data values read from NAND flash cell array 231 is copied into page buffer 235.
[0064] As represented by block 5-3, method 500 includes storing the first plurality of data values in a buffer. For example, with continued reference to Figures 2 and 5, the first plurality of data values read from NAND flash cell array 231 is copied into page buffer 235. From the portion of the method represented by block 5-3, method 500 takes two operational paths that are performed proximate in time to one another and/or simultaneously. Along one path, as represented by block 5-4, method 500 includes facilitating transfer of the first plurality of data values to a requesting device. In some implementations, as represented by block 5 -4a, facilitating the transfer of the first plurality of data values to the requesting device includes setting a status bit that is configured for reading by the requesting device. For example, with continued reference to Figures 2 and 5, chip controller 236 sets a status bit that is readable by storage medium I/O 128 over connections 103. In some implementations, as represented by block 5-4b, facilitating the transfer of the first plurality of data values to the requesting device includes transferring the first plurality of data values from the buffer to the requesting device. For example, with continued reference to Figures 2 and 5, chip controller 236 provides MUX 234 with a drive signal that enables the MUX 234 to push the first plurality of data from page buffer 235 to storage medium I/O 128 in memory controller 120 over connections 103. [0065] Along another path, as represented by block 5-5, after performing the first read operation, method 500 includes further responding to receiving the control command of the first type by initiating performance of an additional read operation using a respective reading signal value different from the first reading signal value to obtain a subsequent plurality of data values from the same portion of the storage medium as the first read operation. For example, with continued reference to Figures 2 and 5, chip controller 236 iteratively provides subsequent read commands and respective subsequent reading threshold voltages to R/W access circuitry 237. In response to receiving each subsequent read command and the respective subsequent reading threshold voltage, R/W access circuitry 237 operates to read a respective subsequent plurality of data from NAND flash cell array 231. Each respective subsequent plurality of data values read from NAND flash cell array 231 is copied into page buffer 235. In some implementations, method 500 includes initiating performance of a first additional read operation of the one or more additional read operations during a time period that overlaps with the transfer of the first plurality of data values from the buffer to the requesting device. In some implementations, method 500 includes initiating performance of a first additional read operation of the one or more additional read operations at a time period proximate to a time that the status bit is set.
[0066] Additionally, in some implementations, initiating performance of one or more additional read operations occurs in response to a first condition. In some implementations, the first condition includes receiving a message indicating that the first plurality of data values could not be decoded. In some implementations, the first condition includes determining that a message, that indicates that the first plurality of data values can be decoded successfully, has not been received within a first duration. In some
implementations, the first condition includes determining that a message, that indicates that the first plurality of data values has been successfully decoded, has not been received within a first duration.
[0067] As represented by block 5-6, method 500 includes storing each additional plurality of data values in a buffer. For example, with further reference to Figures 2 and 5, each respective subsequent plurality of data values read from NAND flash cell array 231 is copied into page buffer 235. As represented by block 5-7, method 500 includes generating a hybrid plurality of data values in the buffer. In other words, in some implementations, so long as performance of the one or more additional read operations has not been terminated, method 500 includes generating, in response to a completion of each of the one or more additional read operations, a respective hybrid plurality of data values by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. In some implementations, method 500 also includes storing each respective hybrid plurality of data values in the buffer by overwriting any previously generated hybrid plurality of data values stored in the buffer. In some
implementations, generating each respective hybrid plurality of data values includes an exclusive-or (XOR) between each of the latest read of the one or more subsequent pluralities of data values and one of a previously generated hybrid plurality of data values and the first plurality of data values.
[0068] As represented by block 5-8, method 500 includes facilitating transfer of the hybrid plurality of data values to the requesting device. In some implementations, facilitating transfer of the hybrid plurality of data values to the requesting device by transmitting a first message indicating that the first plurality of data values is available to be read from the buffer. In some implementations, facilitating transfer of the hybrid plurality of data values to the requesting device by transmitting a subsequent message indicating that a new hybrid plurality of data values is available to be read from the buffer each time a hybrid plurality of data values is newly stored in the buffer.
[0069] As represented by block 5-9, method 500 includes determining whether an iteration limit has been reached. In some implementations, the iteration limit defines a limit on the number of one or more additional read operations that are performed in response to the control command of the first type. If the iteration limit has been reached ("Yes" path from block 5-9), method 500 terminates. On the other hand, if the iteration limit has not been reached ("No" path from block 5-9), as represented by block 5-10, method 500 includes determining if another command has been received. If another command has been received ("Yes" path from block 5-10), method 500 terminates. On the other hand, if another command has not been received ("No" path from block 5-10), method 500 loops back to the portion of the method represented by block 5-5 so that subsequent read operations can be performed as described. In some implementations, the subsequent control command is of a type that causes termination of the one or more additional read operations. In some implementations, any subsequently received control command signals the termination of the one or more additional read operations.
[0070] In some implementations, as represented by the combination of blocks 5-9 and
5-10, method 500 includes terminating performance of the one or more additional read operations upon the earlier of completion of a predefined number of the additional read operations and receiving a subsequent control command. Moreover, in some
implementations, the portions of method 500 represented by blocks 5-9 and 5-10 occur in the opposite order, or simultaneously with respect to one another. In some implementations the portions of method 500 represented by blocks 5-9 and 5-10 also occur simultaneously with the portion of method 500 represented by block 5-5, thereby enabling the one or more additional read operations to be terminable at any time after the first plurality of data values is made available to the requesting device and/or module.
[0071] It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the "first contact" are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.
[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0073] As used herein, the term "if may be construed to mean "when" or "upon" or
"in response to determining" or "in accordance with a determination" or "in response to detecting," that a stated condition precedent is true, depending on the context. Similarly, the phrase "if it is determined [that a stated condition precedent is true]" or "if [a stated condition precedent is true]" or "when [a stated condition precedent is true]" may be construed to mean "upon determining" or "in response to determining" or "in accordance with a determination" or "upon detecting" or "in response to detecting" that the stated condition precedent is true, depending on the context.
[0074] The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The
implementations were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.

Claims

What is claimed is:
1. A method of reading from a storage medium, the method comprising:
receiving from a requesting device a control command of a first type;
responding to receiving the control command of the first type by:
performing a first read operation, using a first reading signal value, to obtain a first plurality of data values from a portion of the storage medium;
after performing the first read operation, initiating performance of one or more additional read operations, each additional read operation using a respective reading signal value different from the first reading signal value to obtain a subsequent plurality of data values from the same portion of the storage medium as the first read operation; and
terminating performance of the one or more additional read operations upon the earlier of completion of a predefined number of the additional read operations and receiving a subsequent control command.
2. The method of claim 1, wherein the subsequent control command is of a type that causes termination of the one or more additional read operations.
3. The method of claim 1, further comprising:
storing the first plurality of data values in a buffer;
transferring the first plurality of data values from the buffer to the requesting device; and
initiating performance of a first additional read operation of the one or more additional read operations during a time period that overlaps with the transfer of the first plurality of data values from the buffer to the requesting device.
4. The method of claim 1, further comprising:
storing the first plurality of data values in a buffer;
setting a status bit that is configured for reading by the requesting device; and initiating performance of a first additional read operation of the one or more additional read operations at a time period proximate to a time that the status bit is set.
5. The method of claim 1, wherein so long as performance of the one or more additional read operations has not been terminated, the method includes generating, in response to a completion of each of the one or more additional read operations, a respective hybrid plurality of data values by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values.
6. The method of claim 1, further comprising:
receiving from a requesting device a control command of a second type, wherein the second type differs from the first type by indicating a request for a single read of a respective portion of the storage medium;
responding to receiving the control command of the second type by:
performing a single read operation to obtain data values from a portion of the storage medium;
storing the obtained data values in a buffer; and transferring the obtained data values from the buffer to the requesting device.
7. The method of any of claims 1-5, wherein the one or more additional read operations is limited to a predefined number of read operations.
8. The method of any of claims 1-5, wherein initiating performance of one or more additional read operations occurs in response to a first condition.
9. The method of claim 8, wherein the first condition includes receiving a message indicating that the first plurality of data values could not be decoded.
10. The method of claim 8, wherein the first condition includes determining that a message, that indicates that the first plurality of data values can be decoded successfully, has not been received within a first duration.
11. The method of claim 8, wherein the first condition includes determining that a message, that indicates that the first plurality of data values has been successfully decoded, has not been received within a first duration.
12. The method of claim 5, further comprising:
storing the first plurality of data values in a buffer; and
transmitting a first message indicating that the first plurality of data values is available to be read from the buffer.
13. The method of claim 12, further comprising:
storing each respective hybrid plurality of data values in the buffer by overwriting any previously generated hybrid plurality of data values stored in the buffer; and
transmitting a subsequent message indicating that a new hybrid plurality of data values is available to be read from the buffer each time a hybrid plurality of data values is newly stored in the buffer.
14. The method of claim 5, wherein generating each respective hybrid plurality of data values includes an exclusive-or (XOR) between each of the latest read of the one or more subsequent pluralities of data values and one of a previously generated hybrid plurality of data values and the first plurality of data values.
15. A device, comprising :
a storage medium; and
a controller configured to:
receive from a requesting device a control command of a first type;
respond to receiving the control command of the first type by:
performing a first read operation, using a first reading signal value, to obtain a first plurality of data values from a portion of the storage medium;
after performing the first read operation, initiating performance of one or more additional read operations, each additional read operation using a respective reading signal value different from the first reading signal value to obtain a subsequent plurality of data values from the same portion of the storage medium as the first read operation; and terminating performance of the one or more additional read operations upon the earlier of completion of a predefined number of the additional read operations and receiving a subsequent control command.
16. The device of claim 15, wherein the subsequent control command is of a type that causes termination of the one or more additional read operations.
17. The device of claim 15, wherein the controller is further configured to:
store the first plurality of data values in a buffer;
transfer the first plurality of data values from the buffer to the requesting device; and initiate performance of a first additional read operation of the one or more additional read operations during a time period that overlaps with the transfer of the first plurality of data values from the buffer to the requesting device.
18. The device of claim 15, wherein the controller is further configured to:
store the first plurality of data values in a buffer;
set a status bit that is configured for reading by the requesting device; and
initiate performance of a first additional read operation of the one or more additional read operations at a time period proximate to a time that the status bit is set.
19. The device of claim 15, wherein so long as performance of the one or more additional read operations has not been terminated, the method includes generating, in response to a completion of each of the one or more additional read operations, a respective hybrid plurality of data values by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values.
20. The device of claim 15, wherein the controller is configured to:
receive from a requesting device a control command of a second type, wherein the second type differs from the first type by indicating a request for a single read of a respective portion of the storage medium;
respond to receiving the control command of the second type by:
performing a single read operation to obtain data values from a portion of the storage medium;
storing the obtained data values in a buffer; and transferring the obtained data values from the buffer to the requesting device.
21. The device of any of claims 15-19, wherein the one or more additional read operations is limited to a predefined number of read operations.
22. The device of any of claims 15-19, wherein initiating performance of one or more additional read operations occurs in response to a first condition.
23. The device of claim 22, wherein the first condition includes receiving a message indicating that the first plurality of data values could not be decoded.
24. The device of claim 22, wherein the first condition includes determining that a message, that indicates that the first plurality of data values can be decoded successfully, has not been received within a first duration.
25. The device of claim 22, wherein the first condition includes determining that a message, that indicates that the first plurality of data values has been successfully decoded, has not been received within a first duration.
26. The device of claim 19, wherein the controller is further configured to:
store the first plurality of data values in a buffer; and
transmit a first message indicating that the first plurality of data values is available to be read from the buffer.
27. The device of claim 26, wherein the controller is further configured to:
store each respective hybrid plurality of data values in the buffer by overwriting any previously generated hybrid plurality of data values stored in the buffer; and
transmit a subsequent message indicating that a new hybrid plurality of data values is available to be read from the buffer each time a hybrid plurality of data values is newly stored in the buffer.
28. The device of claim 19, wherein generating each respective hybrid plurality of data values includes an exclusive-or (XOR) between each of the latest read of the one or more subsequent pluralities of data values and one of a previously generated hybrid plurality of data values and the first plurality of data values.
PCT/US2014/029453 2013-03-15 2014-03-14 Performance optimization of data transfer for soft information generation WO2014144864A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020157024578A KR101982381B1 (en) 2013-03-15 2014-03-14 Performance optimization of data transfer for soft information generation
CN201480015991.9A CN105264496B (en) 2013-03-15 2014-03-14 For the performance optimization of the data transmission of Soft Inform ation generation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361801463P 2013-03-15 2013-03-15
US61/801,463 2013-03-15
US13/963,444 US9367246B2 (en) 2013-03-15 2013-08-09 Performance optimization of data transfer for soft information generation
US13/963,444 2013-08-09

Publications (1)

Publication Number Publication Date
WO2014144864A1 true WO2014144864A1 (en) 2014-09-18

Family

ID=51533763

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/029453 WO2014144864A1 (en) 2013-03-15 2014-03-14 Performance optimization of data transfer for soft information generation

Country Status (4)

Country Link
US (1) US9367246B2 (en)
KR (1) KR101982381B1 (en)
CN (1) CN105264496B (en)
WO (1) WO2014144864A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761312B1 (en) 2016-03-16 2017-09-12 Micron Technology, Inc. FeRAM-DRAM hybrid memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070091677A1 (en) * 2005-10-25 2007-04-26 M-Systems Flash Disk Pioneers Ltd. Method for recovering from errors in flash memory
US20070201274A1 (en) * 2000-01-06 2007-08-30 Super Talent Electronics Inc. Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory
US20080056005A1 (en) * 2006-08-30 2008-03-06 Micron Technology, Inc. Non-volatile memory cell read failure reduction
US20090292972A1 (en) * 2008-05-23 2009-11-26 Samsung Electronics Co., Ltd. Error correction apparatus, method thereof and memory device comprising the apparatus
WO2011024015A1 (en) * 2009-08-25 2011-03-03 Sandisk Il Ltd. Restoring data into a flash storage device
US20110051513A1 (en) * 2009-08-25 2011-03-03 Micron Technology, Inc. Methods, devices, and systems for dealing with threshold voltage change in memory devices

Family Cites Families (420)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4173737A (en) 1978-05-04 1979-11-06 Zenith Radio Corporation Limited position, non-volatile memory tuning system
US4888750A (en) 1986-03-07 1989-12-19 Kryder Mark H Method and system for erase before write magneto-optic recording
US4916652A (en) 1987-09-30 1990-04-10 International Business Machines Corporation Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
US5129089A (en) * 1987-12-18 1992-07-07 Digital Equipment Corporation Distributed interlock apparatus and distributed interlock management method
US5270979A (en) 1991-03-15 1993-12-14 Sundisk Corporation Method for optimum erasing of EEPROM
US5657332A (en) 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
US5381528A (en) * 1992-10-15 1995-01-10 Maxtor Corporation Demand allocation of read/write buffer partitions favoring sequential read cache
US5416915A (en) 1992-12-11 1995-05-16 International Business Machines Corporation Method and system for minimizing seek affinity and enhancing write sensitivity in a DASD array
US5537555A (en) 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US5519847A (en) 1993-06-30 1996-05-21 Intel Corporation Method of pipelining sequential writes in a flash memory
US5329491A (en) 1993-06-30 1994-07-12 Intel Corporation Nonvolatile memory card with automatic power supply configuration
US5708849A (en) 1994-01-26 1998-01-13 Intel Corporation Implementing scatter/gather operations in a direct memory access device on a personal computer
US5696917A (en) 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
GB9419246D0 (en) 1994-09-23 1994-11-09 Cambridge Consultants Data processing circuits and interfaces
US5666114A (en) 1994-11-22 1997-09-09 International Business Machines Corporation Method and means for managing linear mapped address spaces storing compressed data at the storage subsystem control unit or device level
US5530705A (en) 1995-02-08 1996-06-25 International Business Machines Corporation Soft error recovery system and method
US5636342A (en) 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
US5606532A (en) 1995-03-17 1997-02-25 Atmel Corporation EEPROM array with flash-like core
KR100404650B1 (en) 1995-06-14 2004-02-11 히다치초엘에스아이 엔지니어링가부시키가이샤 Semiconductor memory, memory device and memory card
US5890193A (en) 1995-07-28 1999-03-30 Micron Technology, Inc. Architecture for state machine for controlling internal operations of flash memory
US6728851B1 (en) 1995-07-31 2004-04-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US5815434A (en) 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US6044472A (en) 1996-06-21 2000-03-28 Archos Device and method for supplying power to an external data medium reader unit connected to a computer, and external reader unit including this device
KR100412589B1 (en) 1996-07-05 2004-04-06 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor Circuit System, Method for Testing Semiconductor Intergrated Circuits, and Method for Generating a Test Sequence for Testing Thereof
US6134148A (en) 1997-09-30 2000-10-17 Hitachi, Ltd. Semiconductor integrated circuit and data processing system
JPH10124381A (en) 1996-10-21 1998-05-15 Mitsubishi Electric Corp Semiconductor storage device
US5943692A (en) 1997-04-30 1999-08-24 International Business Machines Corporation Mobile client computer system with flash memory management utilizing a virtual address map and variable length data
US6006345A (en) 1997-05-09 1999-12-21 International Business Machines Corporation Pattern generator for memory burn-in and test
US6000006A (en) 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
JPH11126497A (en) 1997-10-22 1999-05-11 Oki Electric Ind Co Ltd Non-volatile semiconductor memory
US6018304A (en) 1997-12-18 2000-01-25 Texas Instruments Incorporated Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability
US6070074A (en) 1998-04-24 2000-05-30 Trw Inc. Method for enhancing the performance of a regenerative satellite communications system
US6138261A (en) 1998-04-29 2000-10-24 Trw Inc. Concatenated coding system for satellite communications
US6182264B1 (en) 1998-05-22 2001-01-30 Vlsi Technology, Inc. Smart dynamic selection of error correction methods for DECT based data services
US7111293B1 (en) 1998-06-03 2006-09-19 Ants Software, Inc. Method for increased concurrency in a computer system
US6192092B1 (en) 1998-06-15 2001-02-20 Intel Corp. Method and apparatus for clock skew compensation
US6260120B1 (en) 1998-06-29 2001-07-10 Emc Corporation Storage mapping and partitioning among multiple host processors in the presence of login state changes and host controller replacement
US6505305B1 (en) 1998-07-16 2003-01-07 Compaq Information Technologies Group, L.P. Fail-over of multiple memory blocks in multiple memory modules in computer system
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6295592B1 (en) 1998-07-31 2001-09-25 Micron Technology, Inc. Method of processing memory requests in a pipelined memory controller
US6233625B1 (en) 1998-11-18 2001-05-15 Compaq Computer Corporation System and method for applying initialization power to SCSI devices
US6288860B1 (en) 1999-01-04 2001-09-11 Maxtor Corporation Servo area numbering strategy for computer disk drives
US6438661B1 (en) 1999-03-03 2002-08-20 International Business Machines Corporation Method, system, and program for managing meta data in a storage system and rebuilding lost meta data in cache
US6449625B1 (en) 1999-04-20 2002-09-10 Lucent Technologies Inc. Use of a two-way stack approach to optimize flash memory management for embedded database systems
US6564271B2 (en) 1999-06-09 2003-05-13 Qlogic Corporation Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
US7620769B2 (en) 2000-01-06 2009-11-17 Super Talent Electronics, Inc. Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory
US7318117B2 (en) 2004-02-26 2008-01-08 Super Talent Electronics, Inc. Managing flash memory including recycling obsolete sectors
US20080282128A1 (en) 1999-08-04 2008-11-13 Super Talent Electronics, Inc. Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance
US20050114587A1 (en) 2003-11-22 2005-05-26 Super Talent Electronics Inc. ExpressCard with On-Card Flash Memory with Shared Flash-Control Bus but Separate Ready Lines
US7660941B2 (en) 2003-09-10 2010-02-09 Super Talent Electronics, Inc. Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories
US6412042B1 (en) 1999-11-17 2002-06-25 Maxtor Corporation System and method for improved disk drive performance and reliability
US6484224B1 (en) 1999-11-29 2002-11-19 Cisco Technology Inc. Multi-interface symmetric multiprocessor
DE19961138C2 (en) 1999-12-17 2001-11-22 Siemens Ag Multiport RAM memory device
US7082056B2 (en) 2004-03-12 2006-07-25 Super Talent Electronics, Inc. Flash memory device and architecture with multi level cells
US8037234B2 (en) 2003-12-02 2011-10-11 Super Talent Electronics, Inc. Command queuing smart storage transfer manager for striping data to raw-NAND flash modules
US6339338B1 (en) 2000-01-18 2002-01-15 Formfactor, Inc. Apparatus for reducing power supply noise in an integrated circuit
US20020152305A1 (en) 2000-03-03 2002-10-17 Jackson Gregory J. Systems and methods for resource utilization analysis in information management environments
US6516437B1 (en) 2000-03-07 2003-02-04 General Electric Company Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates
US6629047B1 (en) 2000-03-30 2003-09-30 Intel Corporation Method and apparatus for flash voltage detection and lockout
US6615307B1 (en) 2000-05-10 2003-09-02 Micron Technology, Inc. Flash with consistent latency for read operations
US20030188045A1 (en) 2000-04-13 2003-10-02 Jacobson Michael B. System and method for distributing storage controller tasks
US6647387B1 (en) 2000-04-27 2003-11-11 International Business Machine Corporation System, apparatus, and method for enhancing storage management in a storage area network
US6678788B1 (en) 2000-05-26 2004-01-13 Emc Corporation Data type and topological data categorization and ordering for a mass storage system
US6934755B1 (en) 2000-06-02 2005-08-23 Sun Microsystems, Inc. System and method for migrating processes on a network
US6442076B1 (en) 2000-06-30 2002-08-27 Micron Technology, Inc. Flash memory with multiple status reading capability
US6980985B1 (en) 2000-08-30 2005-12-27 At&T Corp. Distributed evalulation of directory queries using a topology cache
US6865650B1 (en) 2000-09-29 2005-03-08 Emc Corporation System and method for hierarchical data storage
US7028165B2 (en) 2000-12-06 2006-04-11 Intel Corporation Processor stalling
US6862651B2 (en) 2000-12-20 2005-03-01 Microsoft Corporation Automotive computing devices with emergency power shut down capabilities
US6738870B2 (en) 2000-12-22 2004-05-18 International Business Machines Corporation High speed remote storage controller
KR100381955B1 (en) 2001-01-03 2003-04-26 삼성전자주식회사 Flash memory device with cell current measuring scheme using a write driver
US6754773B2 (en) 2001-01-29 2004-06-22 Snap Appliance, Inc. Data engine with metadata processor
WO2002082435A1 (en) 2001-03-30 2002-10-17 Fujitsu Limited Storage device
US7017107B2 (en) 2001-04-30 2006-03-21 Sun Microsystems, Inc. Storage array employing scrubbing operations at the disk-controller level
US6938253B2 (en) 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
US6757768B1 (en) 2001-05-17 2004-06-29 Cisco Technology, Inc. Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
JP4256600B2 (en) 2001-06-19 2009-04-22 Tdk株式会社 MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD
US7068603B2 (en) 2001-07-06 2006-06-27 Juniper Networks, Inc. Cross-bar switch
US6836815B1 (en) 2001-07-11 2004-12-28 Pasternak Solutions Llc Layered crossbar for interconnection of multiple processors and shared memories
US6928602B2 (en) 2001-07-18 2005-08-09 Sony Corporation Encoding method and encoder
JP4569055B2 (en) 2001-08-06 2010-10-27 ソニー株式会社 Signal processing apparatus and signal processing method
TW539946B (en) 2001-08-07 2003-07-01 Solid State System Company Ltd Window-based flash memory storage system, and the management method and the access method thereof
JP4437519B2 (en) 2001-08-23 2010-03-24 スパンション エルエルシー Memory controller for multilevel cell memory
US7028213B2 (en) 2001-09-28 2006-04-11 Hewlett-Packard Development Company, L.P. Error indication in a raid memory system
US7032123B2 (en) 2001-10-19 2006-04-18 Sun Microsystems, Inc. Error recovery
JP3663377B2 (en) 2001-10-23 2005-06-22 インターナショナル・ビジネス・マシーンズ・コーポレーション Data storage device, read data processing device, and read data processing method
US7380085B2 (en) 2001-11-14 2008-05-27 Intel Corporation Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
US6798696B2 (en) 2001-12-04 2004-09-28 Renesas Technology Corp. Method of controlling the operation of non-volatile semiconductor memory chips
US6871257B2 (en) 2002-02-22 2005-03-22 Sandisk Corporation Pipelined parallel programming operation in a non-volatile memory system
US6836808B2 (en) 2002-02-25 2004-12-28 International Business Machines Corporation Pipelined packet processing
US7533214B2 (en) 2002-02-27 2009-05-12 Microsoft Corporation Open architecture flash driver
KR100476888B1 (en) 2002-04-04 2005-03-17 삼성전자주식회사 Muit-bit flash memory
JP4079684B2 (en) 2002-05-08 2008-04-23 株式会社日立製作所 Heap memory management method and computer system using the same
US6966006B2 (en) 2002-05-09 2005-11-15 International Business Machines Corporation Adaptive startup policy for accelerating multi-disk array spin-up
US6895464B2 (en) 2002-06-03 2005-05-17 Honeywell International Inc. Flash memory management system and method utilizing multiple block list windows
US6885530B2 (en) 2002-06-11 2005-04-26 Stmicroelectronics, Inc. Power limiting time delay circuit
KR100484147B1 (en) 2002-07-26 2005-04-18 삼성전자주식회사 Flash memory management method
US6978343B1 (en) 2002-08-05 2005-12-20 Netlogic Microsystems, Inc. Error-correcting content addressable memory
US7051155B2 (en) 2002-08-05 2006-05-23 Sun Microsystems, Inc. Method and system for striping data to accommodate integrity metadata
JP4177329B2 (en) 2002-08-29 2008-11-05 株式会社ルネサステクノロジ Semiconductor processing apparatus and IC card
US7120856B2 (en) 2002-09-25 2006-10-10 Leanics Corporation LDPC code and encoder/decoder regarding same
JP2004178782A (en) 2002-10-04 2004-06-24 Sharp Corp Semiconductor memory, control method for the same, and portable electronic apparatus
KR100457812B1 (en) 2002-11-14 2004-11-18 삼성전자주식회사 Flash memory, access apparatus and method using flash memory
US7660998B2 (en) 2002-12-02 2010-02-09 Silverbrook Research Pty Ltd Relatively unique ID in integrated circuit
US20040114265A1 (en) 2002-12-16 2004-06-17 Xerox Corporation User-selectable automatic secure data file erasure of job after job completion
US7155579B1 (en) 2002-12-27 2006-12-26 Unisys Corporation Memory controller having programmable initialization sequence
US20040153902A1 (en) 2003-01-21 2004-08-05 Nexflash Technologies, Inc. Serial flash integrated circuit having error detection and correction
US7296216B2 (en) 2003-01-23 2007-11-13 Broadcom Corporation Stopping and/or reducing oscillations in low density parity check (LDPC) decoding
US7043505B1 (en) 2003-01-28 2006-05-09 Unisys Corporation Method variation for collecting stability data from proprietary systems
JP2004240555A (en) 2003-02-04 2004-08-26 Fujitsu Ltd Battery operation controller, battery operation control method and battery operation control program
US7478096B2 (en) 2003-02-26 2009-01-13 Burnside Acquisition, Llc History preservation in a computer storage system
US7162678B2 (en) 2003-03-14 2007-01-09 Quantum Corporation Extended error correction codes
US7527466B2 (en) 2003-04-03 2009-05-05 Simmons Robert J Building-erection structural member transporter
KR100543447B1 (en) 2003-04-03 2006-01-23 삼성전자주식회사 Flash memory with error correction for page copy
KR100526186B1 (en) 2003-04-04 2005-11-03 삼성전자주식회사 Method and apparatus for managing bad block in flash memory
JP4170988B2 (en) 2003-05-09 2008-10-22 富士通株式会社 Risk prediction / avoidance method, system, program, and recording medium for execution environment
US7877647B2 (en) 2003-05-23 2011-01-25 Hewlett-Packard Development Company, L.P. Correcting a target address in parallel with determining whether the target address was received in error
EP1627331B1 (en) 2003-05-23 2017-09-20 IP Reservoir, LLC Intelligent data storage and processing using fpga devices
US7685254B2 (en) 2003-06-10 2010-03-23 Pandya Ashish A Runtime adaptable search processor
US7076598B2 (en) 2003-09-09 2006-07-11 Solid State System Co., Ltd. Pipeline accessing method to a large block memory
US7100002B2 (en) 2003-09-16 2006-08-29 Denali Software, Inc. Port independent data transaction interface for multi-port devices
US7054968B2 (en) 2003-09-16 2006-05-30 Denali Software, Inc. Method and apparatus for multi-port memory controller
US7523157B2 (en) 2003-09-25 2009-04-21 International Business Machines Corporation Managing a plurality of processors as devices
US7012835B2 (en) 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
US7173852B2 (en) 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
TW200516821A (en) 2003-11-14 2005-05-16 Hon Hai Prec Ind Co Ltd System and method for starting up devices orderly
US7401174B2 (en) 2003-12-16 2008-07-15 Matsushita Electric Industrial Co., Ltd. File system defragmentation and data processing method and apparatus for an information recording medium
US7376887B2 (en) 2003-12-22 2008-05-20 International Business Machines Corporation Method for fast ECC memory testing by software including ECC check byte
US7197652B2 (en) 2003-12-22 2007-03-27 International Business Machines Corporation Method and system for energy management in a simultaneous multi-threaded (SMT) processing system including per-thread device usage monitoring
US20050251617A1 (en) 2004-05-07 2005-11-10 Sinclair Alan W Hybrid non-volatile memory system
US7631148B2 (en) 2004-01-08 2009-12-08 Netapp, Inc. Adaptive file readahead based on multiple factors
JP4357304B2 (en) 2004-01-09 2009-11-04 株式会社バッファロー External storage device
US7328377B1 (en) 2004-01-27 2008-02-05 Altera Corporation Error correction for programmable logic integrated circuits
JP4477365B2 (en) 2004-01-29 2010-06-09 株式会社日立製作所 Storage device having a plurality of interfaces and control method of the storage device
US7389465B2 (en) 2004-01-30 2008-06-17 Micron Technology, Inc. Error detection and correction scheme for a memory device
US7350044B2 (en) 2004-01-30 2008-03-25 Micron Technology, Inc. Data move method and apparatus
US20080147964A1 (en) 2004-02-26 2008-06-19 Chow David Q Using various flash memory cells to build usb data flash cards with multiple partitions and autorun function
US7035159B2 (en) 2004-04-01 2006-04-25 Micron Technology, Inc. Techniques for storing accurate operating current values
US7020017B2 (en) 2004-04-06 2006-03-28 Sandisk Corporation Variable programming of non-volatile memory
EP1870814B1 (en) 2006-06-19 2014-08-13 Texas Instruments France Method and apparatus for secure demand paging for processor devices
US7490283B2 (en) 2004-05-13 2009-02-10 Sandisk Corporation Pipelined data relocation and improved chip architectures
JP2005332471A (en) 2004-05-19 2005-12-02 Hitachi Ltd Disk array device
US20050273560A1 (en) 2004-06-03 2005-12-08 Hulbert Jared E Method and apparatus to avoid incoherency between a cache memory and flash memory
US7334179B2 (en) 2004-06-04 2008-02-19 Broadcom Corporation Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
US7159069B2 (en) 2004-06-23 2007-01-02 Atmel Corporation Simultaneous external read operation during internal programming in a flash memory device
US7126873B2 (en) 2004-06-29 2006-10-24 Super Talent Electronics, Inc. Method and system for expanding flash storage device capacity
US7529898B2 (en) 2004-07-09 2009-05-05 International Business Machines Corporation Method for backing up and restoring data
US8190808B2 (en) 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
DK3422583T3 (en) 2004-08-30 2020-09-28 Google Llc SYSTEM AND METHOD OF PROVIDING NON-VOLATILE MEMORY ADMINISTRATION IN CORDLESS PHONES
FR2875358B1 (en) 2004-09-15 2006-12-15 Eads Telecom Soc Par Actions S INSERTING A SECONDARY FLOW OF BINARY INFORMATION IN A MAIN FLOW OF SYMBOLS OF DIGITAL MODULATION
JP2006099665A (en) 2004-09-30 2006-04-13 Hitachi Global Storage Technologies Netherlands Bv Data storage device, and control method of power save mode of serial interface part thereof
US7760880B2 (en) 2004-10-13 2010-07-20 Viasat, Inc. Decoder architecture system and method
JP4956922B2 (en) 2004-10-27 2012-06-20 ソニー株式会社 Storage device
KR100695891B1 (en) 2004-11-17 2007-03-19 삼성전자주식회사 Apparatus and method for selective lock-out based on operation mode of integrated circuit
US20060136681A1 (en) 2004-12-21 2006-06-22 Sanjeev Jain Method and apparatus to support multiple memory banks with a memory block
US8438459B2 (en) 2004-12-22 2013-05-07 Lg Electronics Inc. Apparatus and method for decoding using channel code
US20060156177A1 (en) 2004-12-29 2006-07-13 Sailesh Kottapalli Method and apparatus for recovering from soft errors in register files
US7657696B2 (en) 2005-02-25 2010-02-02 Lsi Corporation Method to detect NAND-flash parameters by hardware automatically
US7822912B2 (en) 2005-03-14 2010-10-26 Phision Electronics Corp. Flash storage chip and flash array storage system
US7707232B2 (en) 2005-05-13 2010-04-27 Microsoft Corporation Implementation for collecting unmanaged memory
US7765454B2 (en) 2005-05-24 2010-07-27 Sgi International, Inc. Fault tolerant memory system
US7283395B2 (en) 2005-06-24 2007-10-16 Infineon Technologies Flash Gmbh & Co. Kg Memory device and method for operating the memory device
JP2008544721A (en) 2005-06-27 2008-12-04 トムソン ライセンシング Method and apparatus for iterative decoder power reduction
US20070061597A1 (en) 2005-09-14 2007-03-15 Micky Holtzman Secure yet flexible system architecture for secure devices with flash mass storage memory
KR100705220B1 (en) 2005-09-15 2007-04-06 주식회사 하이닉스반도체 Erasing and Programming methods of a flash memory device for increasing program speed of the flash memory device
KR20080054412A (en) 2005-09-27 2008-06-17 엔엑스피 비 브이 Error detection/correction circuit and corresponding method
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
KR100715147B1 (en) 2005-10-06 2007-05-10 삼성전자주식회사 Multi-Chip Semiconductor Memory Device having Internal Power Voltage Generating Circuit with reducing current consumption
US20070083697A1 (en) 2005-10-07 2007-04-12 Microsoft Corporation Flash memory management
US8223553B2 (en) 2005-10-12 2012-07-17 Macronix International Co., Ltd. Systems and methods for programming a memory device
US7743363B2 (en) 2005-10-13 2010-06-22 Microsoft Corporation Extensible meta-data
KR101021465B1 (en) 2005-10-26 2011-03-15 삼성전자주식회사 Apparatus and method for receiving signal in a communication system using a low density parity check code
KR100966043B1 (en) 2005-10-31 2010-06-25 삼성전자주식회사 Apparatus and method for transmitting/receiving signal in a communication system using low density parity check codes
US7500062B2 (en) 2005-11-17 2009-03-03 International Business Machines Corporation Fast path memory read request processing in a multi-level memory architecture
WO2007058617A1 (en) 2005-11-17 2007-05-24 Chee Keng Chang A controller for non-volatile memories, and methods of operating the memory controller
US8813052B2 (en) 2005-12-07 2014-08-19 Microsoft Corporation Cache metadata for implementing bounded transactional memory
US7562283B2 (en) 2005-12-27 2009-07-14 D.S.P. Group Ltd. Systems and methods for error correction using binary coded hexidecimal or hamming decoding
US7546515B2 (en) 2005-12-27 2009-06-09 Sandisk Corporation Method of storing downloadable firmware on bulk media
US7349264B2 (en) 2005-12-28 2008-03-25 Sandisk Corporation Alternate sensing techniques for non-volatile memories
US7716180B2 (en) 2005-12-29 2010-05-11 Amazon Technologies, Inc. Distributed storage system with web services client interface
WO2007080586A2 (en) 2006-01-10 2007-07-19 Saifun Semiconductors Ltd. Rd algorithm improvement for nrom technology
US8020060B2 (en) 2006-01-18 2011-09-13 Sandisk Il Ltd Method of arranging data in a multi-level cell memory device
KR100725410B1 (en) 2006-01-20 2007-06-07 삼성전자주식회사 Apparatus and method for executing garbage collection of non volatile memory according to power state
US20070234143A1 (en) 2006-01-25 2007-10-04 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices
JP4859471B2 (en) 2006-02-02 2012-01-25 株式会社日立製作所 Storage system and storage controller
US7546478B2 (en) 2006-02-10 2009-06-09 International Business Machines Corporation Apparatus and method to provide power to a plurality of data storage devices disposed in a data storage system
US7870326B2 (en) 2006-07-28 2011-01-11 Samsung Electronics Co., Ltd. Multiprocessor system and method thereof
US7590473B2 (en) 2006-02-16 2009-09-15 Intel Corporation Thermal management using an on-die thermal sensor
US7681106B2 (en) 2006-03-29 2010-03-16 Freescale Semiconductor, Inc. Error correction device and methods thereof
JP4863749B2 (en) 2006-03-29 2012-01-25 株式会社日立製作所 Storage device using flash memory, erase number leveling method thereof, and erase number level program
US20070245061A1 (en) 2006-04-13 2007-10-18 Intel Corporation Multiplexing a parallel bus interface and a flash memory interface
US7685494B1 (en) 2006-05-08 2010-03-23 Marvell International, Ltd. Error correction coding for varying signal-to-noise ratio channels
US7639542B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US8000134B2 (en) * 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7707481B2 (en) 2006-05-16 2010-04-27 Pitney Bowes Inc. System and method for efficient uncorrectable error detection in flash memory
US7701764B2 (en) 2006-05-17 2010-04-20 Micron Technology, Inc. Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices
US20070300130A1 (en) 2006-05-17 2007-12-27 Sandisk Corporation Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices
US7606084B2 (en) 2006-06-19 2009-10-20 Sandisk Corporation Programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory
JP4842719B2 (en) 2006-06-28 2011-12-21 株式会社日立製作所 Storage system and data protection method thereof
WO2008003094A2 (en) 2006-06-29 2008-01-03 Digital Fountain, Inc. Efficient representation of symbol-based transformations with application to encoding and decoding of forward error correction codes
US7774684B2 (en) 2006-06-30 2010-08-10 Intel Corporation Reliability, availability, and serviceability in a memory device
US7403438B2 (en) 2006-07-12 2008-07-22 Infineon Technologies Flash Gmbh & Co. Kg Memory array architecture and method for high-speed distribution measurements
JP2008047273A (en) 2006-07-20 2008-02-28 Toshiba Corp Semiconductor storage device and its control method
US7831895B2 (en) 2006-07-25 2010-11-09 Communications Coding Corporation Universal error control coding system for digital communication and data storage systems
TW200813724A (en) 2006-07-28 2008-03-16 Samsung Electronics Co Ltd Multipath accessible semiconductor memory device with host interface between processors
US20080052446A1 (en) 2006-08-28 2008-02-28 Sandisk Il Ltd. Logical super block mapping for NAND flash memory
US7566987B2 (en) 2006-09-14 2009-07-28 Lutron Electronics Co., Inc. Method of powering up a plurality of loads in sequence
KR100843133B1 (en) 2006-09-20 2008-07-02 삼성전자주식회사 Apparatus and method for reorganization of Mapping information in flash memory
TW200816651A (en) 2006-09-25 2008-04-01 Sunplus Technology Co Ltd Decoding method and system of real-time wireless channel estimation
US7886204B2 (en) 2006-09-27 2011-02-08 Sandisk Corporation Methods of cell population distribution assisted read margining
US8171380B2 (en) 2006-10-10 2012-05-01 Marvell World Trade Ltd. Adaptive systems and methods for storing and retrieving data to and from memory cells
CN100596029C (en) 2006-10-20 2010-03-24 北京泰美世纪科技有限公司 Method of constructing check matrix for LDPC code, and encoding and decoding device of using the method
JP2008117195A (en) 2006-11-06 2008-05-22 Hitachi Ltd Semiconductor storage device
TWI307100B (en) 2006-11-07 2009-03-01 Macronix Int Co Ltd Memory and method for reading error checking thereof
US7508703B2 (en) 2006-11-13 2009-03-24 Sandisk Corporation Non-volatile memory with boost structures
US8019940B2 (en) 2006-12-06 2011-09-13 Fusion-Io, Inc. Apparatus, system, and method for a front-end, distributed raid
US8074011B2 (en) 2006-12-06 2011-12-06 Fusion-Io, Inc. Apparatus, system, and method for storage space recovery after reaching a read count limit
KR100808664B1 (en) 2006-12-08 2008-03-07 한국전자통신연구원 Parity check matrix storing method, block ldpc coding method and the apparatus using parity check matrix storing method
WO2008075292A2 (en) 2006-12-18 2008-06-26 Nxp B.V. Power-on temperature sensor/spd detect
KR100881669B1 (en) 2006-12-18 2009-02-06 삼성전자주식회사 Method for detecting of static data area and for wear-leveling and for merging data unit of non-volatile data storage and apparatus thereof
US7620781B2 (en) 2006-12-19 2009-11-17 Intel Corporation Efficient Bloom filter
KR100842680B1 (en) 2007-01-08 2008-07-01 삼성전자주식회사 Ecc controller for use in flash memory device and memory system including the same
US7603490B2 (en) 2007-01-10 2009-10-13 International Business Machines Corporation Barrier and interrupt mechanism for high latency and out of order DMA device
KR100855587B1 (en) 2007-01-17 2008-09-01 삼성전자주식회사 Multi-path accessible semiconductor memory device having mail box regions and method for mail box access control therefore
US7596643B2 (en) 2007-02-07 2009-09-29 Siliconsystems, Inc. Storage subsystem with configurable buffer
US7913022B1 (en) 2007-02-14 2011-03-22 Xilinx, Inc. Port interface modules (PIMs) in a multi-port memory controller (MPMC)
US8369141B2 (en) 2007-03-12 2013-02-05 Apple Inc. Adaptive estimation of memory cell read thresholds
KR100918707B1 (en) 2007-03-12 2009-09-23 삼성전자주식회사 Flash memory-based memory system
JP4897524B2 (en) 2007-03-15 2012-03-14 株式会社日立製作所 Storage system and storage system write performance deterioration prevention method
KR100907218B1 (en) 2007-03-28 2009-07-10 삼성전자주식회사 Apparatus for controlling read level and method using the same
WO2008121553A1 (en) 2007-03-29 2008-10-09 Sandisk Corporation Non-volatile storage with decoding of data using reliability metrics based on multiple reads
WO2008121577A1 (en) 2007-03-31 2008-10-09 Sandisk Corporation Soft bit data transmission for error correction control in non-volatile memory
US8032724B1 (en) 2007-04-04 2011-10-04 Marvell International Ltd. Demand-driven opportunistic garbage collection in memory components
US7996642B1 (en) 2007-04-25 2011-08-09 Marvell International Ltd. Digital locked loop on channel tagged memory requests for memory optimization
EP1988474A1 (en) 2007-05-04 2008-11-05 Axalto SA System and method of managing indexation of flash memory
US8151171B2 (en) 2007-05-07 2012-04-03 Broadcom Corporation Operational parameter adaptable LDPC (low density parity check) decoder
US8073648B2 (en) 2007-05-14 2011-12-06 Sandisk Il Ltd. Measuring threshold voltage distribution in memory using an aggregate characteristic
US7930547B2 (en) 2007-06-15 2011-04-19 Alcatel-Lucent Usa Inc. High accuracy bloom filter using partitioned hashing
KR100891005B1 (en) 2007-06-28 2009-03-31 삼성전자주식회사 Flash memory device compensating it's read voltage margin and method for adjusting read voltage thereof
JP2009020986A (en) 2007-07-15 2009-01-29 Hitachi Global Storage Technologies Netherlands Bv Disk drive apparatus, and method for storing table for managing data in nonvolatile semiconductor memory in disk drive apparatus
US8024525B2 (en) 2007-07-25 2011-09-20 Digi-Data Corporation Storage control unit with memory cache protection via recorded log
US8724789B2 (en) 2007-08-06 2014-05-13 Yellow Pages Systems and methods to connect people for real time communications via directory assistance
JP4564520B2 (en) 2007-08-31 2010-10-20 株式会社東芝 Semiconductor memory device and control method thereof
US8095851B2 (en) 2007-09-06 2012-01-10 Siliconsystems, Inc. Storage subsystem capable of adjusting ECC settings based on monitored conditions
JP4404125B2 (en) 2007-09-12 2010-01-27 株式会社デンソー Electronic control device and signal monitoring circuit
US8139412B2 (en) 2007-10-31 2012-03-20 Agere Systems Inc. Systematic error correction for multi-level flash memory
US7894264B2 (en) 2007-11-07 2011-02-22 Micron Technology, Inc. Controlling a memory device responsive to degradation
US7945825B2 (en) 2007-11-25 2011-05-17 Spansion Isreal, Ltd Recovery while programming non-volatile memory (NVM)
US8429492B2 (en) 2007-11-30 2013-04-23 Marvell World Trade Ltd. Error correcting code predication system and method
WO2009072104A2 (en) 2007-12-05 2009-06-11 Densbits Technologies Ltd. Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith
US8751755B2 (en) 2007-12-27 2014-06-10 Sandisk Enterprise Ip Llc Mass storage controller volatile memory containing metadata related to flash memory storage
KR101077339B1 (en) 2007-12-28 2011-10-26 가부시끼가이샤 도시바 Semiconductor storage device
US20090172335A1 (en) 2007-12-31 2009-07-02 Anand Krishnamurthi Kulkarni Flash devices with raid
US8159874B2 (en) 2008-01-22 2012-04-17 Micron Technology, Inc. Cell operation monitoring
US8271515B2 (en) 2008-01-29 2012-09-18 Cadence Design Systems, Inc. System and method for providing copyback data integrity in a non-volatile memory system
JP4617405B2 (en) 2008-02-05 2011-01-26 富士通株式会社 Electronic device for detecting defective memory, defective memory detecting method, and program therefor
US20090204823A1 (en) 2008-02-07 2009-08-13 Analog Devices, Inc. Method and apparatus for controlling system access during protected modes of operation
JP4672743B2 (en) 2008-03-01 2011-04-20 株式会社東芝 Error correction apparatus and error correction method
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
JP2009266349A (en) 2008-04-28 2009-11-12 Toshiba Corp Nonvolatile semiconductor memory device
US8185706B2 (en) 2008-04-30 2012-05-22 Apple Inc. Copyback optimization for memory system
KR101412974B1 (en) 2008-05-28 2014-06-30 삼성전자주식회사 Memory device and memory programming method
KR101412690B1 (en) 2008-05-28 2014-06-27 삼성전자주식회사 Memory device and memory programming method
JP5072723B2 (en) 2008-06-11 2012-11-14 株式会社東芝 Nonvolatile semiconductor memory device
US8959280B2 (en) 2008-06-18 2015-02-17 Super Talent Technology, Corp. Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear
US8627169B2 (en) 2008-06-20 2014-01-07 Cadence Design Systems, Inc. Method and apparatus for dynamically configurable multi level error correction
KR101413137B1 (en) 2008-07-04 2014-07-01 삼성전자주식회사 Memory device and memory programming method
US8037380B2 (en) 2008-07-08 2011-10-11 International Business Machines Corporation Verifying data integrity of a non-volatile memory system during data caching process
US8325554B2 (en) 2008-07-10 2012-12-04 Sanmina-Sci Corporation Battery-less cache memory module with integrated backup
KR101436506B1 (en) 2008-07-23 2014-09-02 삼성전자주식회사 Memory device and method of programming data in memory device
US8130552B2 (en) 2008-09-11 2012-03-06 Sandisk Technologies Inc. Multi-pass programming for memory with reduced data storage requirement
US8429514B1 (en) 2008-09-24 2013-04-23 Network Appliance, Inc. Dynamic load balancing of distributed parity in a RAID array
KR101484556B1 (en) 2008-10-28 2015-01-20 삼성전자주식회사 Read compensation circuit
US8023334B2 (en) 2008-10-31 2011-09-20 Micron Technology, Inc. Program window adjust for memory cell signal line delay
US8214599B2 (en) 2008-11-04 2012-07-03 Gridiron Systems, Inc. Storage device prefetch system using directed graph clusters
US9063874B2 (en) 2008-11-10 2015-06-23 SanDisk Technologies, Inc. Apparatus, system, and method for wear management
KR101516577B1 (en) 2008-11-10 2015-05-06 삼성전자주식회사 Nonvolatile semi-conductor memory device and method for calculating read voltage non-volatile semiconductor memory device
KR20100058166A (en) 2008-11-24 2010-06-03 삼성전자주식회사 Nonvolatile memory device and memory system thereof
KR101555022B1 (en) 2008-12-02 2015-09-23 삼성전자주식회사 Memory device memory system having ita and mapping information recovering method thereof
US8209466B2 (en) 2008-12-16 2012-06-26 Intel Corporation Methods and systems to allocate addresses in a high-endurance/low-endurance hybrid flash memory
US9128699B2 (en) 2008-12-22 2015-09-08 Intel Corporation Method and system for queuing transfers of multiple non-contiguous address ranges with a single command
KR101535225B1 (en) 2009-01-06 2015-07-09 삼성전자주식회사 Decoding method and memory system device for using the method
KR100996009B1 (en) * 2009-02-02 2010-11-22 주식회사 하이닉스반도체 Non volatile memory device and method of operating the same
US8645749B2 (en) 2009-02-04 2014-02-04 Micron Technology, Inc. Systems and methods for storing and recovering controller data in non-volatile memory devices
KR20100090439A (en) 2009-02-06 2010-08-16 주식회사 하이닉스반도체 Reading method of nonvolatile memory device, and nonvolatile memory device implementing the same
US7830732B2 (en) 2009-02-11 2010-11-09 Stec, Inc. Staged-backup flash backed dram module
KR20100093885A (en) 2009-02-17 2010-08-26 삼성전자주식회사 Nonvolatile memory device, operating method thereof and memory system including the same
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8042011B2 (en) 2009-04-28 2011-10-18 Synopsys, Inc. Runtime programmable BIST for testing a multi-port memory device
KR101575248B1 (en) 2009-04-30 2015-12-07 삼성전자주식회사 Memory controller and memory system including the same
US20100281207A1 (en) 2009-04-30 2010-11-04 Miller Steven C Flash-based data archive storage system
US8463820B2 (en) 2009-05-26 2013-06-11 Intel Corporation System and method for memory bandwidth friendly sorting on multi-core architectures
US8180763B2 (en) 2009-05-29 2012-05-15 Microsoft Corporation Cache-friendly B-tree accelerator
US8885434B2 (en) 2009-06-17 2014-11-11 Stmicroelectronics International N.V. Retention of data during stand-by mode
US8479032B2 (en) 2009-06-26 2013-07-02 Seagate Technology Llc Systems, methods and devices for regulation or isolation of backup power in memory devices
US8627117B2 (en) 2009-06-26 2014-01-07 Seagate Technology Llc Device with power control feature involving backup power reservoir circuit
US8412985B1 (en) 2009-06-30 2013-04-02 Micron Technology, Inc. Hardwired remapped memory
US8880835B2 (en) 2009-07-07 2014-11-04 International Business Machines Corporation Adjusting location of tiered storage residence based on usage patterns
US8516219B2 (en) 2009-07-24 2013-08-20 Apple Inc. Index cache tree
US7941696B2 (en) 2009-08-11 2011-05-10 Texas Memory Systems, Inc. Flash-based memory system with static or variable length page stripes including data protection information and auxiliary protection stripes
US7818525B1 (en) 2009-08-12 2010-10-19 Texas Memory Systems, Inc. Efficient reduction of read disturb errors in NAND FLASH memory
WO2011022114A1 (en) 2009-08-20 2011-02-24 Rambus Inc. Atomic memory device
US8464106B2 (en) 2009-08-24 2013-06-11 Ocz Technology Group, Inc. Computer system with backup function and method therefor
US8289801B2 (en) 2009-09-09 2012-10-16 Fusion-Io, Inc. Apparatus, system, and method for power reduction management in a storage device
US8478725B2 (en) 2009-09-14 2013-07-02 Vmware, Inc. Method and system for performing live migration of persistent data of a virtual machine
WO2011036228A1 (en) 2009-09-23 2011-03-31 Conor Maurice Ryan A flash memory device and control method
US8479061B2 (en) 2009-09-24 2013-07-02 AGIGA Tech Solid state memory cartridge with wear indication
US8171257B2 (en) 2009-09-25 2012-05-01 International Business Machines Corporation Determining an end of valid log in a log of write records using a next pointer and a far ahead pointer
WO2011036727A1 (en) 2009-09-25 2011-03-31 富士通株式会社 Memory system and memory system control method
JP5197544B2 (en) 2009-10-05 2013-05-15 株式会社東芝 Memory system
US8312349B2 (en) 2009-10-27 2012-11-13 Micron Technology, Inc. Error detection/correction based memory management
US8423866B2 (en) 2009-10-28 2013-04-16 SanDisk Technologies, Inc. Non-volatile memory and method with post-write read and adaptive re-write to manage errors
CN101699406B (en) 2009-11-12 2011-12-14 威盛电子股份有限公司 Data storage system and method
US8335123B2 (en) 2009-11-20 2012-12-18 Sandisk Technologies Inc. Power management of memory systems
US8130553B2 (en) 2009-12-02 2012-03-06 Seagate Technology Llc Systems and methods for low wear operation of solid state memory
FR2953666B1 (en) 2009-12-09 2012-07-13 Commissariat Energie Atomique LDPC CODING METHOD WITH INCREMENTAL REDUNDANCY
US8250380B2 (en) 2009-12-17 2012-08-21 Hitachi Global Storage Technologies Netherlands B.V. Implementing secure erase for solid state drives
TWI399645B (en) * 2010-01-15 2013-06-21 Silicon Motion Inc Memory device and method for managing data read from a memory
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
US8380915B2 (en) 2010-01-27 2013-02-19 Fusion-Io, Inc. Apparatus, system, and method for managing solid-state storage media
JP5788183B2 (en) 2010-02-17 2015-09-30 三星電子株式会社Samsung Electronics Co.,Ltd. Nonvolatile memory device, method of operating the same, and memory system including the same
US8213255B2 (en) 2010-02-19 2012-07-03 Sandisk Technologies Inc. Non-volatile storage with temperature compensation based on neighbor state information
US8355280B2 (en) 2010-03-09 2013-01-15 Samsung Electronics Co., Ltd. Data storage system having multi-bit memory device and operating method thereof
US8458417B2 (en) 2010-03-10 2013-06-04 Seagate Technology Llc Garbage collection in a storage device
US8365041B2 (en) 2010-03-17 2013-01-29 Sandisk Enterprise Ip Llc MLC self-raid flash data protection scheme
US8164967B2 (en) 2010-03-24 2012-04-24 Apple Inc. Systems and methods for refreshing non-volatile memory
US9183134B2 (en) 2010-04-22 2015-11-10 Seagate Technology Llc Data segregation in a storage device
JP2011233114A (en) 2010-04-30 2011-11-17 Toshiba Corp Memory system
US8321481B2 (en) 2010-05-13 2012-11-27 Assa Abloy Ab Method for incremental anti-tear garbage collection
US20110283119A1 (en) 2010-05-13 2011-11-17 GCCA Inc. System and Method for Providing Energy Efficient Cloud Computing
EP2577830A2 (en) 2010-06-01 2013-04-10 Koninklijke Philips Electronics N.V. System and method for sequential application of power to electrical loads
WO2011153478A2 (en) 2010-06-04 2011-12-08 Flashsoft Corporation Cache management and acceleration of storage media
WO2012001917A1 (en) 2010-06-29 2012-01-05 パナソニック株式会社 Nonvolatile storage system, power supply circuit for memory system, flash memory, flash memory controller, and nonvolatile semiconductor storage device
US20120011393A1 (en) 2010-07-06 2012-01-12 Roberts Richard B Bios recovery
US8737141B2 (en) 2010-07-07 2014-05-27 Stec, Inc. Apparatus and method for determining an operating condition of a memory cell based on cycle information
US8737136B2 (en) 2010-07-09 2014-05-27 Stec, Inc. Apparatus and method for determining a read level of a memory cell based on cycle information
KR101131560B1 (en) 2010-07-15 2012-04-04 주식회사 하이닉스반도체 Non-Volitile Memory Device For Performing Wear-Leveling and Method Thereof
US8503238B1 (en) 2010-07-21 2013-08-06 Sk Hynix Memory Solutions Inc. Error recovery for flash memory
US20120023144A1 (en) 2010-07-21 2012-01-26 Seagate Technology Llc Managing Wear in Flash Memory
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
CN102385902A (en) 2010-09-01 2012-03-21 建兴电子科技股份有限公司 Solid state storage device and data control method thereof
JP2012058860A (en) 2010-09-06 2012-03-22 Toshiba Corp Memory system
US8417878B2 (en) 2010-09-20 2013-04-09 Seagate Technology Llc Selection of units for garbage collection in flash memory
WO2012051600A2 (en) 2010-10-15 2012-04-19 Kyquang Son File system-aware solid-state storage management system
US20120275466A1 (en) 2010-10-21 2012-11-01 Texas Instruments Incorporated System and method for classifying packets
WO2012058328A1 (en) 2010-10-27 2012-05-03 Sandforce, Inc. Adaptive ecc techniques for flash memory based data storage
US9063878B2 (en) 2010-11-03 2015-06-23 Densbits Technologies Ltd. Method, system and computer readable medium for copy back
US8909957B2 (en) 2010-11-04 2014-12-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Dynamic voltage adjustment to computer system memory
KR101774496B1 (en) 2010-12-08 2017-09-05 삼성전자주식회사 Non-volatile memory device, devices having the same, method of operating the same
KR20120064462A (en) 2010-12-09 2012-06-19 삼성전자주식회사 Memory controller and method for correcting error the same, and memory system having the same
US8615681B2 (en) 2010-12-14 2013-12-24 Western Digital Technologies, Inc. System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss
US9038066B2 (en) 2010-12-22 2015-05-19 Vmware, Inc. In-place snapshots of a virtual disk configured with sparse extent
TWI446345B (en) 2010-12-31 2014-07-21 Silicon Motion Inc Method for performing block management, and associated memory device and controller thereof
JP2012151676A (en) 2011-01-19 2012-08-09 Jvc Kenwood Corp Decoding apparatus and decoding method
US8364888B2 (en) 2011-02-03 2013-01-29 Stec, Inc. Erase-suspend system and method
WO2012109679A2 (en) 2011-02-11 2012-08-16 Fusion-Io, Inc. Apparatus, system, and method for application direct virtual memory management
US8966319B2 (en) 2011-02-22 2015-02-24 Apple Inc. Obtaining debug information from a flash memory device
US9047955B2 (en) 2011-03-30 2015-06-02 Stec, Inc. Adjusting operating parameters for memory cells based on wordline address and cycle information
US8874515B2 (en) 2011-04-11 2014-10-28 Sandisk Enterprise Ip Llc Low level object version tracking using non-volatile memory write generations
US8909888B2 (en) 2011-04-29 2014-12-09 Seagate Technology Llc Secure erasure of data from a non-volatile memory
US8713380B2 (en) 2011-05-03 2014-04-29 SanDisk Technologies, Inc. Non-volatile memory and method having efficient on-chip block-copying with controlled error rate
US8745318B2 (en) 2011-06-28 2014-06-03 Seagate Technology Llc Parameter tracking for memory devices
US8898373B1 (en) 2011-06-29 2014-11-25 Western Digital Technologies, Inc. System and method for improving wear-leveling performance in solid-state memory
US9378138B2 (en) 2011-06-29 2016-06-28 International Business Machines Corporation Conservative garbage collection and access protection
US8645773B2 (en) 2011-06-30 2014-02-04 Seagate Technology Llc Estimating temporal degradation of non-volatile solid-state memory
US20130024735A1 (en) 2011-07-19 2013-01-24 Ocz Technology Group Inc. Solid-state memory-based storage method and device with low error rate
US8566667B2 (en) 2011-07-29 2013-10-22 Stec, Inc. Low density parity check code decoding system and method
US8692561B2 (en) 2011-08-11 2014-04-08 International Business Machines Corporation Implementing chip to chip calibration within a TSV stack
US20130047045A1 (en) 2011-08-19 2013-02-21 Stec, Inc. Error indicator from ecc decoder
US9047210B2 (en) 2011-09-15 2015-06-02 Sandisk Technologies Inc. Data storage device and method to correct bit values using multiple read voltages
WO2013048485A1 (en) 2011-09-30 2013-04-04 Intel Corporation Autonomous initialization of non-volatile random access memory in a computer system
US8516019B2 (en) 2011-10-03 2013-08-20 Oracle America, Inc. Time-based object aging for generational garbage collectors
US8825721B2 (en) 2011-10-03 2014-09-02 Oracle International Corporation Time-based object aging for generational garbage collectors
CN103392207B (en) 2011-10-05 2017-08-04 希捷科技有限公司 Itself log recording and level uniformity of non-volatile memories
US8711619B2 (en) 2011-10-18 2014-04-29 Seagate Technology Llc Categorizing bit errors of solid-state, non-volatile memory
US10359949B2 (en) 2011-10-31 2019-07-23 Apple Inc. Systems and methods for obtaining and using nonvolatile memory health information
US8683297B2 (en) 2011-11-02 2014-03-25 Sandisk Technologies Inc. Systems and methods of generating a replacement default read threshold
US20140359381A1 (en) 2011-11-02 2014-12-04 The University Of Tokyo Memory controller and data storage device
US9053809B2 (en) 2011-11-09 2015-06-09 Apple Inc. Data protection from write failures in nonvolatile memory
US8456919B1 (en) 2011-11-10 2013-06-04 Sandisk Technologies Inc. Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder
US8954822B2 (en) * 2011-11-18 2015-02-10 Sandisk Enterprise Ip Llc Data encoder and decoder using memory-specific parity-check matrix
US8687421B2 (en) 2011-11-21 2014-04-01 Sandisk Technologies Inc. Scrub techniques for use with dynamic read
US8830746B2 (en) 2011-12-28 2014-09-09 Apple Inc. Optimized threshold search in analog memory cells using separator pages of the same type as read pages
JP2013142947A (en) 2012-01-10 2013-07-22 Sony Corp Storage control device, storage device, and control method for storage control device
US9767032B2 (en) 2012-01-12 2017-09-19 Sandisk Technologies Llc Systems and methods for cache endurance
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
WO2013112332A1 (en) 2012-01-24 2013-08-01 Apple Inc. Enhanced programming and erasure schemes for analog memory cells
US9208871B2 (en) 2012-01-30 2015-12-08 HGST Netherlands B.V. Implementing enhanced data read for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding
US8964482B2 (en) 2012-01-30 2015-02-24 Freescale Semiconductor, Inc. Dynamic healing of non-volatile memory cells
US8832050B2 (en) 2012-03-09 2014-09-09 Hewlett-Packard Development Company, L.P. Validation of distributed balanced trees
US8817569B2 (en) 2012-03-19 2014-08-26 Sandisk Technologies Inc. Immunity against temporary and short power drops in non-volatile memory
US20130290611A1 (en) 2012-03-23 2013-10-31 Violin Memory Inc. Power management in a flash memory
US9311501B2 (en) 2012-03-26 2016-04-12 International Business Machines Corporation Using different secure erase algorithms to erase chunks from a file associated with different security levels
US8923066B1 (en) 2012-04-09 2014-12-30 Sk Hynix Memory Solutions Inc. Storage of read thresholds for NAND flash storage using linear approximation
US8990477B2 (en) 2012-04-19 2015-03-24 Sandisk Technologies Inc. System and method for limiting fragmentation
US20130297613A1 (en) 2012-05-04 2013-11-07 Monmouth University Indexing based on key ranges
US20130343131A1 (en) 2012-06-26 2013-12-26 Lsi Corporation Fast tracking for flash channels
US8634267B2 (en) 2012-05-14 2014-01-21 Sandisk Technologies Inc. Flash memory chip power management for data reliability and methods thereof
US20130346672A1 (en) 2012-06-22 2013-12-26 Microsoft Corporation Multi-Tiered Cache with Storage Medium Awareness
KR101997079B1 (en) 2012-07-26 2019-07-08 삼성전자주식회사 Storage devie comprising variable resistance memory and operation method thereof
KR20140028481A (en) 2012-08-29 2014-03-10 에스케이하이닉스 주식회사 Semiconductor memory device capable of measuring write current and method for measuring write current
US9329986B2 (en) 2012-09-10 2016-05-03 Sandisk Technologies Inc. Peak current management in multi-die non-volatile memory devices
US8938656B2 (en) 2012-09-14 2015-01-20 Sandisk Technologies Inc. Data storage device with intermediate ECC stage
US9128690B2 (en) 2012-09-24 2015-09-08 Texas Instruments Incorporated Bus pin reduction and power management
US9104328B2 (en) 2012-10-31 2015-08-11 Hitachi, Ltd. Storage apparatus and method for controlling storage apparatus
US8634248B1 (en) 2012-11-09 2014-01-21 Sandisk Technologies Inc. On-device data analytics using NAND flash based intelligent memory
US8817541B2 (en) 2012-11-09 2014-08-26 Sandisk Technologies Inc. Data search using bloom filters and NAND based content addressable memory
US8930778B2 (en) 2012-11-15 2015-01-06 Seagate Technology Llc Read disturb effect determination
US8949544B2 (en) 2012-11-19 2015-02-03 Advanced Micro Devices, Inc. Bypassing a cache when handling memory requests
US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
US8869008B2 (en) 2013-01-17 2014-10-21 Apple Inc. Adaptation of analog memory cell read thresholds using partial ECC syndromes
KR20140100330A (en) 2013-02-06 2014-08-14 삼성전자주식회사 Memory system and operating method thereof
US9383795B2 (en) 2013-03-10 2016-07-05 Seagate Technololgy Llc Storage device power failure infrastructure
US9042181B2 (en) 2013-03-15 2015-05-26 SanDisk Technologies, Inc. Periodic erase operation for a non-volatile medium
US10546648B2 (en) 2013-04-12 2020-01-28 Sandisk Technologies Llc Storage control system with data management mechanism and method of operation thereof
US9378830B2 (en) 2013-07-16 2016-06-28 Seagate Technology Llc Partial reprogramming of solid-state non-volatile memory cells
US9043517B1 (en) 2013-07-25 2015-05-26 Sandisk Enterprise Ip Llc Multipass programming in buffers implemented in non-volatile data storage systems
US9531038B2 (en) 2013-07-31 2016-12-27 Dell Products, Lp System and method of cell block voltage analytics to improve balancing effectiveness and identify self-discharge rate
US9250676B2 (en) 2013-11-29 2016-02-02 Sandisk Enterprise Ip Llc Power failure architecture and verification
US9235245B2 (en) 2013-12-04 2016-01-12 Sandisk Enterprise Ip Llc Startup performance and power isolation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070201274A1 (en) * 2000-01-06 2007-08-30 Super Talent Electronics Inc. Cell-Downgrading and Reference-Voltage Adjustment for a Multi-Bit-Cell Flash Memory
US20070091677A1 (en) * 2005-10-25 2007-04-26 M-Systems Flash Disk Pioneers Ltd. Method for recovering from errors in flash memory
US20080056005A1 (en) * 2006-08-30 2008-03-06 Micron Technology, Inc. Non-volatile memory cell read failure reduction
US20090292972A1 (en) * 2008-05-23 2009-11-26 Samsung Electronics Co., Ltd. Error correction apparatus, method thereof and memory device comprising the apparatus
WO2011024015A1 (en) * 2009-08-25 2011-03-03 Sandisk Il Ltd. Restoring data into a flash storage device
US20110051513A1 (en) * 2009-08-25 2011-03-03 Micron Technology, Inc. Methods, devices, and systems for dealing with threshold voltage change in memory devices

Also Published As

Publication number Publication date
KR20160009527A (en) 2016-01-26
CN105264496B (en) 2018-06-22
US9367246B2 (en) 2016-06-14
KR101982381B1 (en) 2019-05-27
US20140281044A1 (en) 2014-09-18
CN105264496A (en) 2016-01-20

Similar Documents

Publication Publication Date Title
US20200042223A1 (en) System and method for facilitating a high-density storage device with improved performance and endurance
KR102149668B1 (en) Data decoding method of Non-volatile memory device
US9324420B2 (en) Method of estimating deterioration state of memory device and related method of wear leveling
US9519577B2 (en) Method and system for migrating data between flash memory devices
US9454420B1 (en) Method and system of reading threshold voltage equalization
TWI612525B (en) Decoding method, memory storage device and memory control circuit unit
US9244763B1 (en) System and method for updating a reading threshold voltage based on symbol transition information
US9092350B1 (en) Detection and handling of unbalanced errors in interleaved codewords
US9870830B1 (en) Optimal multilevel sensing for reading data from a storage medium
US9384126B1 (en) Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems
US9768808B2 (en) Method for modifying device-specific variable error correction settings
CN107622783B (en) Decoding method, memory storage device and memory control circuit unit
US9478298B2 (en) Memory system and method of reading data thereof
US10102066B2 (en) Data processing device and operating method thereof
US20160299812A1 (en) Device-Specific Variable Error Correction
US20160299844A1 (en) Mapping Logical Groups of Data to Physical Locations In Memory
US20140136925A1 (en) Method of operating a data storage device
US9105359B2 (en) Nonvolatile memory device and error correction methods thereof
US11373709B2 (en) Memory system for performing a read operation and an operating method thereof
US11762734B2 (en) Apparatus and method for handling a data error in a memory system
US11119697B2 (en) Read voltage management based on write-to-read time difference
US9009576B1 (en) Adaptive LLR based on syndrome weight
CN117437957A (en) Memory system, memory device, and method of operating memory device
US9367246B2 (en) Performance optimization of data transfer for soft information generation
KR20230056901A (en) Apparatus and method for programming data in a memory device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201480015991.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14718291

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20157024578

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14718291

Country of ref document: EP

Kind code of ref document: A1