WO2014193592A2

WO2014193592A2 - High performance system topology for nand memory systems

Info

Publication number: WO2014193592A2
Application number: PCT/US2014/036327
Authority: WO
Inventors: Eugene Jinglun Tam
Original assignee: Sandisk Technologies Inc.
Priority date: 2013-05-29
Filing date: 2014-05-01
Publication date: 2014-12-04
Also published as: CN105122227A; CN105122227B; WO2014193592A3

Abstract

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.

Description

HIGH PERFORMANCE SYSTEM TOPOLOGY FOR NAND MEMORY

SYSTEMS

FIELD OF THE INVENTION

[0001] This invention pertains generally to the field of non- volatile memory and, more particularly, to the topology of the memory chips within such systems.

BACKGROUND

[0002] Non-volatile memory systems, such as those formed from NAND flash memory chips, typically include one or more controller chips connected to multiple memory chips. In some cases, such as in solid state drives (SSDs), the number of memory chips can be quite large. For example, with a NAND density of 128Gb, or 16GB, a 8TB SSD drive with 100% over-provision (redundancy) would have 1024 NAND chips. If the system has 16 input/output (IO) channels, each channel has 64 NAND chips. The capacitive pin loading load of NAND chips impose limitations on system clock operation frequency to ensure signal integrity as the drivers may not be able to handle the cumulative load. Because of this, it is a challenge to push data transfer rates to higher frequencies.

SUMMARY OF THE INVENTION

[0003] According to a first set of general aspects, a non-volatile memory system includes a memory section having a plurality of non-volatile memory circuits and a bus structure. In the memory section, each of the memory circuits includes an array of non-volatile memory cells and a latch circuit, where the latch circuit is connectable to a bus input to receive data and commands therefrom and to a bus output to provide data and responses. In response to commands received on bus input the memory circuit can operate in a plurality of modes including: a pass-through mode, where the memory array is inactive and commands and data are passed by the latch circuit from the bus input to the bus output; and an active mode, in which the memory array is active and data can be transferred between the memory array and the bus input or bus output by the latch circuit. The bus structure connects the bus inputs and bus outputs of the non- volatile memory circuits for the transfer of data and commands. The bus structure includes an input bus for the memory section connected to the bus input of a first of the memory circuits, an output bus for the memory section connected to the bus output of a second of the memory circuit, and first and second intermediate busses. The first intermediate bus connects the bus output of the first memory circuit to the bus inputs of a first set of multiple other ones of the memory circuits, the first set not including the second memory circuit. The second intermediate bus connects the bus input of the second memory circuit to the bus outputs of a second set of multiple other ones of the memory circuits, the second set not including the first memory circuit.

[0004] Further aspects relate to a non-volatile memory system with a memory section having multiple non- volatile memory circuits. Each of the memory circuits includes an array of non-volatile memory cells and a latch circuit, where the latch circuit is connectable to a first input-output port to receive data and commands and provide data therefrom and to a second input-output port to provide data and commands and receive data therefrom. In response to commands received on the first input-output port the memory circuit can operate in a plurality of modes including: pass-through modes, wherein the memory array is inactive and commands and data are passed by the latch circuit from the first input-output port to the second input-output port or from the second input-output port to the first input output port; and active modes, in which the memory array is active and data can be transferred between the memory array and the first input-output port by the latch circuit. The memory section also has a bus structure connecting the first input-output ports and second input-output ports of the non-volatile memory circuits for the transfer of data and commands. The bus structure includes an initial bus segment for the memory section connected to the first input-output port of a first of the memory circuits and a first intermediate bus segment connecting the second input-output port of the first memory circuit to the first input- output ports of a first set of multiple other ones of the memory circuits.

[0005] Other aspects relate to a non-volatile memory integrated circuit having a plurality of external contact pads, primary circuitry portion, and a switching circuit. The external contact pads include a first set of a plurality of N external contact pads and a second set of N external contact pads. The primary circuitry portion includes a non-volatile memory array and associated peripheral circuitry and has, when operating in a first mode, N input lines and N output lines. The switching circuit is connected to the first and second sets of external contact pads connected to the input and output lines. The switching circuit can selectively attach the first and second sets of external contact pads to the input and output lines in either a first configuration, where the N input lines are attached to the first set of external contact pads and the N output lines are attached to the second set of external contact pads, or in a second configuration, where the N input lines are attached to the second set of external contact pads and the N output lines are attached to the first set of external contact pads.

[0006] Additional aspect concern a non-volatile memory package having multiple external bonding pads formed thereupon, the external bonding pads including a plurality of external input pads and a plurality of external output pads. The package contains multiple non-volatile memory chips each having a first set and a second set of N contact pins where each of the memory chips can be individually configured to operate in either a first configuration, where the first set of pins are input pins and the second set of pins are output pins, and a second configuration, where the first set of pins are output pins and the second set of pins are input pins. The memory chips include a first memory chip connected with the input pins thereof connected to the external input pads, a second memory chip connected with the output pins thereof connected to the external output pads, and one or more additional memory chips, where, aside from the input pins of the first memory chip and the output pins of the second memory chip, the first, second and additional memory chips are connected so that the output pins of each memory chip are connected to the input pins of one or more other memory chips and the input pins of each memory chip are connected to the output pins of one or more other memory chips. The memory chips are stacked with chips configured according to the first configuration interleaved with chips configured according to the second configuration.

[0007] Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, whose description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an example of a solid state drive having multiple channels, each with a large number of memory chips attached.

[0009] Figure 2 is a schematic illustration of a NAND memory chip.

[0010] Figure 3 schematically illustrates the inclusion of the alternate interface into the memory chip.

[0011] Figures 4-6 illustrate different modes of operation for the memory chip of Figure 3.

[0012] Figure 7 illustrates an exemplary embodiment for a topology of a set of memory chips arranged into a tree type of structure. [0013] Figure 8 shows a fuller development of the topology of the memory circuits within the memory system.

[0014] Figures 9 and 10 respectively show the flow of data in a write and a read operation for the elements of Figure 8.

[0015] Figure 11 shows the memory section of Figures 8 arranged into a single package.

[0016] Figure 12 illustrates how the packages of Figure 11 can be arranged into a tree structure.

[0017] Figure 13 shows another package embodiment, with 5 tiers and a fan out of 2, resulting in a 10 die package. [0018] Figure 14 illustrates the 10 die packages of Figure 13 arranged into a 5 tiers with a fan out of two, for a total of 100 dies. [0019] Figures 15A-C illustrate the connections between the input and output pads of the chips in a package from different views.

[0020] Figures 16A-C illustrate the pad connections in more detail for the multiple pads of a device. [0021] Figure 17 is a simplified box diagram to illustrate an example of how the swapping of input and output pads can be implemented.

[0022] Figures 18A and 18B show exemplary sets of pad assignments.

[0023] Figure 19 looks at the swapping mechanism for a given pad in more detail.

[0024] Figures 20A-C correspond to Figures 15A-C, but for an 11 -chip package with both the input and output pads placed together on the package board.

[0025] Figure 21 illustrates a corresponding topology of the chips for an 11 -chip package.

[0026] Figure 22 illustrates an embodiment of a memory system of four 11 -die packages connected to the same port [0027] Figures 23 A and 23B show two exemplary embodiments of circuits for data propagation with re-synchronization.

[0028] Figure 24 and 25 illustrates a pair of additional memory chip modes that can used in alternate embodiments.

[0029] Figure 26 shows an example of a topology using the modes of Figures 24 and 25.

[0030] Figure 27 illustrates the operation of Figure 26.

DETAILED DESCRIPTION

[0031] As discussed in the Background, non-volatile memory systems having large numbers of memory chips, such as a NAND based solid state drive (SSD) can suffer from large amount of capacitive loading on pins of the memory chips, limiting transfer rates. The following addresses this problem by introducing a topology for the memory chips that can significantly reduce the capacitive loading, allowing for much higher 10 data transfer rates.

[0032] Figure 1 can be used to consider the problem further. An SSD system 10 includes a controller 1 that has a number (16 in this example) of IO channels, each connected by a bus structure (such as shown IOC-1 3) to a number of memory chips, such as the NAND chip 5. Here, each channel has 64 memory chips for a total of 1024 chips, so that with a NAND density of 128Gb, or 16GB, 100% over-provision, this results in a 8TB SSD drive. Figure 2 is a schematic illustration of a NAND memory chip 5 as attached to the bus structure 3. Although the present discussion is given in the context of NAND type flash memory chips and as SSD drive, as the issue being dealt with is the capacitive loading on the bus structure, the techniques are not specific to this example. In particular, what is here referred to as the conventional circuitry portion 7 of the memory chip can be any sort of memory technology. To provide a concrete example for purposes of discussion, though, the following will be based on the NAND memory SSD drive example. More detail on NAND memory devices can be found in US patent and publication numbers 20080158969; 5,570,315; 5,903,495; and 6,046,935, for example. More detail on SSD drives is given in US patent publication number US20090.172257, for example.

[0033] In a first set of aspects, the memory chip includes a new alternate or additional interface relative to the chip's existing interface. This interface can be controlled by an internal ROM fuse, for example. This new interface can also help to the overloading of pins with features that are found on convention interfaces. This additional interface is illustrated with respect to Figure 3.

[0034] Figure 3 schematically illustrates the inclusion of the alternate interface. The memory chip 15 again includes the "conventional" circuits 17 that would be found on a memory circuit, but now also includes as part of the additional interface a D flip- flop (DFF) 19 for receiving data and for receiving and buffering control signals. The bus connections to the chip 15 now include an input bus 13 and an output bus 21. (Figure 3 shows the input bus 13 and output bus 21 on opposite sides of the chip for illustrative purposes, but in practice the corresponding pins can be variously located around the chip.) In the exemplary embodiment, for versatility the memory chip can be used with the standard interface, as in Figure 2, or in this new arranged, where this can be controlled by way of an internal ROM fuse, for example. Under this new arrangement, the pin assignments would differ from the convention case, where rather that a set of, say, 8 pins being set aside for 10 function, the input bus 16 would instead have 8 input lines and the output bus 21 would have 8 output lines.

[0035] The memory chip 15 can operate in an active mode and a pass-through mode, with it typically useful to also have a stand-by mode. These modes are illustrated schematically in Figures 4-6. Figure 4 illustrates the standby mode, where the primary circuit portion 17 is not active and data is passed from the input bus 13 to the output bus 13. Addresses and commands, though, are clocked through the chip from the input bus 13 to the output bus 21.

[0036] In the pass through mode, illustrated in Figure 5, the circuit portion 17 is still inactive, but now in addition to passing commands, data is also passed though the DFF 19 from the input bus 13 to the output bus 21. In the active mode, schematically illustrated in Figure 6, the primary circuit portion 17 is now active, as well as the DFF 19 of the interface. Addresses and commands can again pass through from the input to the output, but data does not pass when the device is selected: in the case of a write, data received on the input lines of the bus 13 would be transferred on to the array; and, in the case of a read, data would be transferred of out of the primary circuit portion 17 and on to the output bus 21.

[0037] The ability of the interface based on the DFF 19 to pass commands, addresses and data from the input bus 13 to the output bus 21 allows for the memory chips to be connected according to a topology that can significantly reduce the amount of capacitive loading on the pins. This is described with respect to Figure 7. As shown in Figure 7, a set of memory chips are arranged into a tree type of structure, shown here to a depth of three tiers with each branch having a depth of 4 shown chips, where here each of the chips is being represented by its DFF portion. A first chip 101 in the arrangement would be connected to receive commands, addresses and data the DI input and a clock signal at CK from the controller. This would then be the only one of the tree of memory chips for the channel whose input bus is driven by the controller.

[0038] The output data lines 105 from 101 at DO are then connected to the data input DI at each of the (in this example) four chips 121, 123, 125, 127 of the second tier. Similarly, the output clock from CKO of 101 is supplied along 105 to the clock input CKI of each of the second tier chips. This process is then repeated at tier 3, where each of the tier 2 chips are connected to drive a number (four again, in this example) of chips, where only the chips 141, 143, 145, 147 being fed by chip 121 are shown to simplify the diagram for purposes of discussion. The data out lines of chip 121 are connected over 135 to the data input pins of each of 141, 143, 145, 147, with the clock signal transferred from CKO of 121 over line 133 to the CKI pin of each of 141, 143, 145, 147. Under this arrangement, each device only drives four chips at most, relative to the arrangement of Figure 1 where each IO channel from controller drives 64 chips. In addition to the tree-like structure of the tiers, the devices are also connected serially through their serially data outputs (SDO) and serial data inputs (DSI). The SDO output of chip 101 is carried over the line 107 to a first of the chips of the second tier, which are all connected serially, as is shown explicitly at 129. The last chip of tier 2 then has its SDO connected over 137 to the SDI input of the first of the chips in the series for tier 3, and so on, where one of the serial connections of tier 3 is shown explicitly at 149. The use of the serial clock can then be used in the selecting of the desired device.

[0039] Figure 8 shows a fuller development of the topology of the memory circuits within the memory system. In particular, this example only shows a single one of the IO channels from the controller 201 connected to a memory section having the memory chips connected according to a tree-like topology. This example for the memory section has five tiers that branch out with a branching ration of 3 at the second and third tiers, before shrinking back down in the last two stages. This particular example is symmetric both respect to how it branches out and then back in and in that the branching ratio for each chip, whether out or in, is the same. Although this symmetric is generally preferable in many cases as it more evenly distributes loading, other less symmetric arrangements can also be used.

[0040] In the exemplary arrangement of Figure 8, the controller 201 is only directly by the 10 channel output bus to the first chip 211 in the tree structure. (In Figure 8, each memory device is again represented only by the DFF of its interface.) Here the portion of the bus structure 261 includes both the data and clock input, DI and CK. The serial clock signal is shown separated out from the other command, address, and data signal to illustrate its serial structure, as opposed to the tree structure used by the other lines. The segments of the main bus then branch from the first to the second, and second to the third tier as described above with respect to Figure 7, and then, going from the third to the fourth and fourth to fifth tier, mirror this arrangement by fanning back in to the last device 241. The output bus section 263 from the last tier is then the input for the 10 channel. The serial output bus 251 from the controller then works its way serially through the tiers and serially within each of the tiers.

[0041] Figure 9 shows the same elements as in Figure 8, but without explicitly including the serial connections, and can be used to illustrate the flow of data for a write operation and how the different device modes are used. In this example, device 225 in the third tier is selected for a write operation. Consequently, device 225 is selected and placed in the active mode. As the path from the controller 201 to device 225 passes through chips 211 and 215, these need to pass the data as well as any commands and addresses and are in the pass-through mode. Any of the other devices that are not needed can then sleep in the stand-by mode, not passing data and saving power. As stand-by mode allows the any commands to pass, any status signals needing to be returned to the controller can pass through devices 239 and 243 and back along section 263 of the bus structure.

[0042] Figure 10 illustrates the read counterpart to the write operation of Figure 9. Device 225 in the third tier is again selected, but this time for a read operation, and is correspondingly in the active mode. As devices 239 and 243 need to pass the data back to the controller over bus segment 263, they will be in the pass-through mode. The rest of the memory devices can sleep to save on power, where chips 211 and 215 pass the commands and addresses to the selected device 225.

[0043] The memory section of Figures 8 can be arranged into a single package, as shown in Figure 11. Here the 17 die are formed into a single, 17 die package. As the input is only supplied to a single chip, the input loading is only one memory chip. Similarly, the output loading is only a single chip. The pin count is also corresponding reduced relative to a package where all of the chips directly attach to the bus structure. The internal loading is 1 memory chip driving at most 3 other chips. For a larger memory section, the packages also themselves can be arranged into a tree structure as shown in Figure 12. Arranged in three tiers with a fan out of three, the 5 17 die packages can provide a channel with a total of 85 dies, again with an output and input loading of only a single device and an internal loading of no more than 3 devices. The structures of Figure 12 can then themselves be arranged into a tree structure and the board level for an even larger capacity memory channel. [0044] Figure 13 looks at another package embodiment, which again has 5 tiers, but with a fan out of 2, resulting in a 10 die package. These can 10 die packages can then also be arranged into a 5 tiers with a fan out of two, for a total of 100 dies, as shown in Figure 14. Consequently, using 16 channels supporting a total of 1600 dies would provide for 25.6TB of storage based uponl6GB dies. A 6TB system with 100% over- provisioning can similarly be built with only 8 channels.

[0045] Within the package, the input and output pad sets can be swapped from chip to chip to more efficiently implement the topology. This can shorten and simplify the connections between the outputs of one tier with the inputs of the following tier. One exemplary embodiment for the 10 die package of Figure 13 is illustrated schematically with respect to Figures 15A-C. Figures 15A-C show the 10 chips (303, 305, 307, 323) stacked up on the package board 301. Figure 15A is a view from the front, toward the bond pads with the input pads shown in black, the output pads as white, and the gray pads at top and bottom are those for the package. Here the collective input and output pads are each represented by a single pad, one to the right and one to the left of the edge of each chip. Figure 15B then would be the view along the bond pad of the stack from the left hand side showing only the left IO pad group. Figure 15C is then the right hand side counterpart of Figure 15B. For example, as shown on the fright side of Figure 15A and in Figure 15B, the bottom chip 303 has its input pads connected to the packages input pads. As shown on the left side of Figure 15B and in Figure 15C, the output pads of 303 are then connected to the inputs of 305 and 315 for the fan out of two. The other connections are similarly represented. [0046] As noted, Figures 15A-C represented each of the input and output pads by a single collective pad. Figures 16A and 16B illustrate the situation in more detail for the multiple pads of a device, here in an example with 8 each for input and output for four of the dies, where both sets are grouped together. Figure 16A illustrates the problems that can arise without the swapping of input and output pads, as the bonding wires would need to be constantly crossing between chips in the package, makings implement the desired topology very difficult on the package level. To solve this packaging issue, the pads belonging to the same pipelines can be aligned as illustrated in Figure 16B. Both arrangements of the pads can use the same version of the chip, but the sets of pads can used either for input or output. The differentiation between input and output can be done several ways, such as through a command, an internal fuse control, or through the bonding pad. In the preferred embodiment, a bonding pad is used, which can be set at either Vcc or Vss to determine which set is for input and which is for output. This is illustrated in Figure 16B by the configuration pad IOCFG, that can be used to configure which pad group is used for input and which is used for output. In Figure 16B, the elements of each set are shown to be adjacent to each other, but these may distributed differently; for example, they could alternate as in Figure 16A, but with the assignments of dies 2 and 4 swapped, such as is shown in Figure 16C. In Figure 16C, the configuration of the sets of pads can be done similarly to as described with respect to Figure 16B, such as with a configuration pad IOCFG (not shown in Figure 16C).

[0047] Figure 17 is a simplified box diagram to illustrate an example of how this swapping of input and output pads can be implemented. A memory chip 400 has a series of pads represented 401, 403 and 405. The pads include the input output configuration IOCFG pad 405 and the two equal sets 401 and 403 of pads that are connected to the switchable connection circuit 411. The other elements of the circuit are grouped together as block 413 with a set of output lines 421 and a set of 423. Based on the level at the IOCFG pad 405, the lines 421 can be attached to the pad set 401 or the pad set 403, with the lines 423 going to the other set. Although the exemplary embodiment uses a specific bonding pad to determine the connection, other embodiments can be based on a command or internal fuse control.

[0048] Both in Figure 17 and in Figure 16B, the elements of each set are shown to be adjacent to each other, but these may distributed differently; for example, they could alternate as in Figure 16C, but with the assignments of dies 2 and 4 swapped. This is illustrated in Figures 18A and 18B that show an exemplary set pad assignments for a more conventional arrangement (in the first column) and then the pad assignments for the case of a swappable set of input and output pads. The Die Group 1 column shows one alignment, here implemented by setting the IOCFG pad to VDD (bottom row), and the Die Group 2 column shows the swapped alignments, here implemented by setting the IOCFG pad to VSS. In the conventional assignments, a number of pads (such as IO0-IO7) function as input-output pads, while in the other columns a number of pads have specific input or output assignments, where these are swapped based on the on the IOCFG level. (Note that although most pads swap depending on their group assignment, the latch enable signal, CLE/ALE, is the same in both assignments.) In Figure 18A, the IN and OUT pads are grouped together, as illustrated in Figure 16B, while Figure 18B illustrates an interleaved arrangement, similar to Figure 16B, but with swapping between Die Groups 1 and 2. Additionally, as shown in Figures 16B and 17, all of the pads except he IOCFG pads swap, but there can also be other pins (not shown), such as a clock signal or supply level, that go straight through and stay with the same pad assignment independently of the IOCFG level. [0049] Figure 19 looks at the swapping mechanism for a given pad in more detail. Pad 501 is one of the swappable pads of the device, which here has the internal data- in DIN bus 521, data-out DOUT bus 523, and control CTRL bus 525. These buses are then connectable to the pad 501 through either an output buffer 511 or an input buffer 513. Based on the value on line 503, such as set by a ROMFUSE or the IOCFG, the pad 501 either functions as an input to supply data and commands to the DIN 521 and CTRL 525 buses or as an output to receive data from the DOUT bus 523.

[0050] As noted above, in the exemplary embodiment the memory chip can be operated in one mode with the pins assigned as developed above, with a number of pins being set aside as input bus lines and a similar number set aside as output bus lines, or in mode using a standard interface, as in Figure 2 and with pad assignments such as in the "conventional" columns of Figures 18A and 18B. This can be controlled by way of an internal ROM fuse, for example, such as those represented at 415 of Figure 17. This increases the versatility of the chip. As the need to swap the connections to the pads 401 and 403 would not be needed when the pads are assigned in the conventional mode, the swap function of 411 would not be used and the pad 405 would be used and could be reassigned to a different function the conventional pad assignment mode. Although the sort of tree like structure described above can be optimal for large size systems, for smaller systems the conventional assignments can be preferable for medium or smaller sized systems.

[0051] Figures 20A-C correspond to Figures 15A-C, but with an alternate assignment of pads with both the input and output pads placed together on the package board 301. More specifically, the lower chips are arranged the same, but with one more chip 325 added, making a 11 -chip package. In this arrangement, the input of the lowest chip 303 and the output of the top chip 325 are both to the right. Figure 21 then illustrates the corresponding topology of the chips in a package. As with 10 die package of Figure 13, this alternate embodiment also uses a maximum fan-out of 2, but includes the last chip to the left whose output now also lies along the left side of the package of this alternate embodiment. As noted above, the tree structure need not be symmetric and in other embodiments, other or additional 1-1 chip arrangements can be added before or after the fan out or even in the central portions. [0052] Figure 22 illustrates an embodiment of a memory system of four 11 -die packages as shown in Figure 21 all connected to the same port: The fan-out is only 4 on the controller, but 2 inside package, so that maximum total fan-out is four. This results in 44 dies on the same channel, which, under the conventional arrangement of Figure 1 would need a fan-out of 44. [0053] For any of these arrangements, as the signals travel through the branches to the different chips of the tree, the signals should preferably maintain a degree of synchronization. The re-synchronization can be done through a delay-tunable clock buffer arranged such that data are resynchronized. The delay elements, which were not explicitly shown in the earlier figures, can mostly be placed at the input and/or the output of the clock buffer. Figures 23A and 23B show two exemplary embodiments of circuits for data propagation with re-synchronization. Both circuits use a double data rate (DDR) arrangement, with data (DIN) and clock (CKIN) inputs and data (DOUT) and clock (CKOUT) outputs. The arrangement of circuit of Figure 23B additionally includes an inverse for clock signal for propagating through the tree structure, where the inverse for the input and output clocks are shown at CKIN# and CKOUT#.

[0054] Figure 24 and 25 illustrates a pair of additional memory chip modes that can used in alternate embodiments, with a corresponding exemplary topology shown in Figure 26 whose operation is illustrate with respect to Figure 27. Referring back to Figures 4-6, these illustrate a standby mode, a pass-through mode, and an active mode. As described further above, in the pass-through mode, address/commands and data are passed from the input bus 13 to the output bus 21, while the primary circuit section 17 is inactive; and in the active mode, addresses and commands can pass, but the primary circuit section is active where data does not pass, either coming in from the input bus 13 into primary circuit section 17, or out from the primary circuit section 17 on to the output bus 21. In Figures 24 and 25, the chip is modified to additionally, or alternately, include a reverse-pass though mode and a reverse active mode. In Figures 24 and 25, the corresponding elements are numbered the same as in Figures 4-6, but where the primes have been added as the elements 13', 2 , and 19' also although a reverse flow, with the input 13' now also can have an output function and conversely for the output 21 '.

[0055] More specifically, Figure 24 illustrates a reverse pass-through mode. As with (forward) pass-through mode, the primary circuit section 17 can again be inactive. Data is again passed through, but now in the reverse direction, from the second input/output port connected at 2 , clocked through the flip-flop 19' in the reverse direction, and out the first I/O port connected at 13'. In the exemplary embodiment, there is not a need to pass addresses and commands in the reverse direction.

[0056] Figure 25 illustrates a reverse active mode, where, as with the (forward) active mode, the circuit portion 17 is again active, but data is output from the memory via the first I/O part 13', which was only used for input in the (forward) active mode. As with the reverse pass-through mode, there is not a need to pass addresses and commands in the reverse direction. As the reverse-active mode allows for the data to be output from the first I/O node 13', depending on the arrangement of the chips within the memory system, there may no longer be the need to for data also to output at the second I/O port 2 . (This is the case for the arrangements described below with respect to Figures 26 and 27.) Consequently, there is not a need for the (forward) active mode to be able to output data at the second I/O port 2 , so functionality can be omitted, in which case the active and reverse active modes can be considered as the input and output phases of an active mode. As with the selection of a more traditional or the modes of Figures 4-6, the selection of the reverse modes instead of, or in addition to, the arrangements where data goes out the second I/O port can be based on a ROM fuse, a command or commands, a level on one or more pads, and so on.

[0057] The inclusion of the reverse modes allows additional topologies to be used. The topologies discussed above mainly looked at the case of a tree like structure where the chips fanned out from a single initial chip, then fanned back down to a final chip and data went in one side (the chip's input bus) and out the other (output bus) as illustrated schematically as a left to right flow in the figures. With the reverse modes, the memory devices can again be structured to fan out in a tree structure, but need not fan back in, where data can be sent back out in the reverse direction to the same "trunk" device, and then out to the controller or host. This is illustrated with respect to Figures 26 and 27.

[0058] Figure 26 illustrates an embodiment with a fan out of 3 from each memory device and can be compared to Figure 8: In both of Figures 26 and 8, the outputs of each memory device is connected to the input of 3 additional memory devices for three levels; however, they differ in that Figure 8 fans back to the final chip, whose output then loops back to the controller. In contrast, Figure 8 lacks these last two levels of Figure 8. (As with the earlier figures of this type, Figure 8 is meant to illustrate the topology of the devices connections, not their actual physical arrangement.) Instead, by adding the two reverse modes, commands and addresses will again flow from controller to the last devices in the last tier, with input data flowing in a similar way; but output data will flow back through the same path as the input data except in the reverse direction, as illustrated schematically in Figure 27. [0059] The top part of Figure 27 shows an example of the flow of data and commands for a channel from the controller out to a selected device in the third tier, again based on the addresses and through the use of the serial connections, as illustrated by the large arrow. The lower part of Figure 27 similarly illustrates the flow of data and responses back to the controller. By using the reverse modes, there is no longer the use of a feedback path as data output from the memory devices flows back the same path as for the input data, effectively reducing the loading on the controller path by half. Under the type of topology illustrated the by Figure 26 using the reverse modes, because data output from memory devices flows through the same path as data input, there is no need to have the any memory devices receiving input from multiple devices to provide small fan-out to the controller. This allows for a constant fan-out throughout the network, maintaining similar signal integrity throughout the whole network.

[0060] For any of the embodiments discussed above, the tree like arrangement can have significant advantages over the more common arrangement illustrated with respect to Figure 1. In particular, the load stays low and uniform even when large numbers of dies are used on a channel: for example, although the load increases linearly with the number of die for the arrangement of Figure 1 , the tree-like structure presented here has a largely constant load based on the degree of fan out, so that if the number of die in the channel were, say, 200, the worst case load is only a few die rather than the full 200. This can lead to higher performance and allow the use of high clock rates. Although the data and commands may need to propagate through a few tiers to get to a selected device, this only a minor performance penalty as, in addition to higher clock rates, a large degree of parallelism and pipelining can be used in the tree-like structure. Additionally, the use of the tree structure and the ability to put to sleep non-selected devices (as described above with respect to Figures 9 and 10) can significantly reduce power consumption of a channel.

[0061] A further advantage of the tree-like relates to how defective chips can be handled. Defects will largely occur in the primary circuit portion, rather than more basic circuitry of the interface's flip-flop. If a chip is found to be defective during operation, as long as the DFF portion of the circuit can pass signals, the chips that fan out, the device can be placed into stand-by mode and mapped out. Additionally, under this arrangement, testing procedures can be simplified as the primary circuit portion need not be tested since due to the available high degree of redundancy, any chips that turn out to be defective can just be treated the same devices that fail during later operation by being put into a permanent standby mode. [0062] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

IT IS CLAIMED:

1. A non- volatile memory system comprising

a memory section having a plurality of non-volatile memory circuits, each of the memory circuits including an array of non-volatile memory cells and a latch circuit, where the latch circuit is connectable to a bus input to receive data and commands therefrom and to a bus output to provide data and responses therefrom, wherein, in response to commands received on the bus input the memory circuit can operate in a plurality of modes including: a pass-through mode, wherein the memory array is inactive and commands and data are passed by the latch circuit from the bus input to the bus output; and an active mode, in which the memory array is active and data can be transferred between the memory array and the bus input or bus output by the latch circuit; and

a bus structure connecting the bus inputs and bus outputs of the non-volatile memory circuits for the transfer of data and commands, including:

an input bus for the memory section connected to the bus input of a first of the memory circuits;

an output bus for the memory section connected to the bus output of a second of the memory circuit;

a first intermediate bus connecting the bus output of the first memory circuit to the bus inputs of a first set of multiple other ones of the memory circuits, the first set not including the second memory circuit; and

a second intermediate bus connecting the bus input of the second memory circuit to the bus outputs of a second set of multiple other ones of the memory circuits, the second set not including the first memory circuit.

2. The non- volatile memory system of claim 1, wherein the memory section is formed as a single multi-die package.

3. The non- volatile memory system of claim 1, wherein first and second memory circuits are formed as part of different multi-die packages.

4. The non- volatile memory system of claim 1, wherein the modes further include a standby mode, wherein the memory array is inactive and data are not passed by the latch circuit from the bus input to the bus output.

5. The non- volatile memory system of claim 1, wherein the first and second sets are the same.

6. The non- volatile memory system of claim 1, wherein the first and second sets are different and wherein the bus structure further includes:

a plurality of third intermediate busses each connecting the bus output of one of the first set of memory circuits to the bus inputs of a third set of multiple other ones of the memory circuits; and

a plurality of fourth intermediate busses each connecting the bus input of one of the second set of memory circuits to the bus outputs of one of the third set of the memory circuits.

7. The non-volatile memory system of claim 6, wherein the first and second sets each have a plurality of N memory circuits, the number of third sets is N, and each of the third sets has N memory circuits.

8. The non-volatile memory circuit of clam 7, wherein N=2.

9. The non- volatile memory circuit of clam 7, wherein N=3.

10. The non- volatile memory system of claim 1, wherein the latch circuit has: a first input connectable to the bus input of the memory circuit;

a first output connectable to the bus output of the memory circuit; a clock input; and

a clock output,

wherein the clock output of the first memory circuit is connected to provide the clock inputs of each of the first set of memory circuits, the clock input of the second memory circuit is connected to receive the clock output from one or more or the second set of memory circuits.

11. The non- volatile memory system of claim 10, wherein the latch circuit further includes re-synchronization circuitry to maintain synchronization of signals on the bus structure.

12. The non- volatile memory system of the claim 1, further comprising:

a controller circuit connectable to the input bus for providing data and commands to the memory section and connectable to the output bus for receiving data and responses from the memory section to manage the storage of data on the memory section.

13. The non- volatile memory system of claim 12, wherein the memory section is formed of a single multi-die package.

14. The non-volatile memory system of claim 12, wherein the memory section is formed of a plurality of multi-die packages, wherein the first memory circuit is on a first of said multi-die packages, the second of the memory circuits is on a second of the multi-die package, and an output bus of the first multi-die package is connected to an input bus of a plurality of other multi-die packages, and an input bus of the second multi-die package is connected to an output bus of a plurality of other multi-die packages.

15. The non- volatile memory system of claim 12, wherein the memory section is formed of a plurality of circuit boards each having a plurality of multi-die packages, wherein the first memory circuit is on a multi-die package of a first of the circuit boards, the second of the memory circuits is on a multi-die package of a second of the circuit boards, and an output bus of the first circuit board is connected to an input bus of a plurality of other circuit boards, and an input bus of the second circuit board is connected to an output bus of a plurality of other circuit boards.

16. The non-volatile memory system of claim 12, wherein each of the latch circuits has:

a first input connectable to the bus input of the memory circuit; a first output connectable to the bus output of the memory circuit; a clock input; and

a clock output,

wherein the clock input of the first memory circuit is connected to receive a clock signal from the controller circuit, the clock output of the first memory circuit is connected to provide the clock inputs of each of the first set of memory circuits, the clock input of the second memory circuit is connected to receive the clock output from one or more or the second set of memory circuits.

17. The non-volatile memory system of claim 16, wherein each of the latch circuits also has:

a serial output; and

a serial input,

wherein the latches of the first and second sets are connected in series with the serial output of each latch of the set except the last being connected to the serial input of each latch of the set except the first, wherein the serial input of the first latch of the first set is connected to the serial output of the first latch, the serial output of the last latch of the second set is connected to the serial input of the second latch, and the serial input of the first latch is received from the controller circuit.

18. The non- volatile memory system of claim 12, where in response to the controller circuit determining that one of the memory circuits is defective, the controller circuit does not operate the defective memory circuit in the active mode, but can operate the defective memory circuit in the pass-through mode.

19. The non- volatile memory system of claim 1, wherein the latch circuit also has:

a serial output; and

a serial input,

wherein the latches of the first and second sets are connected in series with the serial output of each latch of the set except the last being connected to the serial input of each latch of the set except the first, wherein the serial input of the first latch of the first set is connected to the serial output of the first latch, and the serial output of the last latch of the second set is connected to the serial input of the second latch.

20. The non- volatile memory system of claim 1, wherein the output bus for the memory section connected to the bus output of a second of the memory circuit through one or more additional memory circuits.

21. A non- volatile memory system comprising

a memory section having a plurality of non-volatile memory circuits, each of the memory circuits including an array of non- volatile memory cells and a latch circuit, where the latch circuit is connectable to a first input-output port to receive data and commands and provide data therefrom and to a second input-output port to provide data and commands and receive data therefrom, wherein, in response to commands received on the first input-output port the memory circuit can operate in a plurality of modes including: pass-through modes, wherein the memory array is inactive and commands and data are passed by the latch circuit from the first input- output port to the second input-output port or from the second input-output port to the first input output port; and active modes, in which the memory array is active and data can be transferred between the memory array and the first input-output port by the latch circuit; and

a bus structure connecting the first input-output ports and second input-output ports of the non-volatile memory circuits for the transfer of data and commands, including:

an initial bus segment for the memory section connected to the first input-output port of a first of the memory circuits; and

a first intermediate bus segment connecting the second input-output port of the first memory circuit to the first input-output ports of a first set of multiple other ones of the memory circuits.

22. The non- volatile memory system of claim 21, wherein the memory section is formed as a single multi-die package.

23. The non- volatile memory system of claim 21, wherein first and second memory circuits are formed as part of different multi-die packages.

24. The non- volatile memory system of claim 21, wherein the modes further include a standby mode, wherein the memory array is inactive and data are not passed by the latch circuit from the first input-output port between the second input-output port.

25. The non- volatile memory system of claim 21, wherein the latch circuit has:

a first input connectable to the first input-output port of the memory circuit;

a second input connectable to the second input-output port of the memory circuit;

a clock input; and

a clock output,

wherein the clock output of the first memory circuit is connected to provide the clock inputs of each of the first set of memory circuits.

26. The non- volatile memory system of claim 25, wherein the latch circuit further includes re-synchronization circuitry to maintain synchronization of signals on the bus structure.

27. The non- volatile memory system of claim 21, wherein the latch circuit also has:

a serial output; and

a serial input,

wherein the latches of the first set are connected in series with the serial output of each latch of the set except the last being connected to the serial input of each latch of the set except the first, wherein the serial input of the first latch of the first set is connected to the serial output of the first latch.

28. The non-volatile memory system of the claim 21, further comprising: a controller circuit connectable to the initial bus segment for providing data and commands to the memory section to manage the storage of data on the memory section.

29. A non- volatile memory integrated circuit, comprising:

a plurality of external contact pads, including:

a first set of a plurality of N external contact pads; and a second set of N external contact pads;

a primary circuitry portion including a non-volatile memory array and associated peripheral circuitry and having, when operating in a first mode, N input lines and N output lines; and

switching circuit connected to the first and second sets of external contact pads connected to the input and output lines, where the switching circuit can selectively attach the first and second sets of external contact pads to the input and output lines in either a first configuration, where the N input lines are attached to the first set of external contact pads and the N output lines are attached to the second set of external contact pads, or in a second configuration, where the N input lines are attached to the second set of external contact pads and the N output lines are attached to the first set of external contact pads.

30. The non-volatile memory integrated circuit of claim 29, wherein the external contact pads further include a first additional contact pad connectable to the switching circuit, and, when operating in the first mode, the voltage level on the first additional contact pad selects whether the first and second sets of external contact pads and the input and output lines are connected according to the first or second configuration.

31. The non- volatile memory integrated circuit of claim 29, wherein when operating in the first mode, whether the first and second sets of external contact pads and the input and output lines are connected according to the first or second configuration is based upon a command received by the non- volatile memory circuit.

32. The non-volatile memory integrated circuit of claim 29, wherein when operating in the first mode, whether the first and second sets of external contact pads and the input and output lines are connected according to the first or second configuration is based upon a fuse value set on the integrated circuit.

33. The non- volatile memory integrated circuit of claim 29, wherein the external contact pads further include one or more first additional contact pads connected to a corresponding one or more signal lines from the primary circuitry portion, wherein the connections of the additional contact pads to the signal lines is the same for both the first and the second configuration.

34. The non-volatile memory integrated circuit of claim 29, wherein the primary circuitry portion can be set to operate in either the first mode or in a second mode, wherein the 2N lines that operate as the N input lines and N output lines while operating in the first more are assigned a different set of functions when operating in the second mode.

35. The non- volatile memory integrated circuit of claim 34, wherein when operating in the second mode, one or more of the 2N lines having a combined input- output function.

36. The non-volatile memory integrated circuit of claim 34, wherein when the primary circuitry portion is set to operate in one the first and second modes based on a fuse value as set on the integrated circuit.

37. The non-volatile memory integrated circuit of claim 29, wherein each of the first and second sets of contact pads are located as adjacent groups along the integrated circuit.

38. The non-volatile memory integrated circuit of claim 29, wherein pads of the first and second sets of contact pads are interspersed along the integrated circuit.

39. A non- volatile memory package having:

multiple external bonding pads formed thereupon, the external bonding pads including a plurality of external input pads and a plurality of external output pads, and containing a plurality of non-volatile memory chips each having a first set and a second set of N contact pins where each of the memory chips can be individually configured to operate in either a first configuration, where the first set of pins are input pins and the second set of pins are output pins, and a second configuration, where the first set of pins are output pins and the second set of pins are input pins, wherein the memory chips include a first memory chip connected with the input pins thereof connected to the external input pads, a second memory chip connected with the output pins thereof connected to the external output pads, and one or more additional memory chips, where, aside from the input pins of the first memory chip and the output pins of the second memory chip, the first, second and additional memory chips are connected so that the output pins of each memory chip are connected to the input pins of one or more other memory chips and the input pins of each memory chip are connected to the output pins of one or more other memory chips, and

wherein the memory chips are stacked with chips configured according to the first configuration interleaved with chips configured according to the second configuration.

40. The non-volatile memory package of claim 39, wherein the external input pads and the plurality of external output pads are formed along the same edge of package.

41. The non- volatile memory package of claim 39, wherein the external input pads are formed along a different edge of package from the plurality of external output pads.

42. The non-volatile memory package of claim 39, wherein the memory chips are interconnected according to a tree-like structure where the output pins of at least one of the memory chips are connected to the input pins of multiple other ones of the memory chips and where the input pins of at least one of the memory chips are connected to the output pins of multiple other ones of the memory chips.