WO2014201488A1 - Double-layer capacitor comprising a porous semiconductor capacitor electrode - Google Patents

Double-layer capacitor comprising a porous semiconductor capacitor electrode Download PDF

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Publication number
WO2014201488A1
WO2014201488A1 PCT/AT2014/050134 AT2014050134W WO2014201488A1 WO 2014201488 A1 WO2014201488 A1 WO 2014201488A1 AT 2014050134 W AT2014050134 W AT 2014050134W WO 2014201488 A1 WO2014201488 A1 WO 2014201488A1
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Prior art keywords
semiconductor
device layer
layer
component according
capacitor
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PCT/AT2014/050134
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German (de)
French (fr)
Inventor
Ulrich Schmid
Andreas BACKES
Timo BOHNENBERGER
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Technische Universität Wien
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Publication of WO2014201488A1 publication Critical patent/WO2014201488A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/78—Cases; Housings; Encapsulations; Mountings
    • H01G11/82—Fixing or assembling a capacitive element in a housing, e.g. mounting electrodes, current collectors or terminals in containers or encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/26—Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/26—Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features
    • H01G11/28—Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features arranged or disposed on a current collector; Layers or phases between electrodes and current collectors, e.g. adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/30—Electrodes characterised by their material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
    • H01G11/86—Processes for the manufacture of hybrid or EDL capacitors, or components thereof specially adapted for electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries

Definitions

  • the invention relates to a semiconductor component, formed on a semiconductor substrate having at least one device layer and an insulator layer, and a method for the production thereof.
  • Electrochemical double-layer capacitors are often used when large amounts of power and energy have to be absorbed or released. In this capacity, they close the gap between conventional capacitors (high power density) and batteries (high energy density). In the simplest version, they consist of two opposite electrodes (usually carbon), which are electrically insulated from each other by an ion-permeable membrane. An electrolyte is introduced between the electrodes whose ions form an electrochemical double layer when voltage is applied to the electrode surface and in this way store charges.
  • Priority potential applications with particular economic importance are, for example, in the fields of electric traction (motor vehicles) and telecommunications. This can be reduced by intercepting power peaks, the rated power of the primary energy source, the life and range extended and thus the efficiency of the overall system can be significantly improved. Of particular interest to the present invention are further energy self-sufficient sensor nodes on the chip level.
  • Helmholtz bilayers Essential to the function of electrochemical double-layer capacitors is the potential-controlled formation of Helmholtz bilayers, which makes it possible to use carbon electrodes such as carbon nanotubes. Active carbon materials, which have an extremely high porous surface, appear unfavorable, since the distribution of the pore sizes in these materials is very broad and sometimes extending to the range of about 1 nm. Since typical Helmholtz layer thicknesses are even up to 5 nm, the Helmholtz storage layer can not be completely formed on the surface actually present in this electrode material.
  • DE 199 48 742 C1 has already proposed electrodes made of electrically conductive or semiconducting nanostructured elements.
  • This document relates in particular to the production of such an electrode by electrochemical growth of discrete, needle-shaped elements on a correspondingly structured surface, wherein these electrodes or capacitors must subsequently be integrated into chips or printed circuit boards.
  • SOI silicon on insulator
  • an insulator layer for example of silicon oxide
  • the circuits are located in the so-called “device layer” or “device layer” which is separated by the insulator layer from the "bulk” or the “handle wafer”. SOI substrates are advantageous in terms of shorter switching times and lower power consumption, especially with regard to leakage currents.
  • the hitherto known nanostructured semiconductor capacitor electrodes can be integrated with SOI substrates only with relatively great effort, which is why the object of the present invention is to arrange such electrodes or capacitors more simply and less costly on SOI substrates.
  • the invention is therefore characterized by at least one semiconductor capacitor electrode in the device layer in the form of a porous region formed from the device layer.
  • the invention is therefore not to manufacture semiconductor capacitor electrodes as separate components, which subsequently have to be integrated into SOI chips, but these electrodes already on a semiconductor substrate, which can be further processed into a chip in sequence, train. In this way, the fabrication of semiconductor-based double-layer capacitors can be integrated into the manufacturing process of chips, which enables the cost-effective production of high-performance elements in large quantities with relatively low production costs.
  • the invention is preferably developed in such a way that the porous region forming the at least one capacitor electrode in the plane of the device layer is surrounded by trenches extending to the insulator layer is.
  • trenches are known as recesses or cuts in a semiconductor substrate which, like trenches, pass through the substrate layer, in this case through the device layer.
  • said trenches thus surround the at least one capacitor electrode and the porous region, respectively, like a circumferential trench extending down to the insulating layer of the semiconductor substrate, thereby providing complete electrical isolation of the porous region serving as a semiconductor capacitor electrode , is achieved.
  • a semiconductor device according to this preferred embodiment therefore allows the storage of large amounts of charge in an electrochemical double-layer capacitor without significant leakage currents, i. The loss of charges in the substrate, must be accepted.
  • a capacitor is formed by a semiconductor capacitor electrode in the device layer and a further semiconductor capacitor electrode arranged thereon.
  • a semiconductor capacitor electrode in the device layer and a further semiconductor capacitor electrode arranged thereon.
  • only one of the two semiconductor capacitor electrodes integrally formed with the semiconductor substrate and the further capacitor electrode is a separate component, which is determined by methods described below on the semiconductor substrate and contacted accordingly.
  • a particularly high degree of integration of semiconductor components is achieved if a capacitor of two semiconductor capacitor electrodes arranged side by side in the device layer is formed, as corresponds to a preferred variant of the present invention.
  • Such a geometry is favorable in terms of dynamic properties such as charging and discharging times of the electrochemical double-layer capacitor, since diffusion of the electrolyte between the circuit boards is facilitated and no portions are formed in the porous regions with respect to the remaining electrolyte system, and therefore the entire surface area of the porosity Electrode surface is available.
  • the semiconductor capacitor electrodes arranged next to each other be made of a dielectric material, in particular a glass wafer are covered.
  • the semiconductor substrate has a device layer thickness of 5 ⁇ m - 15 ⁇ m, in particular 10 ⁇ m. At this device layer thickness, the best possible results were achieved in the experiment.
  • the semiconductor substrate has an insulator layer thickness of 0.5 ⁇ m - 2 ⁇ m, in particular 1 ⁇ m.
  • the semiconductor substrate has a handle wafer thickness of 300 ⁇ - 700 ⁇ , in particular 550 ⁇ , on.
  • a preferred distance of the capacitor electrodes is given when the capacitor electrodes 5 ⁇ - 10 ⁇ are spaced apart.
  • the present invention is in principle applicable to a number of different semiconductor substrates, such as silicon carbide, gallium arsenide, or indium compounds, or to a combination of a single crystal silicon layer on a dielectric substrate,
  • semiconductor substrate such as silicon carbide, gallium arsenide, or indium compounds
  • SOS silicon on sapphire
  • the semiconductor substrate be formed by a silicon on insulator (silicon on insulator) wafer.
  • the at least one porous region is formed by tubular cavities which extend from the surface of the device layer to the insulator layer. If both semiconductor capacitor electrodes are arranged side by side in the device layer, it is preferred, however, if the porous regions are formed by tubular cavities extending parallel to the surface of the device layer.
  • Such a geometry is favorable in terms of dynamic properties such as charging and discharging times of the electrochemical double-layer capacitor, since diffusion of the electrolyte between the circuit boards is facilitated and no portions are formed in the porous regions with respect to the remaining electrolyte system, and therefore the entire surface area of the porosity Electrode surface is available.
  • the method according to the invention for the production of a semiconductor component comprises the following steps: a) Provision of a semiconductor substrate with at least one device layer and one insulator layer
  • Metal-assisted etching is well known in the art and is described in detail in particular in the article "Metal Assisted Chemical Edging of Silicone: A Review” from Advanced Materials (Adv. Mater., 2011, 23, 285-308).
  • metal particles of the size of the desired porosities are applied to the surface of a semiconductor, such as silicon, and the semiconductor substrate thus treated is coated in an aqueous etching solution containing an oxidizing agent, such as H 2 O 2 , and an acid, in particular HF (Hydrofluoric acid), spent.
  • the metal particles act as catalysts, with silver being particularly preferred.
  • cathodes form on the metal particles, at which hydrogen peroxide (H2O2) is reduced.
  • the silicon atoms under the metal are oxidized and dissolved out by the acid.
  • the metal particles sink more or less perpendicular with respect to the surface in the semiconductor and form corresponding channels.
  • these can also be different in the semiconductor Describe webs, but these are oriented substantially along the lattice structure of the silicon.
  • the metal-assisted etching comprises the use of an aqueous solution of 5.0M-5.5M, in particular 5.3M hydrofluoric acid and 0.15M-0.2M, in particular 0.18MH 2 0 2 .
  • FIG. 1 is a schematic sectional view of a first embodiment according to the present invention
  • FIG. 2 shows a schematic sectional view of an alternative embodiment according to the present invention
  • FIG. 3 shows a scanning electron micrograph of a section through a porous region according to the invention in a device layer of an SOI substrate
  • FIG. 4 shows a scanning electron micrograph of a plan view of a porous region according to the invention in a device layer of an SOI substrate
  • Figure 5 is a schematic sectional view of a preferred embodiment of the present invention in which at least one porous region is formed by tube-like cavities extending parallel to the surface of the device layer.
  • FIG. 1 designates an SOI substrate which essentially consists of a device layer 2, an insulating layer 3 and a handle wafer 4.
  • the insulating layer 3 ensures electrical insulation between the device layer 2 and the handle wafer or the bulk 4.
  • a first semiconductor capacitor electrode in the form of a porous region 6 formed from the device layer 2 is denoted by 5, wherein the semiconductor capacitor electrode 5 is electrically connected by means of a bonding wire 7 with a circuit not shown in detail on the SOI substrate 1.
  • a second semiconductor capacitor electrode 8 is arranged, wherein a cavity 9 is formed, which is filled with a suitable electrolyte. The filling can take place, for example, via a filling hole 10, which can be closed with a glass lid 11.
  • the second semiconductor capacitor electrode 8 is in turn connected via a bonding wire 12 to corresponding structures on the SOI substrate.
  • the first semiconductor capacitor electrode 5 and the second semiconductor capacitor electrode 8 form, together with the electrolyte in the cavity 9, an electrochemical double-layer capacitor.
  • Trenches 13 surround the semiconductor capacitor electrode 5 in the device layer 2 and thus isolate the electrochemical double-layer capacitor from the remainder of the device layer 2.
  • both the first semiconductor capacitor electrode 5 and the second semiconductor capacitor electrode 8 are arranged side by side in the device layer 2 and a cover 14 of dielectric material, such as a glass wafer, forms a closed cavity 9 for the device Electrolytes.
  • Another trench 15, which reaches down to the insulating layer 3, provides for a separation of the two semiconductor capacitor electrodes 5 and 8.
  • the photograph according to FIG. 3 shows that the porous region 6 is formed in the form of essentially rectilinear porosities, which are formed in the metal-assisted chemical etching process.
  • the porosities in the device layer 2 have an enormously high electrode surface area for the formation of Helmholtz double layers, whereby particularly high capacitances of the capacitor can be achieved.
  • the porous regions are formed by tube-like cavities extending parallel to the surface of the device layer, which differs from the variants of the present invention shown in FIGS. 1 and 2 with regard to the dynamic properties of the electrochemical double-layer capacitor and above all in terms of loading and unloading is beneficial.

Abstract

The invention relates to a semiconductor component formed on a semiconductor substrate comprising at least one device layer and one insulating layer, said component being characterised by at least one semiconductor capacitor electrode in the device layer configured in the form of a porous region formed in the device layer. The method according to the invention comprises the following steps: a) providing a semiconductor substrate with at least one device layer and one insulating layer; b) creating at least one porous region in the device layer by means of metal-assisted etching; c) surrounding the porous region with trenches extending down to the insulating layer; and d) contacting the at least one porous region in order to form a semiconductor capacitor electrode in the device layer.

Description

DOPPELSCHICHTKONDENSATOR MIT PORÖSER HALBLEITER-KONDENSATORELEKTRODE  DOUBLE LAYER CAPACITOR WITH POROUS SEMICONDUCTOR CAPACITOR ELECTRODE
Die Erfindung betrifft ein Halbleiter-Bauteil, ausgebildet auf einem zumindest eine Device-Schicht und eine Isolator-Schicht aufweisenden Halbleiter-Substrat sowie ein Verfahren zu dessen Herstellung. The invention relates to a semiconductor component, formed on a semiconductor substrate having at least one device layer and an insulator layer, and a method for the production thereof.
Elektrochemische Doppelschichtkondensatoren kommen vielfach zum Einsatz, wenn große Leistungsund Energiemengen aufgenommen bzw. abgegeben werden müssen. In dieser Eigenschaft schließen sie die Lücke zwischen herkömmlichen Kondensatoren (hohe Leistungsdichte) und Batterien (hohe Energiedichte). In einfachster Ausführung bestehen sie aus zwei gegenüberliegenden Elektroden (meist Kohlenstoff), welche durch eine ionendurchlässige Membran elektrisch gegeneinander isoliert sind. Zwischen die Elektroden wird ein Elektrolyt eingebracht, dessen Ionen bei anliegender Spannung an der Elektrodenoberfläche eine elektrochemische Doppelschicht ausbilden und auf diese Weise Ladungen speichern. Vorrangige potentielle Einsatzgebiete mit besonderer wirtschaftlicher Bedeutung liegen beispielsweise in den Bereichen Elektrotraktion (Kraftfahrzeuge) und Telekommunikation. Hierbei kann durch Abfangen von Leistungsspitzen die Nennleistung der primären Energiequelle reduziert, die Lebensdauer und Reichweite verlängert und damit die Wirtschaftlichkeit des Gesamtsystems wesentlich verbessert werden. Von besonderem Interesse für die vorliegende Erfindung sind weiters energieautarke Sensorknoten auf Chipebene. Electrochemical double-layer capacitors are often used when large amounts of power and energy have to be absorbed or released. In this capacity, they close the gap between conventional capacitors (high power density) and batteries (high energy density). In the simplest version, they consist of two opposite electrodes (usually carbon), which are electrically insulated from each other by an ion-permeable membrane. An electrolyte is introduced between the electrodes whose ions form an electrochemical double layer when voltage is applied to the electrode surface and in this way store charges. Priority potential applications with particular economic importance are, for example, in the fields of electric traction (motor vehicles) and telecommunications. This can be reduced by intercepting power peaks, the rated power of the primary energy source, the life and range extended and thus the efficiency of the overall system can be significantly improved. Of particular interest to the present invention are further energy self-sufficient sensor nodes on the chip level.
Wesentlich für die Funktion von elektrochemischen Doppelschichtkondensatoren ist die potentialgesteuerte Ausbildung von Helmholtz-Doppelschichten, was die Verwendung von Elektroden aus Kohlenstoff, wie z.B. Aktivekohlematerialien, die zwar eine extrem hoch poröse Oberfläche aufweisen, ungünstig erscheinen lässt, da die Verteilung der Porengrößen bei diesen Materialien sehr breit ist und sich mitunter bis in den Bereich von ungefähr 1 nm erstrecken. Da typische Helmholtz- Schichtdicken selbst bei bis zu 5 nm liegen, kann bei diesem Elektrodenmaterial die Helmholtz- Speicherschicht nicht vollständig an der tatsächlich vorhandenen Oberfläche ausgebildet werden. Essential to the function of electrochemical double-layer capacitors is the potential-controlled formation of Helmholtz bilayers, which makes it possible to use carbon electrodes such as carbon nanotubes. Active carbon materials, which have an extremely high porous surface, appear unfavorable, since the distribution of the pore sizes in these materials is very broad and sometimes extending to the range of about 1 nm. Since typical Helmholtz layer thicknesses are even up to 5 nm, the Helmholtz storage layer can not be completely formed on the surface actually present in this electrode material.
Aus diesem Grund wurden in der DE 199 48 742 Cl bereits Elektroden aus elektrisch leitfähigen oder halbleitenden, nanostrukturierten Elementen vorgeschlagen. Dieses Dokument betrifft insbesondere die Herstellung einer solchen Elektrode durch elektrochemisches Wachstum diskreter, nadeiförmiger Elemente auf einer entsprechend strukturierten Oberfläche, wobei diese Elektroden bzw. Kondensatoren in weiterer Folge in Chips oder Leiterplatten integriert werden müssen. For this reason, DE 199 48 742 C1 has already proposed electrodes made of electrically conductive or semiconducting nanostructured elements. This document relates in particular to the production of such an electrode by electrochemical growth of discrete, needle-shaped elements on a correspondingly structured surface, wherein these electrodes or capacitors must subsequently be integrated into chips or printed circuit boards.
Bei modernen Chiparchitekturen kommen zunehmend Halbleiter-Substrate zum Einsatz, die unter dem Begriff„Silicon On Insulator" (SOI) bekannt sind. Bei diesen Substanzen wird eine Isolatorschicht, beispielsweise aus Siliziumoxid in das Substrat eingebracht, um nur eine relativ dünne Schicht für die Herstellung von Schaltkreisen zu nutzen. Die Schaltkreise befinden sich hierbei in der sogenannten „Device Layer" oder„Device-Schicht" die durch die Isolatorschicht vom„Bulk" bzw. dem„Handle Wafer" getrennt ist. SOI-Substrate sind hinsichtlich kürzerer Schaltzeiten und einer geringeren Leistungsaufnahme, besonders bezüglich der Leckströme, vorteilhaft. In modern chip architectures, semiconductor substrates are increasingly being used, which are known by the term "silicon on insulator" (SOI), in which an insulator layer, for example of silicon oxide, is introduced into the substrate to form only a relatively thin layer for the silicon Making use of circuits. The circuits are located in the so-called "device layer" or "device layer" which is separated by the insulator layer from the "bulk" or the "handle wafer". SOI substrates are advantageous in terms of shorter switching times and lower power consumption, especially with regard to leakage currents.
Die bisher bekannten nanostrukturierten Halbleiter-Kondensatorelektroden sind nur mit relativ großem Aufwand auf SOI-Substraten integrierbar, weshalb es Aufgabe der vorliegenden Erfindung ist, derartige Elektroden bzw. Kondensatoren einfacher und kostengünstiger auf SOI-Substraten anzuordnen. The hitherto known nanostructured semiconductor capacitor electrodes can be integrated with SOI substrates only with relatively great effort, which is why the object of the present invention is to arrange such electrodes or capacitors more simply and less costly on SOI substrates.
Ausgehend von einem Halbleiterbauteil der eingangs genannten Art ist die Erfindung daher gekennzeichnet durch zumindest eine Halbleiter-Kondensatorelektrode in der Device-Schicht in Form eines aus der Device-Schicht gebildeten, porösen Bereichs. Mit anderen Worten liegt die Erfindung daher darin, Halbleiter-Kondensatorelektroden nicht als separate Bauteile zu fertigen, die in der Folge in SOI-Chips integriert werden müssen, sondern diese Elektroden bereits auf einem Halbleitersubstrat, das in der Folge zu einem Chip weiterverarbeitet werden kann, auszubilden. Auf diese Weise kann die Herstellung von Doppelschichtkondensatoren auf Halbleiterbasis in den Herstellungsprozess von Chips integriert werden, was die kostengünstige Fertigung von Hochleistungselementen in hoher Stückzahl bei relativ geringem Fertigungsaufwand ermöglicht. Starting from a semiconductor component of the type mentioned in the introduction, the invention is therefore characterized by at least one semiconductor capacitor electrode in the device layer in the form of a porous region formed from the device layer. In other words, the invention is therefore not to manufacture semiconductor capacitor electrodes as separate components, which subsequently have to be integrated into SOI chips, but these electrodes already on a semiconductor substrate, which can be further processed into a chip in sequence, train. In this way, the fabrication of semiconductor-based double-layer capacitors can be integrated into the manufacturing process of chips, which enables the cost-effective production of high-performance elements in large quantities with relatively low production costs.
Um das volle Potential von SOI-Substrate hinsichtlich der Vermeidung von Leckströmen ausschöpfen zu können, ist die Erfindung bevorzugt dahingehend weitergebildet, dass der die zumindest eine Kondensatorelektrode bildende poröse Bereich in der Ebene der Device-Schicht von bis auf die Isolator-Schicht reichenden Trenches umgeben ist. Im technischen Gebiet der Mikroelektronik sind Trenches als Ausnehmungen oder Einschnitte in Halbleitersubstrat bekannt, die sich wie Gräben durch die Substratschicht, in diesem Fall durch die Device-Schicht ziehen. Bei dieser bevorzugten Variante der vorliegenden Erfindung umgeben die genannten Trenches die zumindest eine Kondensatorelektrode bzw. den porösen Bereich somit wie ein umlaufender Graben, der bis auf die Isolierschicht des Halbleitersubstrats hinabreicht, wodurch eine vollständige elektrische Isolierung des porösen Bereichs, der als Halbleiter-Kondensatorelektrode dient, erreicht wird. Ein Halbleiterbauteil gemäß dieser bevorzugten Ausführungsform gestattet daher die Speicherung großer Ladungsmengen in einem elektrochemischen Doppelschichtkondensator, ohne dass bedeutende Leckströme, d.h. Der Verlust von Ladungen in das Substrat, in Kauf genommen werden müssen. In order to be able to exploit the full potential of SOI substrates with regard to the prevention of leakage currents, the invention is preferably developed in such a way that the porous region forming the at least one capacitor electrode in the plane of the device layer is surrounded by trenches extending to the insulator layer is. In the technical field of microelectronics, trenches are known as recesses or cuts in a semiconductor substrate which, like trenches, pass through the substrate layer, in this case through the device layer. In this preferred variant of the present invention, said trenches thus surround the at least one capacitor electrode and the porous region, respectively, like a circumferential trench extending down to the insulating layer of the semiconductor substrate, thereby providing complete electrical isolation of the porous region serving as a semiconductor capacitor electrode , is achieved. A semiconductor device according to this preferred embodiment therefore allows the storage of large amounts of charge in an electrochemical double-layer capacitor without significant leakage currents, i. The loss of charges in the substrate, must be accepted.
Gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung ist es vorgesehen, dass ein Kondensator von einer Halbleiter-Kondensatorelektrode in der Device-Schicht und einer auf dieser angeordneten weiteren Halbleiter-Kondensatorelektrode gebildet ist. Bei einer solchen Bauform eines elektrochemischen Doppelschichtkondensators auf Halbleiterbasis ist somit lediglich eine der beiden Halbleiter-Kondensatorelektroden einstückig mit dem Halbleitersubstrat ausgebildet und die weitere Kondensatorelektrode stellt einen separaten Bauteil dar, der mit weiter unten beschriebenen Methoden auf dem Halbleitersubstrat festgelegt und entsprechend kontaktiert wird. According to a preferred embodiment of the present invention, it is provided that a capacitor is formed by a semiconductor capacitor electrode in the device layer and a further semiconductor capacitor electrode arranged thereon. In such a design of a Thus, only one of the two semiconductor capacitor electrodes integrally formed with the semiconductor substrate and the further capacitor electrode is a separate component, which is determined by methods described below on the semiconductor substrate and contacted accordingly.
Im Gegensatz zu der soeben beschriebenen Ausführungsform der vorliegenden Erfindung wird eine besonders hohe Integration von Halbleiterbauteilen erreicht, wenn ein Kondensator von zwei in der Device-Schicht nebeneinander angeordneten Halbleiter-Kondensatorelektroden gebildet ist, wie dies einer bevorzugten Variante der vorliegenden Erfindung entspricht. Eine solche Geometrie ist hinsichtlich der dynamischen Eigenschaften wie Lade- und Entladezeiten des elektrochemischen Doppelschichtkondensators günstig, da die Diffusion des Elektrolyten zwischen den Leiterplatten erleichtert wird und sich keine gegenüber dem restlichen Elektrolytsystem abgeschlossen Abschnitte in den porösen Bereichen bilden, weshalb die gesamte Oberfläche der Porosität als Elektrodenoberfläche zur Verfügung steht. In contrast to the embodiment of the present invention just described, a particularly high degree of integration of semiconductor components is achieved if a capacitor of two semiconductor capacitor electrodes arranged side by side in the device layer is formed, as corresponds to a preferred variant of the present invention. Such a geometry is favorable in terms of dynamic properties such as charging and discharging times of the electrochemical double-layer capacitor, since diffusion of the electrolyte between the circuit boards is facilitated and no portions are formed in the porous regions with respect to the remaining electrolyte system, and therefore the entire surface area of the porosity Electrode surface is available.
Bei der soeben beschriebenen Variante der vorliegenden Erfindung muss klarerweise eine Abdeckung der porösen Bereiche, die die Halbleiter-Kondensatorelektroden bilden, erfolgen, wobei es gemäß einer bevorzugten Ausführungsform bevorzugt ist, dass die nebeneinander angeordneten Halbleiter- Kondensatorelektroden von einem dielektrischen Material, insbesondere von einem Glaswafer bedeckt sind. Clearly, in the just described variant of the present invention, it is necessary to cover the porous regions forming the semiconductor capacitor electrodes, wherein according to a preferred embodiment it is preferred that the semiconductor capacitor electrodes arranged next to each other be made of a dielectric material, in particular a glass wafer are covered.
Gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung weist das Halbleiter-Substrat eine Device-Schicht-Dicke von 5 μιη - 15 um, insbesondere 10 um auf. Bei dieser Device-Schicht- Dicke wurden im Versuch die bestmöglichen Ergebnisse erzielt. According to a preferred embodiment of the present invention, the semiconductor substrate has a device layer thickness of 5 μm - 15 μm, in particular 10 μm. At this device layer thickness, the best possible results were achieved in the experiment.
Weiters ist es besonders bevorzugt, wenn das Halbleiter-Substrat eine Isolator-Schicht-Dicke von 0,5 μιη - 2 um, insbesondere 1 μιη, aufweist. Furthermore, it is particularly preferred if the semiconductor substrate has an insulator layer thickness of 0.5 μm - 2 μm, in particular 1 μm.
Weiters bevorzugt weist das Halbleiter-Substrat eine Handle-Wafer-Dicke von 300 μιη - 700 μιη, insbesondere 550 μιη, auf. Further preferably, the semiconductor substrate has a handle wafer thickness of 300 μιη - 700 μιη, in particular 550 μιη, on.
Ein bevorzugter Abstand der Kondensatorelektroden ist gegeben, wenn die Kondensatorelektroden 5 μιη - 10 μτη voneinander beabstandet sind. A preferred distance of the capacitor electrodes is given when the capacitor electrodes 5 μιη - 10 μτη are spaced apart.
Während die vorliegende Erfindung prinzipiell auf eine Reihe von unterschiedlichen Halbleitersubstraten, wie beispielsweise Siliziumkarbid, Galliumarsenid oder Indiumverbindungen oder auf eine Kombination aus einer einkristallinen Siliziumschicht auf einem dielektrischen Substrat, so wie es beispielsweise die Silicon On Saphire (SOS)-Technologie ermöglicht, anwendbar ist, ist es bevorzugt, wenn das Halbleiter-Substrat von einem Silizium auf Isolator (Silicon-On-Insulator)-Wafer gebildet ist. While the present invention is in principle applicable to a number of different semiconductor substrates, such as silicon carbide, gallium arsenide, or indium compounds, or to a combination of a single crystal silicon layer on a dielectric substrate, For example, as silicon on sapphire (SOS) technology allows, it is preferred that the semiconductor substrate be formed by a silicon on insulator (silicon on insulator) wafer.
Im einfachsten Fall ist der zumindest eine poröse Bereich von röhrenartigen Hohlräumen gebildet, die sich von der Oberfläche der Device-Schicht zur Isolator-Schicht erstrecken. Wenn beide Halbleiter- Kondensatorelektroden in der Device-Schicht nebeneinander angeordnet sind, ist es jedoch bevorzugt, wenn die porösen Bereiche von parallel zur Oberfläche der Device-Schicht verlaufenden, röhrenartigen Hohlräumen gebildet sind. Eine solche Geometrie ist hinsichtlich der dynamischen Eigenschaften wie Lade- und Entladezeiten des elektrochemischen Doppelschichtkondensators günstig, da die Diffusion des Elektrolyten zwischen den Leiterplatten erleichtert wird und sich keine gegenüber dem restlichen Elektrolytsystem abgeschlossen Abschnitte in den porösen Bereichen bilden, weshalb die gesamte Oberfläche der Porosität als Elektrodenoberfläche zur Verfügung steht. In the simplest case, the at least one porous region is formed by tubular cavities which extend from the surface of the device layer to the insulator layer. If both semiconductor capacitor electrodes are arranged side by side in the device layer, it is preferred, however, if the porous regions are formed by tubular cavities extending parallel to the surface of the device layer. Such a geometry is favorable in terms of dynamic properties such as charging and discharging times of the electrochemical double-layer capacitor, since diffusion of the electrolyte between the circuit boards is facilitated and no portions are formed in the porous regions with respect to the remaining electrolyte system, and therefore the entire surface area of the porosity Electrode surface is available.
Das erfindungsgemäße Verfahren zur Herstellung eines Halbleiterbauteils gemäß oben angeführten Beschreibung umfasst die folgenden Schritte: a) Bereitstellen eines Halbleiter-Substrats mit zumindest einer Device-Schicht und einer Isolator-Schicht The method according to the invention for the production of a semiconductor component according to the above description comprises the following steps: a) Provision of a semiconductor substrate with at least one device layer and one insulator layer
b) Herstellen zumindest eines porösen Bereichs in der Device-Schicht durch Metallunterstütztes Ätzen  b) producing at least one porous region in the device layer by metal assisted etching
c) Umgeben des porösen Bereichs mit bis auf die Isolator-Schicht reichenden Trenches d) Ankontaktieren des zumindest einen porösen Bereichs zur Ausbildung einer Halbleiter- Kondensatorelektrode in der Device-Schicht.  c) surrounding the porous region with trenches reaching down to the insulator layer d) contacting the at least one porous region to form a semiconductor capacitor electrode in the device layer.
Metall-unterstütztes Ätzen (metal assisted etching) ist im Stand der Technik bekannt und insbesondere in dem Artikel "Metal Assisted Chemical Edging of Silicone: A Review" aus Advanced Materials (Adv. Mater. 2011, 23, 285 - 308) detailliert beschrieben. Prinzipiell werden bei diesem Verfahren Metallpartikel in der Größe der gewünschten Porositäten auf die Oberfläche eines Halbleiters, wie beispielsweise Silizium, aufgebracht und das so behandelte Halbleitersubstrat in eine wässrige Ätzlösung, enthaltend ein Oxidationsmittel, wie beispielsweise H2O2, und eine Säure, insbesondere HF (Flusssäure), verbracht. Die Metallpartikel wirken als Katalysatoren, wobei insbesondere Silber besonders bevorzugt ist. Beim Ätzvorgang bilden sich an den Metallpartikeln Kathoden aus, an denen Wasserstoffperoxid (H2O2) reduziert wird. Als Folge dessen werden die Siliziumatome unter dem Metall oxidiert und durch die Säure herausgelöst. Auf diese Weise sinken die Metallpartikel mehr oder weniger senkrecht in Bezug auf die Oberfläche in den Halbleiter ein und bilden entsprechende Kanäle aus. Abhängig von der Geometrie der Metallpartikel können diese im Halbleiter auch unterschiedliche Bahnen beschreiben, wobei sich diese jedoch im Wesentlichen entlang der Gitterstruktur des Siliziums orientieren. Metal-assisted etching is well known in the art and is described in detail in particular in the article "Metal Assisted Chemical Edging of Silicone: A Review" from Advanced Materials (Adv. Mater., 2011, 23, 285-308). In principle, in this process, metal particles of the size of the desired porosities are applied to the surface of a semiconductor, such as silicon, and the semiconductor substrate thus treated is coated in an aqueous etching solution containing an oxidizing agent, such as H 2 O 2 , and an acid, in particular HF (Hydrofluoric acid), spent. The metal particles act as catalysts, with silver being particularly preferred. In the etching process, cathodes form on the metal particles, at which hydrogen peroxide (H2O2) is reduced. As a result, the silicon atoms under the metal are oxidized and dissolved out by the acid. In this way, the metal particles sink more or less perpendicular with respect to the surface in the semiconductor and form corresponding channels. Depending on the geometry of the metal particles, these can also be different in the semiconductor Describe webs, but these are oriented substantially along the lattice structure of the silicon.
Gemäß einer bevorzugten Ausfuhrungsform der vorliegenden Erfindung umfasst das Metallunterstützte Ätzen den Einsatz einer wässrigen Lösung von 5.0M - 5.5M, insbesondere 5.3M Flusssäure und 0.15M - 0.2M, Insbesondere 0.18M H202. According to a preferred embodiment of the present invention, the metal-assisted etching comprises the use of an aqueous solution of 5.0M-5.5M, in particular 5.3M hydrofluoric acid and 0.15M-0.2M, in particular 0.18MH 2 0 2 .
Die Erfindung wird nachfolgend anhand eines in der Zeichnung dargestellten Ausführungsbeispiels erläutert. In dieser zeigen The invention will be explained with reference to an embodiment shown in the drawing. In this show
Figur 1 eine schematische Schnittdarstellung einer ersten Ausführungsform gemäß der vorliegenden Erfindung, FIG. 1 is a schematic sectional view of a first embodiment according to the present invention,
Figur 2 eine schematische Schnittdarstellung einer alternativen Ausführungsform gemäß der vorliegenden Erfindung,  FIG. 2 shows a schematic sectional view of an alternative embodiment according to the present invention,
Figur 3 eine rasterlektronenmikroskopische Aufnahme eines Schnitts durch einen erfindungsgemäßen porösen Bereich in einer Device-Schicht eines SOI-Substrat,  FIG. 3 shows a scanning electron micrograph of a section through a porous region according to the invention in a device layer of an SOI substrate,
Figur 4 eine rasterelektronenmikroskopische Aufnahme einer Draufsicht auf einen erfindungsgemäßen porösen Bereich in einer Device-Schicht eines SOI-Substrats und  FIG. 4 shows a scanning electron micrograph of a plan view of a porous region according to the invention in a device layer of an SOI substrate and FIG
Figur 5 eine schematische Schnittdarstellung einer bevorzugten Ausführungsform der vorliegenden Erfindung bei der der zumindest eine poröse Bereich von parallel zur Oberfläche der Device-Schicht verlaufenden, röhrenartigen Hohlräumen gebildet ist. Figure 5 is a schematic sectional view of a preferred embodiment of the present invention in which at least one porous region is formed by tube-like cavities extending parallel to the surface of the device layer.
In Figur 1 ist mit 1 ein SOI-Substrat bezeichnet, welches sich im Wesentlichen aus einer Device- Schicht 2, einer Isolierschicht 3 und einem Handle-Wafer 4 aufbaut. Die Isolierschicht 3 stellt eine elektrische Isolierung zwischen der Device-Schicht 2 und dem Handle-Wafer bzw. dem Bulk 4 sicher. Eine erste Halbleiter-Kondensatorelektrode in Form eines aus der Device-Schicht 2 gebildeten porösen Bereichs 6 ist mit 5 bezeichnet, wobei die Halbleiter-Kondensatorelektrode 5 mittels eines Bonddrahtes 7 mit einem nicht näher dargestellten Schaltkreis auf dem SOI-Substrat 1 elektrisch verbunden ist. Gegenüber der ersten Halbleiter-Kondensatorelektrode 5 ist eine zweite Halbleiter- Kondensatorelektrode 8 angeordnet, wobei ein Hohlraum 9 ausgebildet wird, der mit einem geeigneten Elektrolyten befüllt ist. Die Befüllung kann beispielsweise über ein Füllloch 10 erfolgen, welches mit einem Glasdeckel 11 verschließbar ist. Die zweite Halbleiter-Kondensatorelektrode 8 ist wiederum über einen Bonddraht 12 mit entsprechenden Strukturen auf dem SOI-Substrat verbunden. Die erste Halbleiter-Kondensatorelektrode 5 und die zweite Halbleiter-Kondensatorelektrode 8 bilden zusammen mit dem Elektrolyten im Hohlraum 9 einen elektrochemischen Doppelschichtkondensator aus. Trenches 13 umgeben die Halbleiter-Kondensatorelektrode 5 in der Device-Schicht 2 und isolieren somit den elektrochemischen Doppelschichtkondensator vom Rest der Device-Schicht 2. Bei der alternativen Ausführungsform gemäß Figur 2 sind sowohl die erst Halbleiter- Kondensatorelektrode 5 als auch die zweite Halbleiter-Kondensatorelektrode 8 nebeneinander in der Device-Schicht 2 angeordnet und eine Abdeckung 14 aus dielektrischen Material wie beispielsweise aus einem Glaswafer stellt einen abgeschlossenen Hohlraum 9 für den Elektrolyten her. Ein weiterer Trench 15, der bis auf die Isolierschicht 3 hinabreicht, sorgt für eine Trennung der beiden Halbleiter- Kondensatorelektroden 5 und 8. In FIG. 1, 1 designates an SOI substrate which essentially consists of a device layer 2, an insulating layer 3 and a handle wafer 4. The insulating layer 3 ensures electrical insulation between the device layer 2 and the handle wafer or the bulk 4. A first semiconductor capacitor electrode in the form of a porous region 6 formed from the device layer 2 is denoted by 5, wherein the semiconductor capacitor electrode 5 is electrically connected by means of a bonding wire 7 with a circuit not shown in detail on the SOI substrate 1. Opposite the first semiconductor capacitor electrode 5, a second semiconductor capacitor electrode 8 is arranged, wherein a cavity 9 is formed, which is filled with a suitable electrolyte. The filling can take place, for example, via a filling hole 10, which can be closed with a glass lid 11. The second semiconductor capacitor electrode 8 is in turn connected via a bonding wire 12 to corresponding structures on the SOI substrate. The first semiconductor capacitor electrode 5 and the second semiconductor capacitor electrode 8 form, together with the electrolyte in the cavity 9, an electrochemical double-layer capacitor. Trenches 13 surround the semiconductor capacitor electrode 5 in the device layer 2 and thus isolate the electrochemical double-layer capacitor from the remainder of the device layer 2. In the alternative embodiment according to FIG. 2, both the first semiconductor capacitor electrode 5 and the second semiconductor capacitor electrode 8 are arranged side by side in the device layer 2 and a cover 14 of dielectric material, such as a glass wafer, forms a closed cavity 9 for the device Electrolytes. Another trench 15, which reaches down to the insulating layer 3, provides for a separation of the two semiconductor capacitor electrodes 5 and 8.
Die Aufnahme gemäß Figur 3 zeigt, dass der poröse Bereich 6 in Form von im Wesentlichen geradlinig verlaufenden Porositäten gebildet ist, welche beim Metall-unterstützten chemischen Ätzverfahren gebildet werden. The photograph according to FIG. 3 shows that the porous region 6 is formed in the form of essentially rectilinear porosities, which are formed in the metal-assisted chemical etching process.
In Figur 4 ist zu erkennen, dass im porösen Bereich 6 die Porositäten in der Device-Schicht 2 eine enorm hohe Elektrodenoberfläche für die Ausbildung von Helmholtz-Doppelschichten zur Verfügung, wodurch besonders hohe Kapazitäten des Kondensators erzielt werden können. In FIG. 4 it can be seen that in the porous region 6, the porosities in the device layer 2 have an enormously high electrode surface area for the formation of Helmholtz double layers, whereby particularly high capacitances of the capacitor can be achieved.
Bei der in Figur 5 dargestellten erfindungsgemäßen Ausführungsform sind die porösen Bereiche von parallel zur Oberfläche der Device-Schicht verlaufenden, röhrenartigen Hohlräumen gebildet, was gegenüber den in den Figuren 1 und 2 dargestellten Varianten der vorliegenden Erfindung hinsichtlich der dynamischen Eigenschaften des elektrochemischen Doppelschichtkondensators und vor allem hinsichtlich der Lade- und Entladezeiten von Vorteil ist. In the embodiment according to the invention shown in FIG. 5, the porous regions are formed by tube-like cavities extending parallel to the surface of the device layer, which differs from the variants of the present invention shown in FIGS. 1 and 2 with regard to the dynamic properties of the electrochemical double-layer capacitor and above all in terms of loading and unloading is beneficial.

Claims

ANSPRÜCHE
1. Halbleiter-Bauteil, ausgebildet auf einem zumindest eine Device-Schicht und eine Isolator- Schicht aufweisenden Halbleiter-Substrat, gekennzeichnet durch zumindest eine Halbleiter- Kondensatorelektrode in der Device-Schicht in Form eines aus der Device-Schicht gebildeten porösen Bereichs. 1. semiconductor component, formed on a at least one device layer and an insulator layer having semiconductor substrate, characterized by at least one semiconductor capacitor electrode in the device layer in the form of a porous layer formed from the device layer.
2. Halbleiter-Bauteil nach Anspruch 1, dadurch gekennzeichnet, dass der die zumindest eine Kondensatorelektrode bildende poröse Bereich in der Ebene der Device-Schicht von bis auf die Isolator-Schicht reichenden Trenches umgeben ist. 2. Semiconductor component according to claim 1, characterized in that the at least one capacitor electrode forming porous region in the plane of the device layer is surrounded by extending to the insulator layer trenches.
3. Halbleiter-Bauteil nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass ein Kondensator von einer Halbleiter-Kondensatorelektrode in der Device-Schicht und einer auf dieser angeordneten weiteren Halbleiter-Kondensatorelektrode gebildet ist. 3. Semiconductor component according to claim 1 or 2, characterized in that a capacitor is formed by a semiconductor capacitor electrode in the device layer and a further semiconductor capacitor electrode arranged thereon.
4. Halbleiter-Bauteil nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass ein Kondensator von zwei in der Device-Schicht nebeneinander angeordneten Halbleiter-Kondensatorelektroden gebildet ist. 4. Semiconductor component according to claim 1 or 2, characterized in that a capacitor of two in the device layer adjacent to each other arranged semiconductor capacitor electrodes is formed.
5. Halbleiter-Bauteil nach Anspruch 4, dadurch gekennzeichnet, dass die nebeneinander angeordneten Halbleiter-Kondensatorelektroden von einem dielektrischen Material, insbesondere von einem Glaswafer bedeckt sind. 5. Semiconductor component according to claim 4, characterized in that the juxtaposed semiconductor capacitor electrodes are covered by a dielectric material, in particular by a glass wafer.
6. Halbleiter-Bauteil nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass das Halbleiter-Substrat eine Device-Schicht-Dicke von 5 μιη - 15 μιη, insbesondere 10 μιη, aufweist. 6. Semiconductor component according to one of claims 1 to 5, characterized in that the semiconductor substrate has a device layer thickness of 5 μιη - 15 μιη, in particular 10 μιη having.
7. Halbleiter-Bauteil nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass das Halbleiter-Substrat eine Isolator- Schicht-Dicke von 0,5 um - 2 μιη, insbesondere 1 um, aufweist. 7. Semiconductor component according to one of claims 1 to 6, characterized in that the semiconductor substrate has an insulator layer thickness of 0.5 μm - 2 μm, in particular 1 μm.
8. Halbleiter-Bauteil nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass das Halbleiter-Substrat eine Handle-Wafer-Dicke von 300 um - 700 μιη, insbesondere 550 μιη, aufweist. 8. Semiconductor component according to one of claims 1 to 7, characterized in that the semiconductor substrate has a handle wafer thickness of 300 to - 700 μιη, in particular 550 μιη.
9. Halbleiter-Bauteil nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass die Kondensatorelektroden 5 um - 10 μιη voneinander beabstandet sind. 9. Semiconductor component according to one of claims 1 to 8, characterized in that the capacitor electrodes 5 by -10 μιη are spaced apart.
10. Halbleiter-Bauteil nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, dass das Halbleiter-Substrat von einem Silizium auf Isolator (Silicon-On-Insulator)-Wafer gebildet ist. 10. Semiconductor component according to one of claims 1 to 9, characterized in that the semiconductor substrate is formed by a silicon on insulator (silicon-on-insulator) wafer.
11. Halbleiter-Bauteil nach einem der Ansprüche 4 bis 10, dadurch gekennzeichnet, dass die porösen Bereiche von parallel zur Oberfläche der Device-Schicht verlaufenden, röhrenartigen Hohlräumen gebildet sind. 11. Semiconductor component according to one of claims 4 to 10, characterized in that the porous regions are formed by parallel to the surface of the device layer extending, tubular cavities.
12. Verfahren zu Herstellung eines Halbleiter-Bauteils nach einem der Ansprüche 1 bis 11, gekennzeichnet durch folgende Schritte: a) Bereitstellen eines Halbleiter-Substrats mit zumindest einer Device-Schicht und einer Isolator-Schicht 12. A method for producing a semiconductor device according to any one of claims 1 to 11, characterized by the following steps: a) providing a semiconductor substrate having at least one device layer and an insulator layer
b) Herstellen zumindest eines porösen Bereichs in der Device-Schicht durch Metallunterstütztes Ätzen  b) producing at least one porous region in the device layer by metal assisted etching
c) Umgeben des porösen Bereichs mit bis auf die Isolator-Schicht reichenden Trenches d) Ankontaktieren des zumindest einen porösen Bereichs zur Ausbildung einer Halbleiter- Kondensatorelektrode in der Device-Schicht.  c) surrounding the porous region with trenches reaching down to the insulator layer d) contacting the at least one porous region to form a semiconductor capacitor electrode in the device layer.
13. Verfahren nach Anspruch 11, dadurch gekennzeichnet, dass das Metall-unterstützte Ätzen den Einsatz einer wässrigen Lösung von 5.0M - 5.5M, insbesondere 5.3M Flusssäure und 0.15M - 0.2M, Insbesondere 0.18M H2O2 umfasst. 13. The method according to claim 11, characterized in that the metal-assisted etching comprises the use of an aqueous solution of 5.0M-5.5M, in particular 5.3M hydrofluoric acid and 0.15M-0.2M, in particular 0.18M H2O2.
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