WO2015166494A1

WO2015166494A1 - An address intercepting integrated circuit for write-once operation of a storage

Info

Publication number: WO2015166494A1
Application number: PCT/IL2015/050444
Authority: WO
Inventors: Raphael Cohen; Michael David FISZER
Original assignee: Raphael Cohen; Fiszer Michael David
Priority date: 2014-04-29
Filing date: 2015-04-29
Publication date: 2015-11-05

Abstract

An address intercepting integrated circuit (AIIC) for write-once operation of a storage receives read and write instructions to be conveyed to a storage. The AIIC receives instructions including a first address and content to write to the first address. The AIIC selects a second address which was not previously used and stores the data in the second address of the storage. A map of the storage is retained to translate the first write address to the second write address. Upon receiving a Read instruction, the AIIC retrieves the content according to the second address, which was established when the content was written.

Description

AN ADDRESS INTERCEPTING INTEGRATED CIRCUIT FOR WRITE-ONCE

OPERATION OF A STORAGE

CROSS REFERENCE TO RELATED APPLICATIONS

[001] This application claims the benefit of U.S. Provisional Application No. 61/985,493 filed on April 29, 2014 and U.S. Provisional Application No. 61/985,494 filed April 29, 2014, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

[002] The invention generally relates to secure storages and particularly to write-once secure storages.

BACKGROUND

[003] In the digital world, storing data is a crucial element of many businesses and individuals. Data corruption is a serious concern as more and more information is stored digitally. Hackers, criminals and the like often target storages to acquire the information within, or corrupt data and in some cases hold the data hostage for a ransom. Additionally, constant system changes, software upgrades and the like may cause a computer to stop normal functionality.

[004] It would be advantageous to provide a system and method to allow continuous points of restoration to a storage, especially if the continuous restoration points are incorruptible.

SUMMARY

[005] A summary of several example embodiments of the disclosure follows. This summary is provided for the convenience of the reader to provide a basic

understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated

embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments" may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[006] Certain embodiments disclosed herein include a method for writing to a write- once storage using an address intercepting integrated circuit (AIIC). The method comprises receiving at least an instruction by the AIIC to write content to a storage, the storage coupled to the AIIC, and the at least an instruction comprising at least a first address and content to be written on the storage at the first address; selecting a second address of the storage, the second address not previously written to; writing the content to the second address in the storage; and storing, in map of the storage, the first address and the second address.

[007] Certain embodiments disclosed herein also include an address-intercepting integrated circuit (AIIC) for writing to a storage. The AIIC comprises: a northbound input/output (I/O) circuit , the northbound I/O circuit operative for connecting to a bus for receiving data and instructions; a storage I/O circuit, the storage I/O circuit operative for connecting to at least a storage; and a controller configured to cause the AIIC to: receive at least an instruction by the AIIC to write content to a storage, the storage coupled to the AIIC, and the at least an instruction comprising at least a first address and content to be written on the storage at the first address; select a second address of the storage, the second address not previously written to; write the content to the second address in the storage; and store, in a map of the storage, the first address and the second address.

[008] Certain embodiments disclosed herein include a method for reading from a storage using an AIIC. The method comprises: receiving at least an instruction to read content from a storage by an AIIC, the instruction comprising at least a first address; translating the first address by the AIIC to a second address, using a map of the storage; and reading the content from the second address of the storage.

[009] Certain embodiments disclosed herein also include an address-intercepting integrated circuit (AIIC) for reading from a write-once storage. The AIIC comprises: a northbound input/output (I/O) circuit, the northbound I/O circuit operative for coupling to a bus for receiving data and instructions; a storage I/O circuit, the storage I/O circuit operative for connecting to at least a storage; and a controller configured to cause the AIIC to: receive at least an instruction to read content from a storage, the at least an instruction comprising at least a first address; translate the first address to a second address, using a map of the storage; and reading the content from the second address of the storage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The subject matter disclosed is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a schematic illustration of an AIIC in accordance with an embodiment.

[0012] Figure 2 is a schematic illustration of a system utilizing an AIIC implemented according to an embodiment.

[0013] Figure 3 is a flowchart of a method for writing to storage using an address intercepting integrated circuit (IC) according to an embodiment.

[0014] Figure 4 is a flowchart of a method for reading from a storage using an address- intercepting IC (AIIC) according to an embodiment.

[0015] Figure 5 is a schematic illustration of a system utilizing an AIIC implemented according to another embodiment.

[0016] Figure 6 is a flowchart of a method for writing to a storage connected to an address intercepting integrated circuit (IC) for data backup according to an

embodiment.

[0017] Figure 7 is a flowchart of a method for writing to a storage connected to an AIIC for data backup according to another embodiment.

[0018] Figure 8 is a flowchart of a method for reading data backup from a storage connected to an AIIC according to an embodiment.

[0019] Figure 9 is a memory graph of a map respective of a first address, in accordance with an embodiment. DETAILED DESCRIPTION

[0020] It is important to note that the embodiments disclosed herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed embodiments. Moreover, some statements may apply to some features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

[0021] An address intercepting integrated circuit (AIIC) for write-once operation of a storage receives read and write instructions to be conveyed to a storage. The AIIC receives instructions including a first address and content to write to the first address. The AIIC selects a second address which was not previously used and stores the data in the second address of the storage. A map of the storage is retained to translate the first write address to the second write address. Upon receiving a Read instruction, the AIIC retrieves the content according to the second address, which was established when the content was written.

[0022] Fig. 1 is a non-limiting exemplary schematic illustration of an address intercepting integrated circuit (AIIC) 100 in accordance with an embodiment. The AIIC 100 includes a northbound input/output (I/O) circuit 1 10 and a storage I/O circuit 120. The northbound I/O circuit 1 10 is operative to be communicatively connected to a bus of a chipset. The storage I/O circuit is 120 is operative to be communicatively connected to at least a storage. In certain embodiments, the storage I/O circuit 120 may be communicatively connected to a plurality of storage devices. In some embodiments, the plurality of storage devices may form together a single logical storage. AIIC 100 further includes a controller 130. Controller 130 is operative for controlling the AIIC 1 10. In certain embodiments, controller 130 is configured to implement the methods described in further detail herein. The controller 130 may be implemented, for example, as a microcontroller or a state machine. The microcontroller is connected to a memory 140. The memory 140 may be used as a buffer for storing at least an address and content to be written to the address. In certain embodiments the memory 140 may be used for storing instructions therein that when executed by the microcontroller cause the AIIC 100 to perform the methods as described in more detail herein. In certain embodiments, the controller 130 may be implemented separately from the AIIC 1 10, and is communicatively connected thereto.

[0023] Fig. 2 is an exemplary and non-limiting schematic illustration of a system 200 utilizing an AIIC 100 implemented according to an embodiment. The system 200 includes at least one processing element 210, for example, a central processing unit (CPU). The processing element 210 is coupled via a bus 205 to a memory 220. The memory may be used as a working scratch pad for the processing element 210, a temporary storage, and others, as the case may be. The memory may comprise of volatile memory such as, but not limited to random access memory (RAM), or nonvolatile memory (NVM), such as, but not limited to, Flash memory. The processing element 210 may be coupled to an input 250. The processing element 210 may be further coupled with a northbound I/O circuit 1 10 of an AIIC 100. The storage I/O circuit 120 of the AIIC 100 may be coupled with storage 230. Storage 230 may include storage portion 235, designated a write-once storage portion. In certain embodiments a controller 130 of the AIIC 100 is configured to perform the methods as detailed herein.

[0024] In an embodiment, the processing element 210 may comprise, or be a

component of, a larger processing unit implemented with one or more processors. The one or more processors may be implemented with any combination of general- purpose microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate array (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable entities that can perform calculations or other manipulations of information.

[0025] The processing element 210 and/or the memory 220 may also include machine- readable media for storing software. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code). The instructions, when executed by the one or more processors, cause the processing system to perform the various functions described herein.

[0026] Fig. 3 is a non-limiting exemplary flowchart 300 of a method for writing to storage using an address intercepting integrated circuit (IC) according to an embodiment. In S310 instructions are received by the address intercepting IC (Al IC) to write content to a storage, the storage connected to the Al IC. The instructions may be sent from an operating system (OS). The instructions include at least a first address and content to be written on the storage at the first address. The Al IC may be for example, an

Application-specific IC (ASIC), Field-programmable gate array (FPGA), intellectual property core (IP Core) and the like. In S320 the AIIC selects a second address from the storage, the second address being an address which was not previously written to. In some embodiments, the second address may be the next available address on the storage which appears after the first address and has not been written to previously. In other embodiments it may be an address in a pre-allocated and distinct logical area of the storage. In S330 the content is written to the second address in the storage. If the first address has not been previously written to, then the second address is identical to the first address. In S340 the first address and second address are stored in a map of the storage. In some embodiments, the map of the storage is stored on the storage itself. The method ensures each address in the storage is written to only once, while being transparent to an operating system communicating instructions to the storage. In certain embodiments the AIIC may designate a portion of the addresses of the storage to be write-once, and others may be written to multiple times. In this case a check is performed to determine if the address is a write-once address or a regular address. If the address is a write-once address, the method continues as detailed above, otherwise the address is written to and read from as usual. The storage map is always stored on the write-once portion of the storage to ensure integrity of the map.

[0027] Fig. 4 is a non-limiting exemplary flowchart 400 of a method for reading from a storage using an AIIC according to an embodiment. In 410 instructions are received by an AIIC to read content from a write-once storage, the instructions including at least a first address. In S420 the first address is translated by the AIIC to a second address, using a map of the storage. In S430 the content of the second address is read from the storage. By sending content read from the second address when a request was made to read the content from a first address, the operation of the AIIC is transparent to the OS requesting the content. Additionally, the content on the storage is

incorruptible as it cannot be erased once it is written.

[0028] A system and method perform backup of a storage with continuous points of retrieval using an address intercepting circuit (AIIC). In one embodiment, the AIIC receives instructions to write new content to a first address. If the first address contains old content, a second address which data has not been written to is selected, and the old content is written to the second address. The new content is written to the first address, and the second address is mapped so as to enable the restoration to an earlier point of update of the storage. Mapping may include use of a last-in first-out (LIFO) memory. In some embodiments a timestamp respective of each data write is also or alternatively used. In certain embodiments, when the AIIC receives an instruction to read content from a first address, it is translated to a second address, and translation may be respective of a timestamp.

[0029] Fig. 5 is an exemplary and non-limiting schematic illustration of a system 500 utilizing an AIIC 100 implemented according to an embodiment. The system 500 includes at least one processing element 510, for example, a central processing unit (CPU). The processing element 510 is coupled via a bus 505 to a memory 520. The memory may be used as a working scratch pad for the processing element 510, a temporary storage, and others, as the case may be. The memory may comprise of volatile memory such as, but not limited to random access memory (RAM), or nonvolatile memory (NVM), such as, but not limited to, Flash memory. The processing element 510 may be coupled to an input 550. The processing element 510 may be further coupled with a northbound I/O circuit 1 10 of an AIIC 100. The storage I/O circuit 120 of the AIIC 100 may be coupled with storage 530. Storage 530 may include storage portion 535, designated a write-once storage portion. In some embodiments, the AIIC 100 may be connected to a plurality of storages. The plurality of storages may be multiple logical units or a single logical unit. In certain embodiments a controller 130 of the AIIC 100 is configured to perform the methods as detailed herein. [0030] In an embodiment, the processing element 510 may comprise, or be a component of, a larger processing unit implemented with one or more processors. The one or more processors may be implemented with any combination of general- purpose microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate array (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable entities that can perform calculations or other manipulations of information.

[0031] The processing element 510 and/or the memory 520 may also include machine- readable media for storing software. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code). The instructions, when executed by the one or more processors, cause the processing system to perform the various functions described herein.

[0032] Fig. 6 is a non-limiting exemplary flowchart 600 of a method for writing to storage connected to an address intercepting integrated circuit (IC) for data backup according to an embodiment. In S610 instructions are received by the address intercepting IC (Al IC) to write content to a storage, the storage connected to the AIIC. The

instructions may be sent from an operating system (OS). The instructions include at least a first address and content to be written on the storage at the first address. The AIIC may be for example, an Application-specific IC (ASIC), Field-programmable gate array (FPGA), intellectual property core (IP Core) and the like. In S620 the AIIC selects a second address from the storage, the second address being an address which was not previously written to. In some embodiments, the second address may be the next available address on the storage which appears after the first address and has not been written to previously. In other embodiments it may be an address in a pre-allocated and distinct logical area of the storage. In S630 the content is written to the second address in the storage. If the first address has not been previously written to, then the second address is identical to the first address. In S640 the second address is mapped so as to enable the restoration to an earlier point of update of the storage. Mapping may include storing the second address in a last-in-first-out (LIFO) memory. Each address of the storage may be assigned a LIFO memory. The number of available points of restoration corresponds to the depth (i.e. number of elements) of the LIFO memory. The LIFO memory may be implemented, for example, as a stack. In other embodiments, mapping may be performed using a linked list. The map may further include a timestamp respective of the received instructions. In some

embodiments, the map is implemented on a portion of the storage. The method ensures each address in the storage is written to only once, while being transparent to an operating system communicating instructions to the storage. In certain

embodiments the AIIC may designate a portion of the addresses of the storage to be write-once, and others may be written to multiple times. In this case a check is performed to determine if the address is a write-once address or a regular address. If the address is a write-once address, the method continues as detailed above, otherwise the address is written to and read from as usual. The storage map is always stored on the write-once portion of the storage to ensure integrity of the map.

033] Fig. 7 is a non-limiting exemplary flowchart of a method for writing to a storage connected to an AIIC for data backup according to another embodiment. In 710 instructions are received by the AIIC to write new content to a storage, the storage connected to the AIIC. The instructions may be sent from an operating system (OS). The instructions include at least a first address and content to be written on the storage at the first address. The AIIC may be for example, an Application-specific IC (ASIC), Field-programmable gate array (FPGA), intellectual property core (IP Core) and the like. In S720 a check is performed to determine if the first address was previously written to and contains old content. If the address was previously written to and contains old content, execution continues at S730, otherwise execution continues at S750. In S730 the AIIC selects a second address, the second address being an address which was not previously written to. In some embodiments, the second address may be any of: the next available address on the storage which appears after the first address, an address in a pre-allocated and distinct logical area of the storage, or an available address of a distinct physical storage. In S740 the AIIC writes the old content from the first address to the second address. In S750 the new content is written to the first address. In S760 the second address is mapped so as to enable the restoration to an earlier point of update of the storage. Mapping may include storing the second address in a last-in-first-out (LIFO) memory. Each address of the storage may be assigned a LIFO memory. The number of available points of restoration corresponds to the depth (i.e. number of elements) of the LIFO memory. The LIFO memory may be implemented, for example, as a stack. In other embodiments, mapping may be performed using a linked list. The map may further include a timestamp respective of the received instructions. In some embodiments, the map is implemented on a portion of the storage..

[0034] Fig. 8 is a non-limiting exemplary flowchart 800 of a method for reading data backup from a storage connected to an AIIC according to an embodiment. In 810 instructions are received by an AIIC to read content from a write-once storage, the instructions including at least a first address. The instruction may further include a timestamp. In S820 the first address is translated by the AIIC to a second address, using a map. If a timestamp is included, the first address may be translated to a second address respective further of the timestamp. For example, the first address may be mapped to a second address in a first timestamp. The first address may be mapped to a third address in a second timestamp. In S830 the content of the second address is read from the storage.

[0035] Fig. 9 is a non-limiting exemplary memory graph 900 of a map respective of a first address A1 . The first address A1 is mapped to a plurality of second addresses. The plurality of second addresses are stored in a map, to enable the restoration to an earlier point of update of the storage. When an instruction is received by an AIIC to read content from the first address A1 , the first address is translated to a second address. The last second address in the map is A12, therefore the content is read from address A12. In certain embodiments, each element in the map further includes a timestamp corresponding to the received instruction to write content. The instruction may be, for example, to read content from first address A1 with a timestamp of T2. The first address A1 is translated respective of the timestamp T2 to the second address A6. Content is then read from the second address A6. [0036] By sending content read from the second address when a request was made to read the content from a first address, the operation of the AIIC is transparent to the OS requesting the content. Additionally, the content on the storage is incorruptible as it cannot be erased once it is written. This allows for continuous retrieval points of the data stored thereon, allowing for a continuous backup of the content written to the storage.

[0037] The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer readable medium consisting of parts, or of certain devices and/or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units ("CPUs"), a memory, and input/output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit. Furthermore, a non- transitory computer readable medium is any computer readable medium except for a transitory propagating signal.

[0038] All examples and conditional language recited herein are intended for

pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof.

Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Claims

CLAIMS What is claimed is:

1 . A computerized method for writing to a write-once storage using an address intercepting integrated circuit (AIIC), the method comprising:

receiving at least an instruction by the AIIC to write content to a storage, the storage coupled to the AIIC, and the at least an instruction comprising at least a first address and content to be written on the storage at the first address;

selecting a second address of the storage, the second address not previously written to;

writing the content to the second address in the storage; and

storing, in map of the storage, the first address and the second address.

2. The computerized method of claim 1 , wherein the AIIC is any of: application- specific integrated circuit (ASIC), field-programmable gate array (FPGA), or intellectual property core (IP Core).

3. The computerized method of claim 1 , wherein the second address is the next available address which has not been previously written to on the storage after the first address.

4. The computerized method of claim 1 , wherein the first address has not been previously written to, and the first address and the second address are identical.

5. The computerized method of claim 1 , wherein the map of the storage is stored on one of: the storage, a memory of the AIIC.

6. The computerized method of claim 1 , wherein the AIIC is used only on a portion of the addresses of the storage.

7. An address-intercepting integrated circuit (AIIC) for writing to a storage, the AIIC comprising:

a northbound input/output (I/O) circuit , the northbound I/O circuit operative for connecting to a bus for receiving data and instructions;

a storage I/O circuit, the storage I/O circuit operative for connecting to at least a storage; and

a controller configured to cause the AIIC to: receive at least an instruction by the AIIC to write content to a storage, the storage coupled to the AIIC, and the at least an instruction comprising at least a first address and content to be written on the storage at the first address; select a second address of the storage, the second address not previously written to; write the content to the second address in the storage; and store, in a map of the storage, the first address and the second address.

8. The AIIC of claim 7, wherein the AIIC is implemented as any of: application- specific integrated circuit (ASIC), field-programmable gate array (FPGA), or intellectual property core (IP Core).

9. The AIIC of claim 7, wherein the second address is the next available address which has not been previously written to on the storage after the first address.

10. The AIIC of claim 7, wherein the first address has not been previously written to, and the first address and the second address are identical.

1 1. The AIIC of claim 7, wherein the map of the storage is stored on one of: the storage, a memory of the AIIC.

12. The AIIC of claim 7, wherein the AIIC is used only on a portion of the addresses of the storage.

13. A computerized method for reading from a storage using an AIIC, the method comprising: receiving at least an instruction to read content from a storage by an AIIC, the instruction comprising at least a first address;

translating the first address by the AIIC to a second address, using a map of the storage; and

reading the content from the second address of the storage.

14. The computerized method of claim 13, wherein the map of the storage is stored on one of: the storage, a memory of the AIIC.

15. The computerized method of claim 13, wherein the first address is identical to the second address.

16. The computerized method of claim 13, wherein a portion of the storage is a write- once storage and a portion is not, further comprising:

determining if the first address is of the write-once portion; and;

performing the method of claim 13 only if the first address is of the write-once portion.

17. The computerized method of claim 13, wherein the AIIC is any of: ASIC, FPGA, or IP Core.

18. An address-intercepting integrated circuit (AIIC) for reading from a write-once storage, the AIIC comprising:

a northbound input/output (I/O) circuit, the northbound I/O circuit operative for coupling to a bus for receiving data and instructions;

a controller configured to cause the AIIC to: receive at least an instruction to read content from a storage, the at least an instruction comprising at least a first address; translate the first address to a second address, using a map of the storage; and reading the content from the second address of the storage.

19. The AI IC of claim 18, wherein the storage map is stored on one of: the storage, a memory of the AI IC.

20. The AI IC of claim 18, wherein the first address is identical to the second address.

21 . The AI IC of claim 18, wherein a portion of the storage is a write-once storage and a portion is not and the controller is further configured to cause the AIIC to: determine if the first address is of the write-once portion; and perform the method of claim 18 only if the first address is of the write-once portion.

22. The AI IC of claim 18, wherein the AI IC is any of: ASIC, FPGA, or IP Core.