WO2016081363A1

WO2016081363A1 - A system-on-chip on a semiconductor-on-insulator wafer and a method of manufacturing

Info

Publication number: WO2016081363A1
Application number: PCT/US2015/060871
Authority: WO
Inventors: Srikanth Kommu; Horacio Josue MENDEZ; Igor Peidous
Original assignee: Sunedison Semiconductor Limited
Priority date: 2014-11-18
Filing date: 2015-11-16
Publication date: 2016-05-26

Abstract

A method of preparing a semiconductor-on-insulator (e.g., silicon-on-insulator) structure, and more particularly a method for producing an integrated circuit device on a semiconductor-on-insulator structure is provided. The method comprises forming multiple integrated circuit device types on a semiconductor-on-insulator structure in different regions of the device layer. The integrate circuit device types include a module of radiofrequency devices and a module of CMOS devices.

Description

A SYSTEM-ON-CHIP ON A SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 62/081,356 filed on 18 November 2014, the entire disclosure of which is hereby incorporated by reference in its entirety.

THE FIELD OF THE INVENTION

[0002] The present invention generally relates to the field of semiconductor wafer and integrated circuit device manufacture. More specifically, the present invention relates to a method for forming a semiconductor-on-insulator (e.g., silicon-on-insulator) structure, and more particularly to a method for producing a system on a chip on a semiconductor-on-insulator structure.

BACKGROUND OF THE INVENTION

[0003] Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, or gallium arsenide.

[0004] Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor-on-insulator, and more specifically, a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between 0.01 and 20 micrometers thick, such as between 0.05 and 20 micrometers thick. In general, composite layer structures, such as silicon- on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, followed by a thermal treatment to strengthen the bond.

[0005] After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. See, e.g., U.S. Pat. No. 5, 189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and costly, wastes one of the substrates, and generally does not have suitable thickness uniformity for layers thinner than a few microns.

[0006] Another common method of achieving layer transfer utilizes a hydrogen implant followed by thermally induced layer splitting. Particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds deposited on the wafer during the implantation process.

[0007] The front surface of the donor wafer is then bonded to a handle wafer to form a bonded wafer through a hydrophilic bonding process. Prior to bonding, the donor wafer and/or handle wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation, which activation process renders the surfaces of one or both of the donor water and handle wafer hydrophilic. The wafers are then pressed together, and a bond is formed there between. This bond is relatively weak, and must be strengthened before further processing can occur.

[0008] In some processes, the hydrophilic bond between the donor wafer and handle wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between approximately 300°C and 500°C. In some processes, wafer bonding may occur at high temperatures, such as between approximately 800°C and 1100°C. The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thus solidifying the bond between the donor wafer and the handle wafer. Concurrently with the heating or annealing of the bonded wafer, the particles earlier implanted in the donor wafer weaken the cleave plane.

[0009] A portion of the donor wafer is then separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an SOI wafer.

[0010] According to other methods, the bonded pair may instead be subjected to an elevated temperature over a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the elevated temperature causes initiation and propagation of a crack along the cleave plane, thus separating a portion of the donor wafer. This method allows for better uniformity of the transferred layer and allows recycle of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500°C.

[001 1] The use of high resistivity semiconductor-on-insulator (e.g., silicon-on- insulator) wafers for RF related devices such as antenna switches offers benefits over traditional substrates in terms of cost and integration. To reduce parasitic power loss and minimize harmonic distortion inherent when using conductive substrates for high frequency applications it is necessary, but not sufficient, to use substrate wafers with a high resistivity. Accordingly, the resistivity of the handle wafer for an RF device is generally greater than about 500 Ohm-cm. With reference now to FIG. 1, a silicon on insulator structure 2 comprising a very high resistivity silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device layer 10. Such a substrate is prone to formation of high conductivity charge inversion or accumulation layers 12 at the BOX/handle interface causing generation of free carriers (electrons or holes), which reduce the effective resistivity of the substrate and give rise to parasitic power losses and device nonlinearity when the devices are operated at RF frequencies. These

inversion/accumulation layers can be due to BOX fixed charge, oxide trapped charge, interface trapped charge, and even DC bias applied to the devices themselves.

[0012] A method is required therefore to trap the charge in any induced inversion or accumulation layers so that the high resistivity of the substrate is maintained even in the very near surface region. It is known that charge trapping layers (CTL) between the high resistivity handle substrates and the buried oxide (BOX) may improve the performance of RF devices fabricated using SOI wafers. A number of methods have been suggested to form these high interface trap layers. For example, with reference now to FIG. 2, one method of creating a semiconductor-on-insulator structure 20 (e.g., a silicon-on-insulator, or SOI) with a CTL for RF device applications is based on depositing an undoped polycrystalline silicon film 28 on a silicon substrate having high resistivity 22 and then forming a stack of oxide 24 and top silicon layer 26 on it. A polycrystalline silicon layer 28 acts as a high defectivity layer between the silicon substrate 22 and the buried oxide layer 24. See FIG. 2, which depicts a polycrystalline silicon film for use as a charge trapping layer 28 between a high resistivity substrate 22 and the buried oxide layer 24 in a silicon-on-insulator structure 20. An alternative method is the implantation of heavy ions to create a near surface damage layer. Devices, such as radiofrequency devices, are built in the top silicon layer 26.

[0013] It has been shown in academic studies that the polycrystalline silicon layer in between the oxide and the substrate improves the device isolation, decreases transmission line losses and reduces harmonic distortions. See, for example: H. S. Gamble, et al."Low-loss CPW lines on surface stabilized high resistivity silicon," Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet and J. -P. Raskin, "Enhanced high resistivity SOI wafers for RF applications," IEEE Intl. SOI Conf, pp. 46-47, 2004; D. Lederer and J. -P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity," IEEE Electron Device Letters, vol. 26, no. 1 1, pp.805-807, 2005; D. Lederer, B. Aspar, C. Laghae and J. -P. Raskin, "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate," IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Kerret al. "Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer", Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008.

SUMMARY OF THE INVENTION

[0014] Briefly, the present invention is directed to an integrated circuit device comprising: a single crystal silicon handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 Ohm- cm; a charge trapping layer in interfacial contact with the front surface layer of the single crystal silicon handle substrate, the charge trapping layer comprising one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; a dielectric layer in interfacial contact with the charge trapping layer; and a single crystal silicon device layer in interfacial contact with the dielectric layer, the single crystal silicon device layer comprising a module of radiofrequency devices and a module of complementary metal-oxide semiconductor devices.

[0015] The present invention is further directed to an integrated circuit device comprising: a single crystal silicon handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 Ohm- cm; a charge trapping layer in interfacial contact with the front surface layer of the single crystal silicon handle substrate, the charge trapping layer comprising one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; a dielectric layer in interfacial contact with the charge trapping layer; a first single crystal silicon device layer comprising a module of radiofrequency devices; and a second single crystal silicon device layer comprising a module of complementary metal-oxide semiconductor devices, wherein one of the first single crystal silicon device layer and the second single crystal silicon device layer is in interfacial contact with the dielectric layer.

[0016] The present invention is still further directed to a method of preparing an integrated circuit device, the method comprising: forming a charge trapping layer on a front surface layer of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, a bulk single crystal silicon region, and the central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of at least 100 Ohm-cm, and the charge trapping layer comprises one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; forming a buried oxide layer, wherein the buried oxide layer is in interfacial contact with the charge trapping layer; forming a single crystal silicon device layer in interfacial contact with the buried oxide layer, wherein the buried oxide layer is positioned between the charge trapping layer and the single crystal silicon device layer; forming a module of radiofrequency devices in a first region of the single crystal silicon device layer; and forming a module of complementary metal-oxide

semiconductor devices in a second region of the single crystal silicon device layer.

[0017] The present invention is still further directed to a method of preparing an integrated circuit device, the method comprising: forming a charge trapping layer on a front surface layer of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, a bulk single crystal silicon region, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of at least 100 Ohm-cm, and the charge trapping layer comprises one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; forming a buried oxide layer and a first single crystal silicon device layer, wherein the first single crystal silicon device layer is derived from a first single crystal silicon donor substrate and further wherein the buried oxide layer is in interfacial contact with the charge trapping layer and is positioned between the charge trapping layer and the silicon crystal silicon device layer; bonding a second single crystal silicon donor substrate to the first single crystal silicon device layer, wherein the second single crystal silicon donor substrate comprises two major, generally parallel surfaces, one of which is a front surface of the second single crystal silicon donor substrate and the other of which is a back surface of the second single crystal silicon donor substrate, a circumferential edge joining the front and back surfaces of the second single crystal silicon donor substrate, a bulk region of the second single crystal silicon donor substrate, and a central plane of the second single crystal silicon donor substrate between the front and back surfaces of the second single crystal silicon donor substrate, and further wherein the front surface of the second single crystal silicon donor substrate comprises a silicon dioxide layer and the bulk region of the second single crystal silicon donor substrate comprises a cleave plane; cleaving the second single crystal silicon donor substrate to thereby form a second single crystal silicon device layer; removing a portion of the second single crystal silicon device layer to thereby expose a portion of the first single crystal silicon device layer; forming a module of radiofrequency devices in the first single crystal silicon device layer; and forming a module of complementary metal- oxide semiconductor devices in the second region of the single crystal silicon device layer.

[0018] Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a depiction of a silicon-on-insulator wafer comprising a high resistivity substrate and a buried oxide layer.

[0020] FIG. 2 is a depiction of a silicon-on-insulator wafer comprising a polycrystalline silicon charge trapping layer between a high resistivity substrate and a buried oxide layer.

[0021] FIG. 3 is a depiction of a silicon-on-insulator wafer comprising a polycrystalline silicon charge trapping layer between a high resistivity substrate and a buried oxide layer. The silicon device layer comprises a module of radiofrequency devices and a module of CMOS devices.

[0022] FIG. 4 is a depiction of a silicon-on-insulator wafer comprising a polycrystalline silicon charge trapping layer between a high resistivity substrate and a buried oxide layer. The first silicon device layer comprises a module of radiofrequency devices, and the second silicon device layer comprises a module of CMOS devices. DETAILED DESCRIPTION OF THE EMBODIMENT(S) OF THE INVENTION

[0023] The present invention is directed to a method for preparing a composite multi-layered structure and the composite multi-layered structure prepared thereby. The composite multi-layered structure is useful as a system-on-chip (SOC) integrated circuit that includes a module of radiofrequency (RF) devices and a module of complementary metal oxide semiconductor (CMOS) logic devices. It has been discovered that a system- on-chip comprising both RF devices and CMOS logic devices improves the functionality of the system and reduces its form factors. The present invention overcomes the difficulty of integrating RF and CMOS logic devices on one structure, which is advantageous since the silicon wafer types needed for RF device fabrication are different from those required for manufacturing logic CMOS devices.

[0024] The present invention provides an implementation of a system-on-chip (SOC) integrated circuit on a semiconductor-on-insulator (SOI, e.g., a silicon-on- insulator) wafer having a special structure that is suitable for manufacturing both RF and logic CMOS devices. In some embodiments, the SOI wafer comprises a substrate, a charge trapping layer, and a single crystal silicon device layer, further wherein the device layer comprises a module of radiofrequency (RF) devices and a module of

complementary metal oxide semiconductor (CMOS) logic devices. In some

embodiments, the SOI wafer comprises a substrate, a charge trapping layer, a first silicon layer on a first insulator layer, and a second silicon layer on a second insulator layer. RF devices are made in the first silicon layer, and CMOS logic devises are formed in the second silicon layer. The charge trapping layer enhances the performance of RF devices. The best performance of CMOS logic devices may be achieved in case of a fully depleted MOSFET architecture realized using the second silicon layer thin enough for being fully depleted at a proper gate bias, while the first silicon layer is utilized for a back body bias of CMOS device channels.

[0025] According to the present invention, a method is provided for producing a high defectivity charge trapping layer on a single crystal semiconductor handle substrate, e.g., a single crystal semiconductor handle wafer. The single crystal semiconductor handle wafer comprising the high defectivity charge trapping layer is useful in the production of a semiconductor-on-insulator (e.g., silicon-on-insulator) structure. According to the present invention, the high defectivity charge trapping layer in the single crystal semiconductor handle wafer is formed at the region near the oxide interface. Advantageously, the method of the present invention provides a highly defective charge trapping layer that is stable against thermal processing, such as subsequent thermal process steps in the production of the semiconductor-on-insulator substrate and device manufacture.

[0026] The substrates for use in the present invention include a semiconductor handle substrate, e.g., a single crystal semiconductor handle wafer and a semiconductor donor substrate, e.g., a single crystal semiconductor donor wafer. The semiconductor device layer in a semiconductor-on-insulator composite structure is derived from the single crystal semiconductor donor wafer. The semiconductor device layer may be transferred onto the semiconductor handle substrate by wafer thinning techniques such as etching a semiconductor donor substrate or by cleaving a semiconductor donor substrate comprising a damage plane. In general, the single crystal semiconductor handle wafer and single crystal semiconductor donor wafer comprise two major, generally parallel surfaces. One of the parallel surfaces is a front surface of the substrate, and the other parallel surface is a back surface of the substrate. The substrates comprise a

circumferential edge joining the front and back surfaces, a bulk region between the front and back surfaces, and a central plane between the front and back surfaces. The substrates additionally comprise an imaginary central axis perpendicular to the central plane and a radial length that extends from the central axis to the circumferential edge. In addition, because semiconductor substrates, e.g., silicon wafers, typically have some total thickness variation (TTV), warp, and bow, the midpoint between every point on the front surface and every point on the back surface may not precisely fall within a plane. As a practical matter, however, the TTV, warp, and bow are typically so slight that to a close approximation the midpoints can be said to fall within an imaginary central plane which is approximately equidistant between the front and back surfaces.

[0027] Prior to any operation as described herein, the front surface and the back surface of the substrate may be substantially identical. A surface is referred to as a "front surface" or a "back surface" merely for convenience and generally to distinguish the surface upon which the operations of method of the present invention are performed. In the context of the present invention, a "front surface" of a single crystal semiconductor handle substrate, e.g., a single crystal silicon handle wafer, refers to the major surface of the substrate that becomes an interior surface of the bonded structure. It is upon this front surface that the charge trapping layer is formed. Accordingly, a "back surface" of a single crystal semiconductor handle substrate, e.g., a handle wafer, refers to the major surface that becomes an exterior surface of the bonded structure. Similarly, a "front surface" of a single crystal semiconductor donor substrate, e.g., a single crystal silicon donor wafer, refers to the major surface of the single crystal semiconductor donor substrate that becomes an interior surface of the bonded structure. The front surface of a single crystal semiconductor donor substrate often comprises a dielectric layer, e.g., a silicon dioxide layer, which forms the buried oxide (BOX) layer in the final structure. A "back surface" of a single crystal semiconductor donor substrate, e.g., a single crystal silicon donor wafer, refers to the major surface that becomes an exterior surface of the bonded structure. Upon completion of conventional bonding and wafer thinning steps, the single crystal semiconductor donor substrate forms the semiconductor device layer of the semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure.

[0028] The single crystal semiconductor handle substrate and the single crystal semiconductor donor substrate may be single crystal semiconductor wafers. In preferred embodiments, the semiconductor wafers comprise a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. The single crystal semiconductor wafers, e.g., the single crystal silicon handle wafer and single crystal silicon donor wafer, of the present invention typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Wafer thicknesses may vary from about 250 micrometers to about 1500 micrometers, such as between about 300 micrometers and about 1000 micrometers, suitably within the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. [0029] In particularly preferred embodiments, the single crystal semiconductor wafers comprise single crystal silicon wafers which have been sliced from a single crystal ingot grown in accordance with conventional Czochralski crystal growing methods or float zone growing methods. Such methods, as well as standard silicon slicing, lapping, etching, and polishing techniques are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, N.Y., 1982 (incorporated herein by reference). Preferably, the wafers are polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O'Mara et al, Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the wafers can be cleaned, for example, in a standard SCI/ SC2 solution. In some embodiments, the single crystal silicon wafers of the present invention are single crystal silicon wafers which have been sliced from a single crystal ingot grown in accordance with conventional Czochralski ("Cz") crystal growing methods, typically having a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. Preferably, both the single crystal silicon handle wafer and the single crystal silicon donor wafer have mirror-polished front surface finishes that are free from surface defects, such as scratches, large particles, etc. Wafer thickness may vary from about 250 micrometers to about 1500 micrometers, such as between about 300 micrometers and about 1000 micrometers, suitably within the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers.

[0030] In some embodiments, the single crystal semiconductor handle substrate and the single crystal semiconductor donor substrate, i.e., single crystal semiconductor handle wafer and single crystal semiconductor donor wafer, comprise interstitial oxygen in concentrations that are generally achieved by the Czochralski-growth method. In some embodiments, the semiconductor wafers comprise oxygen in a concentration between about 4 PPMA and about 18 PPMA. In some embodiments, the semiconductor wafers comprise oxygen in a concentration between about 10 PPMA and about 35 PPMA. Preferably, the single crystal silicon handle wafer comprises oxygen in a concentration of no greater than about 10 ppma. Interstitial oxygen may be measured according to SEMI MF 1188-1105.

[0031] In some embodiments, the semiconductor handle substrate, e.g., a single crystal semiconductor handle substrate, such as a single crystal silicon handle wafer, has a relatively high minimum bulk resistivity. High resistivity wafers are generally sliced from single crystal ingots grown by the Czochralski method or float zone method. Cz- grown silicon wafers may be subjected to a thermal anneal at a temperature ranging from about 600°C to about 1000°C in order to annihilate thermal donors caused by oxygen that are incorporated during crystal growth. In some embodiments, the single crystal semiconductor handle wafer has a minimum bulk resistivity of at least 10 Ohm-cm, at least 100 Ohm-cm, at least about 500 Ohm-cm, at least about 1000 Ohm-cm, or even at least about 3000 Ohm-cm, such as between about 100 Ohm-cm and about 100,000 Ohm- cm, or between about 500 Ohm-cm and about 100,000 Ohm-cm, or between about 1000 Ohm-cm and about 100,000 Ohm-cm, or between about 500 Ohm-cm and about 10,000 Ohm-cm, or between about 750 Ohm-cm and about 10,000 Ohm-cm, between about 1000 Ohm-cm and about 10,000 Ohm-cm, between about 2000 Ohm-cm and about 10,000 Ohm-cm, between about 3000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm cm and about 5,000 Ohm-cm. Methods for preparing high resistivity wafers are known in the art, and such high resistivity wafers may be obtained from commercial suppliers, such as SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMC Electronic Materials, Inc.).

[0032] In some embodiments, the single crystal semiconductor handle wafer surface could be intentionally damaged by a sound blasting process or by a caustic etch. In some embodiments, the front surface of the single crystal semiconductor handle wafer may be oxidized by conventional oxidation methods.

[0033] According to the method of the present invention, semiconductor material is deposited onto the exposed front surface of the single crystal semiconductor handle wafer, such as a single crystal silicon wafer, which may comprise an exposed oxidized front surface layer. Semiconductor material suitable for use in forming a charge trapping layer in a semiconductor-on-insulator device is suitably capable of forming a highly defective layer in the fabricated device. Such materials include polycrystalline semiconductor materials and amorphous semiconductor materials. Materials that may be polycrystalline or amorphous include silicon (Si), silicon germanium (SiGe), silicon doped with carbon (SiC), and germanium (Ge). Polycrystalline silicon denotes a material comprising small silicon crystals having random crystal orientations.

Polycrystalline silicon grains may be as small in size as about 20 nanometers. According to the method of the present invention, the smaller the crystal grain size of

polycrystalline silicon deposited the higher the defectivity in the charge trapping layer. Amorphous silicon comprises a non-crystalline allotropic form of silicon, which lacks short range and long range order. Silicon grains having crystallinity over no more than about 10 nanometers may also be considered essentially amorphous. Silicon germanium comprises an alloy of silicon germanium in any molar ratio of silicon and germanium. Silicon doped with carbon comprises a compound of silicon and carbon, which may vary in molar ratio of silicon and carbon. Preferably, the charge trapping layer has a resistivity at least about 1000 Ohm-cm, or at least about 3000 Ohm-cm, such as between about 1000 Ohm-cm and about 100,000 Ohm-cm, between about 1000 Ohm-cm and about 10,000 Ohm-cm, between about 2000 Ohm-cm and about 10,000 Ohm-cm, between about 3000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm cm and about 5,000 Ohm-cm.

[0034] The material for deposition onto the front surface of the single crystal semiconductor handle wafer to thereby form the charge trapping layer may be deposited by means known in the art. For example, the semiconductor material may be deposited using metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors for LPCVD or PECVD include methyl silane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH₂Ci2), silicon tetrachloride (SiC ), among others. For example, polycrystalline silicon may be deposited onto the surface oxidation layer by pyrolyzing silane (SiH₄) in a temperature range between about 550°C and about 690°C, such as between about 580°C and about 650°C. The chamber pressure may range from about 70 to about 400 mTorr. Amorphous silicon may be deposited by plasma enhanced chemical vapor deposition (PECVD) at temperatures generally ranging between about 75°C and about 300°C. Silicon germanium, particularly amorphous silicon germanium, may be deposited at temperatures up to about 300°C by chemical vapor deposition by including organogermanium compounds, such as isobutylgermane, alkylgermanium trichlorides, and dimethylaminogermanium trichloride. Silicon doped with carbon may be deposited by thermal plasma chemical vapor deposition in epitaxial reactors using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, ethylene, among others. For LPCVD deposition, methylsilane is a particularly preferred precursor since it provides both carbon and silicon. For PECVD deposition, the preferred precursors include silane and methane. In some embodiments, the silicon layer may comprise a carbon concentration of at least about 1% on an atomic basis, such as between about 1% and about 10%.

[0035] In some embodiments, the deposition of the semiconductor material of the charge trapping layer may be temporarily interrupted, at least once and preferably more than once, in order to prepare multiple layers of charge trapping material. The interim surface of the semiconductor material film may be exposed to inert, oxidizing, nitridizing, or passivating atmosphere to thereby poison or passivate the deposited semiconductor material. Stated another way, the method of the present invention may comprise deposition of a multilayer of charge trapping semiconductor material by a cycling process in which semiconductor material is deposited, deposition is interrupted, the layer of semiconductor material is poisoned or passivated, and the next layer of semiconductor material is deposited. In some embodiments, a multilayer may be formed comprising one passivated semiconductor layer and one additional semiconductor layer may be deposited to form the charge trapping layer. In some embodiments, the multilayer comprises more than one passivated semiconductor layer and one additional semiconductor layer in the charge trapping layer. By depositing the charge trapping layer in this way, a multilayer comprising, for example, one or more passivated layers, or two or more passivated layers, such as three or more passivated layers, such as at least four passivated layers, or between four and about 100 passivated layers, or between four and about 60 passivated layers, or between four and about 50 passivated layers, or between four and about 25 passivated layers, or between six and about passivated 20 layers of semiconductor material is deposited onto the handle substrate. A large number of semiconductor layers may be deposited limited in part by throughput demands and by the smallest practical layer thickness that may be deposited, which is currently about 20 nanometers. Each of these layers of semiconductor material is poisoned or passivated such that during the high temperature processes of semiconductor-on-insulator fabrication, crystal grain growth in each layer of the multilayer is limited by the thickness of the passivated multilayer rather than by the thickness of the overall charge trapping layer as in prior art processes. In some embodiments, the semiconductor layers may be passivated by exposing the first semiconductor layer to an atmosphere comprising a nitrogen-containing gas, such as nitrogen, nitrous oxide, ammonia (NH₃), nitrogen plasma, and any combination thereof. In this regard, the atmosphere in which the semiconductor layer is deposited may comprise a nitrogen-containing gas, such as nitrogen, and termination of the deposition process followed by exposure to the gas may be sufficient to form a thin passivation layer over the semiconductor layer. In some embodiments, the chamber may be evacuated of the deposition gas and purged with the nitrogen containing gas in order to effect passivation of the previously deposited semiconductor layer. Exposure to nitrogen may nitride the deposited semiconductor layer, for example, resulting in the formation of a thin layer of silicon nitride of just a few angstroms thickness. Alternative passivation methods may be used. For example, the semiconductor layer may be passivated by exposing the first semiconductor layer to an atmosphere comprising an oxygen containing gas, such as oxygen, ozone, water vapor, or any combination thereof. According to these embodiments, a thin layer of semiconductor oxide may form on the semiconductor layer, the semiconductor oxide being sufficient to passivate the layer. For example, a thin layer of silicon oxide may be formed between each layer of the multilayer. The oxide layer may be only a few angstroms thick. In some embodiment, air, which comprises both nitrogen and oxygen, may be used as the passivated gas. In some embodiments, the semiconductor layers may be passivated by exposing the first semiconductor layer to a liquid selected from the group consisting of water, peroxide (e.g. hydrogen peroxide solution), or SCI solution ( H₃:H₂0₂:H₂0). [0036] The overall thickness of the charge trapping layer comprising multiple passivated semiconductor layers may be between about 0.3 micrometers and about 5 micrometers, such as between about 0.3 micrometers and about 3 micrometers, such as between about 0.3 micrometers and about 2 micrometers or between about 2

micrometers and about 3 micrometers. If a multilayer approach is employed, each layer of the multilayer may be at least about 5 nanometers thick, such as at least about 20 nanometers thick, such as between about 5 and about 1000 nanometers thick, between about 20 and about 1000 nanometers thick, between about 20 and about 500 nanometers thick, or between about 100 and about 500 nanometers thick. Advantageously, the passivation process imparts additional defectivity into the charge trapping layer.

[0037] After deposition of the multilayer comprising passivated semiconductor layers, optionally an oxide film is formed on top of the deposited semiconductor material film. This may be accomplished by means known in the art, such as thermal oxidation (in which some portion of the deposited semiconductor material film will be consumed) and/or CVD oxide deposition. In some embodiments, the charge trapping layer, e.g., polycrystalline film, may be thermally oxidized (in which some portion of the deposited semiconductor material film will be consumed) or the silicon dioxide film may be grown by CVD oxide deposition. In some embodiments, the single crystal semiconductor handle substrate comprising the charge trapping layer may be thermally oxidized in a furnace such as an ASM A400. The temperature may range from 750°C to 1200°C in an oxidizing ambient. The oxidizing ambient atmosphere can be a mixture of inert gas, such as Ar or N₂, and (¾. The oxygen content may vary from 1 to 10 percent, or higher. In some embodiments, the oxidizing ambient atmosphere may be up to 100% (a "dry oxidation"). In an exemplary embodiment, semiconductor handle wafers comprising the charge trapping layer may be loaded into a vertical furnace, such as an A400. The temperature is ramped to the oxidizing temperature with a mixture of 2 and O2. After the desired oxide thickness has been obtained, the O2 is turned off and the furnace temperature is reduced and wafers are unloaded from the furnace. In order to incorporate nitrogen in the interfacial layer to deposit silicon nitride or silicon oxynitride, the atmosphere may comprise nitrogen alone or a combination of oxygen and nitrogen, and the temperature may be increased to a temperature between 1 100°C and 1400°C. An alternative nitrogen source is ammonia. In some embodiments, the handle substrates comprising the charge trapping layers are oxidized to provide an oxide layer on the charge trapping layer of at least about 0.01 micrometers thick, or at least about 0.05 micrometers thick, such as between about 0.05 micrometers and about 4 micrometers, such as between about 0.1 micrometers and about 2 micrometers, or between about 0.2 micrometers and about 0.4 micrometers. The oxidation process additionally oxidizes the back surface of the single crystal semiconductor handle wafer, which advantageously reduces warp and bow potentially caused by the different coefficients of thermal expansion of silicon and silicon dioxide.

[0038] After deposition of the charge trapping layer, and optional oxidation, wafer cleaning is optional. If desired, the wafers can be cleaned, for example, in a standard SCI/ SC2 solution. Additionally, the wafers, particularly, the silicon dioxide layer on the charge trapping layer, may be subjected to chemical mechanical polishing (CMP) to reduce the surface roughness, preferably to the level of RMS 2x2 um2 is less than

about 5 angstroms, wherein root mean squared - 1 ^t" ¹ , the roughness profile contains ordered, equally spaced points along the trace, and y_t is the vertical distance from the mean line to the data point.

[0039] The single crystal semiconductor handle substrate, e.g., a single crystal silicon donor substrate, prepared according to the method described herein to comprise a charge trapping layer, and, optionally, an oxide film, is next bonded a single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, which is prepared according to conventional layer transfer methods. That is, the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, may be subjected to standard process steps including oxidation, implant, and post implant cleaning. Accordingly, a single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, is a material that is conventionally used in preparation of multilayer semiconductor structures, e.g., a single crystal silicon donor wafer, that has been etched and polished and optionally oxidized, is subjected to ion implantation to form a damage layer in the donor substrate. [0040] The single crystal semiconductor donor substrate may be a single crystal semiconductor wafer. In preferred embodiments, the semiconductor wafer comprises a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending upon the desired properties of the final integrated circuit device, the single crystal semiconductor (e.g., silicon) donor wafer may comprise a dopant selected from the group consisting of boron, arsenic, and phosphorus. The resistivity of the single crystal semiconductor (e.g., silicon) donor wafer may range from 1 to 50 Ohm-cm, typically, from 5 to 25 Ohm-cm. The single crystal semiconductor donor wafer may be subjected to standard process steps including oxidation, implant, and post implant cleaning. Accordingly, a semiconductor donor substrate, such as a single crystal semiconductor wafer of a material that is

conventionally used in preparation of multilayer semiconductor structures, e.g., a single crystal silicon donor wafer, that has been etched and polished and optionally oxidized, is subjected to ion implantation to form a damage layer in the donor substrate.

[0041] In some embodiments, the semiconductor donor substrate, e.g., a single crystal silicon donor substrate, comprises a dielectric layer. Suitable dielectric layers may comprise a material selected from among silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof. In some embodiments, the dielectric layer comprises an oxide layer having a thickness of at least about 10 nanometer thick, such as between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, or between about 100 nanometers and about 800 nanometers, such as about 600 nanometers.

[0042] In some embodiments, the front surface of the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, may be thermally oxidized (in which some portion of the semiconductor material will be consumed) or a silicon dioxide film may be grown by CVD oxide deposition. In some embodiments, the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor wafer, may be thermally oxidized in a furnace such as an ASM A400. The temperature may range from 750°C to 1200°C in an oxidizing ambient. The oxidizing ambient atmosphere can be a mixture of inert gas, such as Ar or N₂, and (¾. The oxygen content may vary from 1 to 10 percent, or higher. In some embodiments, the oxidizing ambient atmosphere may be up to 100% (a "dry oxidation"). In an exemplary embodiment, semiconductor donor wafers may be loaded into a vertical furnace, such as an A400. The temperature is ramped to the oxidizing temperature with a mixture of 2 and O2. After the desired oxide thickness has been obtained, the O2 is turned off and the furnace temperature is reduced and wafers are unloaded from the furnace. In some embodiments, the donor substrates are oxidized to provide an oxide layer on the front surface layer of at least about 1 nanometer thick, such as between about 0.01

micrometers and about 10 micrometers, such as between about 0.01 micrometers and about 2 micrometers, or between about 0.1 micrometers and about 1 micrometers. The oxidation process additionally oxidizes the back surface of the donor substrate, which advantageously reduces warp and bow potentially caused by the different coefficients of thermal expansion of silicon and silicon dioxide.

[0043] Ion implantation may be carried out in a commercially available instrument, such as an Applied Materials Quantum H. Implanted ions include He, H, H₂, or combinations thereof. Ion implantation is carried out as a density and duration sufficient to form a damage layer in the semiconductor donor substrate. Implant density

12 2 17 2 14 may range from about 10 ions/cm to about 10 ions/cm , such as from about 10 ions/cm² to about 10¹⁷ ions/cm². Implant energies may range from about 1 keV to about 3,000 keV, such as from about 10 keV to about 3,000 keV. The depth of implantation determines the thickness of the single crystal semiconductor device layer in the final SOI structure. In some embodiments it may be desirable to subject the single crystal semiconductor donor wafers, e.g., single crystal silicon donor wafers, to a clean after the implant. In some preferred embodiments, the clean could include a Piranha clean followed by a DI water rinse and SC1/SC2 cleans.

[0044] In some embodiments of the present invention, the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, having an ion implant region therein formed by helium ion and/or hydrogen ion implant is annealed at a temperature sufficient to form a thermally activated cleave plane in the single crystal semiconductor donor substrate. An example of a suitable tool might be a simple Box furnace, such as a Blue M model. In some preferred embodiments, the ion implanted single crystal semiconductor donor substrate is annealed at a temperature of from about 200°C to about 350°C, from about 225°C to about 325°C, preferably about 300°C.

Thermal annealing may occur for a duration of from about 2 hours to about 10 hours, such as from about 2 hours to about 8 hours. Thermal annealing within these temperatures ranges is sufficient to form a thermally activated cleave plane. After the thermal anneal to activate the cleave plane, the single crystal semiconductor donor substrate surface is preferably cleaned.

[0045] In some embodiments, the ion-implanted and optionally cleaned and optionally annealed single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, is subjected to oxygen plasma and/or nitrogen plasma surface activation. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as those available from EV Group, such as

EVG®810LT Low Temp Plasma Activation System. The ion-implanted and optionally cleaned single crystal semiconductor donor wafer is loaded into the chamber. The chamber is evacuated and backfilled with (¾ to a pressure less than atmospheric to thereby create the plasma. The single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, is exposed to this plasma for the desired time, which may range from about 1 second to about 120 seconds. Oxygen plasma surface oxidation is performed in order to render the front surface of the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, hydrophilic and amenable to bonding to a single crystal semiconductor handle substrate prepared according to the method described above.

[0046] The hydrophilic front surface layer of the single crystal semiconductor donor substrate, e.g., a single crystal silicon donor substrate, and the front surface of the single crystal semiconductor handle substrate, e.g., single crystal silicon handle substrate, which comprises the charge trapping layer and which is optionally oxidized, are next brought into intimate contact to thereby form a bonded structure. The bonded structure comprises a dielectric layer, e.g., a buried oxide, with a portion of the dielectric layer contributed by the oxidized front surface of the single crystal semiconductor handle substrate and a portion of the dielectric layer contributed by the oxidized front surface of the single crystal semiconductor donor substrate. In some embodiments, the dielectric layer, e.g., buried oxide layer, has a thickness of at least about 10 nanometer thick, such as between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, or between about 100 nanometers and about 800 nanometers, such as about 600 nanometers.

[0047] Since the mechanical bond is relatively weak, the bonded structure is further annealed to solidify the bond between the donor wafer and the handle wafer. In some embodiments of the present invention, the bonded structure is annealed at a temperature sufficient to form a thermally activated cleave plane in the single crystal semiconductor donor substrate. An example of a suitable tool might be a simple Box furnace, such as a Blue M model. In some preferred embodiments, the bonded structure is annealed at a temperature of from about 200°C to about 350°C, from about 225°C to about 325°C, preferably about 300°C. Thermal annealing may occur for a duration of from about 0.5 hours to about 10 hour, preferably a duration of about 2 hours. Thermal annealing within these temperatures ranges is sufficient to form a thermally activated cleave plane. After the thermal anneal to activate the cleave plane, the bonded structure may be cleaved.

[0048] After the thermal anneal, the bond between the single crystal semiconductor donor substrate and the single crystal semiconductor handle substrate is strong enough to initiate layer transfer via cleaving the bonded structure at the cleave plane. Cleaving may occur according to techniques known in the art. In some embodiments, the bonded structure may be placed in a conventional cleave station affixed to stationary suction cups on one side and affixed by additional suction cups on a hinged arm on the other side. A crack is initiated near the suction cup attachment and the movable arm pivots about the hinge cleaving the wafer apart. Cleaving removes a portion of the semiconductor donor wafer, thereby leaving a semiconductor device layer, preferably a silicon device layer, on the semiconductor-on-insulator composite structure. [0049] After cleaving, the cleaved structure may be subjected to a high temperature anneal in order to further strengthen the bond between the transferred device layer and the single crystal semiconductor handle substrate. An example of a suitable tool might be a vertical furnace, such as an ASM A400. In some preferred embodiments, the bonded structure is annealed at a temperature of from about 1000°C to about 1200°C, preferably at about 1000°C. Thermal annealing may occur for a duration of from about 0.5 hours to about 8 hours, preferably a duration of about 4 hours. Thermal annealing within these temperatures ranges is sufficient to strengthen the bond between the transferred device layer and the single crystal semiconductor handle substrate.

[0050] After the cleave and high temperature anneal, the bonded structure may be subjected to a cleaning process designed to remove thin thermal oxide and clean particulates from the surface. In some embodiments, the single crystal semiconductor donor wafer may be brought to the desired thickness and smoothness by subjecting to a vapor phase HC1 etch process in a horizontal flow single wafer epitaxial reactor using ¾ as a carrier gas. In some embodiments, the thickness of the device layer may be between about 1 nanometer and about 100 micrometers, such as between about 10 nanometers and about 50 micrometers. In some embodiments, an epitaxial layer may be deposited on the transferred device layer. The finished SOI wafer comprises the semiconductor handle substrate, the charge trapping layer, the dielectric layer (e.g., buried oxide layer), and the semiconductor device layer, may then be subjected to end of line metrology inspections and cleaned a final time using typical SC1-SC2 process.

[0051] According to the present invention, SOI wafers are obtained with the deposited semiconductor material charge trapping layer embedded underneath of BOX. These substrates are suitable for use in manufacture of system on a chip (SOC) devices comprising a module of radiofrequency devices and a module of complementary metal- oxide semiconductor devices.

[0052] In some embodiments, the present invention is directed to a system on a chip circuit device. With reference now to FIG. 3, the composite layer structure 100 is suitable for use in preparing an system on a chip (SOC) device. In some embodiments, the composite layer structure 100 comprises a single crystal semiconductor (e.g., silicon) handle substrate 102. A single crystal semiconductor (e.g., silicon) handle substrate 102 comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor (e.g., silicon) handle substrate 102and the other of which is a back surface of the single crystal semiconductor (e.g., silicon) handle substrate 102, a circumferential edge joining the front and back surfaces of the single crystal

semiconductor (e.g., silicon) handle substrate 102, and a central plane of the single crystal semiconductor (e.g., silicon) handle substrate 102 between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal semiconductor (e.g., silicon) handle substrate 102has a minimum bulk resistivity of 100 Ohm-cm. The composite layer structure 100 also comprises a charge trapping layer 104 in interfacial contact with the front surface layer of the single crystal semiconductor (e.g., silicon) handle substrate 102. The charge trapping layer 104 comprises one or more semiconductor layers. The one or more semiconductor layers each comprise a polycrystalline structure or an amorphous structure. The polycrystalline structure and the amorphous structure may comprise a material selected from the group consisting of silicon, SiGe, SiC, and Ge. The composite layer structure 100 also comprises a dielectric layer 106 (e.g., the buried oxide layer) in interfacial contact with the charge trapping layer 104. The composite layer structure 100 also comprises a single crystal

semiconductor (e.g., silicon) device layer 108 in interfacial contact with the dielectric layer 106. In some embodiments, the dielectric layer 106 comprises a buried oxide layer having a thickness between about 0.01 micrometers and about 20 micrometers, such as between about 0.1 micrometers and about 10 micrometers, or between about 0.2 micrometers and about 1 micrometers. Depending upon the desired properties of the final integrated circuit device, the single crystal semiconductor (e.g., silicon) device layer 108 comprises a dopant selected from the group consisting of boron, arsenic, and phosphorus. The resistivity of the single crystal silicon device layer 108 may range from 1 to 50 Ohm-cm, typically, from 5 to 25 Ohm-cm.

[0053] According to the method of the present invention, a module of radiofrequency devices 110 and a module of complementary metal-oxide semiconductor devices 112 are fabricated into the single crystal semiconductor (e.g., silicon) device layer 108 to thereby prepare the system on a chip (SOC) integrated circuit device. CMOS fabrication implies process steps to form isolated CMOS elements which may include low power/low voltage NFETs and PFETs (N- and P channel Field Effect Transistors), resistors, and capacitors. Process steps include conventional technology modules of shallow trench isolation (STI) or isolation by local oxidation (LOCOS), Well formation, Gate formation and Source/drain formation. Radio Frequency Integrated circuits may include elements of antennas, RF filters, Low-noise amplifiers, mixers, oscillators, phase-locked loops, frequency synthesizers, analog-to-digital and digital-to- analog converters, and power amplifiers. They are built of power transistors, lumped- element (spiral inductors, interdigitated capacitors) or distributed components (micro- strips) for impedance matching and other elements. Most advanced RF circuits may be fabricated using CMOS device technology compatible with high power applications that implies larger device feature sizes.

[0054] In some embodiments, the present invention is directed to an integrated circuit device. With reference now to FIG. 4, the composite layer structure 200 is suitable for use in preparing an integrated circuit device comprising a single crystal semiconductor (e.g., silicon) handle substrate 202. A single crystal semiconductor (e.g., silicon) handle substrate 202 comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor (e.g., silicon) handle substrate 202 and the other of which is a back surface of the single crystal semiconductor (e.g., silicon) handle substrate 202, a circumferential edge joining the front and back surfaces of the single crystal semiconductor (e.g., silicon) handle substrate 202, and a central plane of the single crystal semiconductor (e.g., silicon) handle substrate 202 between the front and back surfaces of the single crystal semiconductor (e.g., silicon) handle substrate 202. The single crystal semiconductor (e.g., silicon) handle substrate 202 has a minimum bulk resistivity of 100 Ohm-cm. The composite layer structure 200 also comprises a charge trapping layer 204 in interfacial contact with the front surface layer of the single crystal semiconductor (e.g., silicon) handle substrate 202. The charge trapping layer 204 comprises one or more semiconductor layers. The one or more semiconductor layers each comprise a polycrystalline structure or an amorphous structure. The polycrystalline structure and the amorphous structure may comprise a material selected from the group consisting of silicon, SiGe, SiC, and Ge. The composite layer structure 200 also comprises a dielectric layer 206 in interfacial contact with the charge trapping layer 204. The composite layer structure 200 also comprises a first single crystal semiconductor (e.g., silicon) device layer 208 comprising a module of radiofrequency devices 210 and a second single crystal semiconductor (e.g., silicon) device layer 212 comprising a module of complementary metal-oxide semiconductor devices 214. In some embodiments, the dielectric layer 206 comprises a buried oxide layer having a thickness between about 0.01 micrometers and about 20 micrometers, such as between about 0.1 micrometers and about 10 micrometers, or between about 0.2 micrometers and about 1 micrometer. Depending upon the desired properties of the final integrated circuit device, the single crystal semiconductor (e.g., silicon) device layers 208 and 212 comprise dopants selected from the group consisting of boron, arsenic, and phosphorus. The resistivity of the single crystal silicon device layers 208 and 212 may range from 1 to 50 Ohm-cm, typically, from 5 to 25 Ohm-cm.

[0055] In some embodiments, the second single crystal semiconductor (e.g., silicon) device layer 212 may be formed on the structure by bonding the silicon-on- insulator structure having the first single crystal semiconductor (e.g., silicon) device layer 208 to a second single crystal silicon donor substrate having a cleave plane and an outer silicon dioxide layer. According to the method of the present invention, the first single crystal semiconductor (e.g., silicon) device layer 208 comprises a back body bias element 216. FDSOI device architecture allows effective modulation of FET threshold voltage using "back body bias." FET drive current is conventionally controlled by the transistor gate through the gate oxide on the top of FET channel. On the other side of the FET channel, it is in contact with BOX (buried oxide). BOX is uniquely thin in FDSOI structure and acts as a bottom gate oxide. The back body bias is conducted by applying an appropriate voltage to a portion of the substrate underneath FET channel. In the result, the (top) gate voltage at which FET switches from "off to "on" state (threshold voltage) is influenced by the voltage applied from the back side of the channel. The portion of the substrate underneath FET channel - back body bias element - is selectively doped for providing a controlled bias of the FET channel. Selective doping is made using conventional lithography and ion implantation. [0056] The second single crystal semiconductor (e.g., silicon) device layer 212 is fabricated in interfacial contact with an interlayer dielectric layer 218 positioned between the back body bias elements 216 and the second single crystal semiconductor (e.g., silicon) device layer 212. The silicon dioxide layer on the second single crystal silicon donor substrate may have a thickness between about 1 nanometer and about 100 nanometers, such as between about 10 nanometers and about 25 nanometers. This silicon dioxide layer becomes the interlayer dielectric 218 in the final structure. The second single crystal silicon donor substrate bonded to the first single crystal semiconductor (e.g., silicon) device layer 208 is cleaved and/or thinned by the techniques described above. The second single crystal semiconductor (e.g., silicon) device layer 212may have a final thickness between about 1 nanometer and about 50 nanometers, such as between about 5 nanometers and about 15 nanometers. To manufacture the composite layer structure, a sequential bonding and cleaving of two silicon donor substrates on a handle substrate may be used. This results in a formation of a silicon-on- insulator structure comprising a blanket first single crystal semiconductor (e.g., silicon) device layer 208 for RF devices and a blanket second single crystal semiconductor (e.g., silicon) device layer 212 for CMOS devices. Before device fabrication, it may be beneficial to expose those areas of the first single crystal silicon device layer assigned for RF devices. This may be done by selective etch of portions of the second single crystal semiconductor (e.g., silicon) device layer 212 from the top of the first single crystal semiconductor (e.g., silicon) device layer 208 with protecting from etch the areas of the second crystal silicon device layer assigned for CMOS devices by mans of lithography. Either wet or reactive ion etch can be used.

[0057] According to the method of the present invention, a module of radiofrequency devices 210 and a module of complementary metal-oxide semiconductor devices 214 are fabricated into the first single crystal semiconductor (e.g., silicon) device layer 208 and the second single crystal semiconductor (e.g., silicon) device layer 212, respectively, to thereby prepare the system on a chip integrated circuit device. [0058] Having described the invention in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims.

[0059] As various changes could be made in the above compositions and processes without departing from the scope of the invention, it is intended that all matter contained in the above description be interpreted as illustrative and not in a limiting sense.

[0060] When introducing elements of the present invention or the preferred embodiment(s) thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

WHAT TS CLAIMED TS:

1 . An integrated circuit device comprising:

a single crystal silicon handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 Ohm-cm; a charge trapping layer in interfacial contact with the front surface layer of the single crystal silicon handle substrate, the charge trapping layer comprising one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;

a dielectric layer in interfacial contact with the charge trapping layer; and a single crystal silicon device layer in interfacial contact with the dielectric layer, the single crystal silicon device layer comprising a module of radiofrequency devices and a module of complementary metal-oxide semiconductor devices.

2. The integrated circuit device of claim 1 wherein the single crystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

3. The integrated circuit device of claim 2 wherein the single crystal silicon wafer has a bulk resistivity between about 100 Ohm-cm and about 100,000 Ohm-cm.

4. The integrated circuit device of claim 2 wherein the single crystal silicon wafer has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

5. The integrated circuit device of claim 2 wherein the single crystal silicon handle wafer has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm- cm.

6. The integrated circuit device of claim 2 wherein the single crystal silicon handle wafer has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm- cm.

7. The integrated circuit device of claim I wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 5 micrometers.

8. The integrated circuit device of claim 1 wherein the total thickness of the cliarge trapping layer is between about 0.3 micrometers and about 3 micrometers.

9. The integrated circuit device of claim 1 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 2 micrometers.

10. The integrated circuit device of claim 1 wherein the charge trapping layer comprises two or more semiconductor layers, wherein each of the two or more semiconductor layers are passivated.

1 1 . The integrated circuit device of claim 1 wherein the dielectric layer comprises silicon dioxide.

12. The integrated circuit device of claim 1 wherein the dielectric layer has a thickness between about 0.01 micrometers and about 20 micrometers.

13. The integrated circuit device of claim I wherein the dielectric layer has a thickness between about 0.1 micrometers and about 10 micrometers.

14. The integrated circuit device of claim 1 wherein the dielectric layer has a thickness between about 0.2 micrometers and about 1 micrometer.

15. The integrated circuit device of claim I wherein the single crystal silicon device layer comprises a dopant selected from the group consisting of boron, arsenic, and phosphorus.

16. The integrated circuit device of claim I wherein the module of radiofrequency devices comprises a device selected from the group consisting of MOSFETs, Bipolar transistors, resistors, capacitors, inductors, micro-strips, and any combination thereof.

17. The integrated circuit device of claim 1 wherein the module of complementary metal-oxide semiconductor devices comprises a device selected from the group consisting of NFfc s, PFETs, Resistors, Capacitors, and any combination thereof.

18. The integrated circuit device of claim I wherein the module of complementary metal-oxide semiconductor devices comprises a fully depleted

MOSFET.

19. An integrated circuit device comprising:

a dielectric layer in interfacial contact with the charge trapping layer; a first single crystal silicon device layer comprising a module of radiofrequency devices; and

a second single crystal silicon device layer comprising a module of

complementary metal-oxide semiconductor devices,

wherein one of the first single crystal silicon device layer and the second single crystal silicon device layer is in interfacial contact with the dielectric layer.

20. The integrated circuit device of claim 19 wherein the first single crystal silicon device layer is in interfacial contact with the dielectric layer, and the second single crystal silicon device layer is in interfacial contact with the first single crystal silicon device layer.

21. The integrated circuit device of claim 19 wherein the first single crystal silicon device layer is in interfacial contact with the dielectric layer, and the second single crystal silicon device layer is in interfacial contact with an interlayer dielectric layer positioned between the first single crystal silicon device layer and the second single ciystal silicon device layer.

22. The integrated circuit device of claim 19 wherein the first single ciystal silicon device layer is in interfacial contact with the dielectric layer and further comprises a back body bias element, and the second single crystal silicon device layer is in interfacial contact with an interlayer dielectric layer positioned between the back body bias elements and the second single crystal silicon device layer.

23. The integrated circuit device of claim 19 wherein the single ciystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single ciystal silicon ingot grown by the Czochralski method or the float zone method.

24. The integrated circuit device of claim 23 wherein the single ciystal silicon wafer has a bulk resistivity between about 100 Ohm-cm and about 100.000 Ohm-cm.

25. The integrated circuit device of claim 23 wherein the single ciystal silicon wafer has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

26. The integrated circuit device of claim 23 wherein the single crystal silicon handle wafer has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm- cm.

27. The integrated circuit device of claim 19 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 5 micrometers.

28. The integrated circuit device of claim 1 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 3 micrometers.

29. The integrated circuit device of claim 19 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 2 micrometers.

30. The integrated circuit device of claim 19 wherein the charge trapping layer comprises two or more semiconductor layers, wherein each of the two or more semiconductor layers are passivated.

3 1. The integrated circuit device of claim 1 wherein the dielectric layer comprises silicon dioxide.

32. The integrated circuit device of claim 1 wherein the dielectric layer has a thickness between about 0.01 micrometers and about 20 micrometers.

33. The integrated circuit device of claim 1 wherein the dielectric layer has a thickness between about 0.1 micrometers and about 10 micrometers.

34. The integrated circuit device of claim 19 wherein the dielectric layer has a thickness between about 0.2 micrometers and about 1 micrometer.

35. The integrated circuit device of claim 19 wherein the single crystal silicon device layer comprises a dopant selected from the group consisting of boron, arsenic, and phosphorus.

36. The integrated circuit device of claim 1 wherein the module of radiofrequency devices comprises a device selected from the group consisting of MOSFETs, Bipolar transistors, resistors, capacitors, inductors, micro-strips, and any combination thereof.

37. The integrated circuit device of claim 19 wherein the module of complementary metal-oxide semiconductor devices comprises a device selected from the group consisting of NFfc s, PFtTs, Resistors, Capacitors, and any combination thereof.

38. The integrated circuit device of claim 19 wherein the module of complementary metal-oxide semiconductor devices comprises a fully depleted

MOSFET.

39. A method of preparing an integrated circuit device, the method comprising:

forming a charge trapping layer on a front surface layer of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, a bulk single crystal silicon region, and the central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherei the single crystal silicon handle substrate has a minimum bulk resistivity of at least 100 Ohm-cm, and the charge trapping layer comprises one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycry stall ine structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;

forming a buried oxide layer, wherein the buried oxide layer is in interfacial contact with the charge trapping layer;

forming a single crystal silicon device layer in interfacial contact with the buried oxide layer, wherein the buried oxide layer is positioned between the charge trapping layer and the silicon crystal silicon device layer; forming a module of radiofrequency devices in a first region of the single crystal silicon device layer; and

forming a module of complementary metal-oxide semiconductor devices in a second region of the single crystal silicon device layer.

40. The method of claim 39 wherein the single crystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

41 . The method of claim 40 wherein the single crystal silicon wafer has a bulk resistivity between about 100 Ohm-cm and about 100,000 Ohm-cm.

42. The method of claim 40 wherein the single crystal silicon wafer has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

43. The method of claim 40 wherein the single crystal silicon handle wafer has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

44. The method of claim 40 wherein the single crystal silicon handle wafer has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

45. The method of claim 39 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 5 micrometers.

46. The method of claim 39 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 3 micrometers.

47. The method of claim 39 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 2 micrometers.

48. The method of claim 39 wherein the charge trapping layer comprises two or more semiconductor layers, wherein each of the two or more semiconductor layers are passivated.

49. The method of claim 39 wherein the buried oxide layer has a thickness between about 0.01 micrometers and about 20 micrometers.

50. The method of claim 39 wherein the buried oxide la er has a thickness between about 0.1 micrometers and about 10 micrometers.

51. The method of claim 39 wherein the buried oxide layer has a thickness between about 0.2 micrometers and about 1 micrometer.

52. The method of claim 39 wherein the single crystal silicon device layer comprises a dopant selected from the group consisting of boron, arsenic, and phosphorus.

53. The method of claim 39 wherein the module of radiofrequency devices comprises a device selected from the group consisting of MOSFETs, Bipolar transistors, resistors, capacitors, inductors, micro-strips, and any combination thereof.

54. The method of claim 39 wherein t e module of complementary metal- oxide semiconductor devices comprises a device selected from the group consisting of NFETs, PFETs, Resistors, Capacitors, and any combination thereof.

55. The method of claim 39 wherein the module of complementary metal- oxide semiconductor devices comprises a fully depleted OSFET.

56. A method of preparing an integrated circuit device, the method comprising:

forming a charge trapping layer on a front surface layer of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, a bulk single crystal silicon region, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of at least 100 Ohm-cm, and the charge trapping layer comprises one or more semiconductor layers, wherein each of the one or more semiconductor layers comprise a polycrystalline structure or an amorphous structure and further wherein each of the one or more semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge;

forming a buried oxide layer and a first single crystal silicon device layer, wherein the first single crystal silicon device layer is derived from a first single crystal silicon donor substrate and further wherein the buried oxide layer is in interfacial contact with the charge trapping layer and is positioned between the charge trapping layer and the silicon crystal silicon device layer;

bonding a second single crystal silicon donor substrate to the first single crystal silicon device layer, wherein the second single crystal silicon donor substrate comprises two major, generally parallel surfaces, one of which is a front surface of the second single crystal silicon donor substrate and the other of which is a back surface of the second single ciystal silicon donor substrate, a circumferential edge joining the front and back surfaces of the second single crystal silicon donor substrate, a bulk region of the second single ciystal silicon donor substrate, and a central plane of the second single crystal silicon donor substrate between the front and back sur faces of the second single ciystal silicon donor substrate, and further wherein the front surface of the second single ciystal silicon donor substrate comprises a silicon dioxide layer and the bulk region of the second single crystal silicon donor substrate comprises a cleave plane;

cleaving the second single crystal silicon donor substrate to thereby form a second single crystal silicon device layer;

removing a portion of the second single crystal silicon device layer to thereby expose a portion of the first single crystal silicon device layer;

forming a module of radiofrequency devices in the first single crystal silicon device layer; and

forming a module of complementary metal-oxide semiconductor devices in the second region of the single crystal silicon device layer.

57. The method of claim 56 wherein the single crystal silicon handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

58. The method of claim 57 wherein the single crystal silicon wafer has a bulk resistivity between about 100 Ohm-cm and about 100,000 Ohm-cm.

59. The method of claim 57 wherein the single crystal silicon wafer has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

60. The method of claim 57 wherein the single crystal silicon handle wafer has a bulk resistivity between about 2000 Ohm cm and about 10,000 Ohm-cm.

61. The method of claim 57 wherein the single crystal silicon handle wafer has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

62. The method of claim 56 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 5 micrometers.

63. The method of claim 56 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 3 micrometers.

64. The method of claim 56 wherein the total thickness of the charge trapping layer is between about 0.3 micrometers and about 2 micrometers.

65. The method of claim 56 wherein the charge trapping layer comprises two or more semiconductor layers, wherein each of the two or more semiconductor layers are passivated.

66. The method of claim 56 wherein the buried oxide layer has a thickness between about 0.01 micrometers and about 20 micrometers.

67. The method of claim 56 wherein the buried oxide layer has a thickness between about 0.1 micrometers and about 10 micrometers.

68. The method of claim 56 wherein the buried oxide layer has a thickness between about 0.2 micrometers and about 1 micrometer.

69. The method of claim 56 wherein the single crystal silicon device layer comprises a dopant selected from the group consisting of boron, aisenic, and phosphorus.

70. The method of claim 56 wherein the module of radiofrequency devices comprises a device selected from the group consisting of MOSFETs, Bipolar transistors, resistors, capacitors, inductors, micro-strips, and any combination thereof.

71. The method of claim 56 wherein the module of complementary metal- oxide semiconductor devices comprises a device selected from the group consisting of NFETs, PFETs, Resistors, Capacitors, and any combination thereof.

72. The method of claim 56 wherein the module of complementary metal- oxide semiconductor devices comprises a fully depleted MOSFET.