A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additional variation in clock rate, two or more...http://www.google.es/patents/US7131024?utm_source=gb-gplus-sharePatente US7131024 - Multiple transmit data rates in programmable logic device serial interface
Multiple transmit data rates in programmable logic device serial interface
