An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to...http://www.google.es/patents/US6904571?utm_source=gb-gplus-sharePatente US6904571 - Algorithm and methodology for the polygonalization of sparse circuit schematics
Algorithm and methodology for the polygonalization of sparse circuit schematics
