A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material....http://www.google.es/patents/US6316309?utm_source=gb-gplus-sharePatente US6316309 - Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells
Method of forming self-isolated and self-aligned 4F-square vertical FET ...
