A synchronous DRAM has cell arrays arranged in a matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks are used for time sharing between...http://www.google.es/patents/US5596541?utm_source=gb-gplus-sharePatente US5596541 - Synchronous dynamic random access memory
