A semiconductor memory system with a fully automated built-in refresh control circuitry, comprising a dynamic random access memory cell array, a data transfer gate circuit through which data signals are to be transferred to or from the memory cell array, a data transfer request signal generator to produce...http://www.google.es/patents/US4807196?utm_source=gb-gplus-sharePatente US4807196 - Refresh address counter test control circuit for dynamic random access memory system
Refresh address counter test control circuit for dynamic random access ...
