Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded circuit, a hardware description language (HDL) pin name from an HDL description of the embedded circuit,...http://www.google.es/patents/US7117471?utm_source=gb-gplus-sharePatente US7117471 - Generation of design views having consistent input/output pin definitions
Generation of design views having consistent input/output pin definitions
