A method of manufacturing a semiconductor wafer, which includes performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks,...http://www.google.es/patents/US5457073?utm_source=gb-gplus-sharePatente US5457073 - Multi-level interconnection CMOS devices with SOG
